SuccessChanges

Summary

  1. Fix unneeded semi column (details)
  2. [AArch64][SVE] Add mul/mla/mls lane & dup intrinsics (details)
  3. [AArch64] Fix BTI landing pad generation. (details)
Commit 961aeb7a15584d5e5d9848f7844ecba9a2d608c2 by noreply
Fix unneeded semi column
The file was modifiedlibc/test/src/string/memory_utils/utils_test.cpp
Commit 671cbc1fbba049ec2343cdcff069ce59c0160e31 by kerry.mclaughlin
[AArch64][SVE] Add mul/mla/mls lane & dup intrinsics

Summary:
Implements the following intrinsics:
- @llvm.aarch64.sve.dup
- @llvm.aarch64.sve.mul.lane
- @llvm.aarch64.sve.mla.lane
- @llvm.aarch64.sve.mls.lane

Reviewers: c-rhodes, sdesmalen, dancgr, efriedma, rengolin

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74222
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-scalar-to-vec.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit d5a186a60014dc1a8c979c978cb32aba7ecb9102 by oliver.stannard
[AArch64] Fix BTI landing pad generation.

In some cases BTI landing pad is inserted even compatible instruction
was there already. Meta instruction does not count in this case
therefore skip them in the check for first instructions in the function.

Differential revision: https://reviews.llvm.org/D74492
The file was modifiedllvm/lib/Target/AArch64/AArch64BranchTargets.cpp
The file was modifiedllvm/test/CodeGen/AArch64/branch-target-enforcement.mir