SuccessChanges

Summary

  1. [AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer (details)
  2. [SplitKit] Cope with no live subranges in defFromParent (details)
  3. [SystemZ]  Support bare nop instructions (details)
  4. [MLIR][SPIRV] Support different function control in (de)serialization (details)
  5. [X86] Support Intel Key Locker (details)
  6. [gn build] Port 413577a8790 (details)
  7. [InstCombine] recognizeBSwapOrBitReverseIdiom - assert for correct bit providence indices. NFCI. (details)
  8. [InstCombine] recognizeBSwapOrBitReverseIdiom - recognise zext(bswap(trunc(x))) patterns (PR39793) (details)
  9. [mlir] Added support for rank reducing subviews (details)
  10. [NFC][ARM] Add more LowOverheadLoop tests. (details)
  11. [mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments (details)
  12. [SCEV] Verify that all mapped SCEV AddRecs refer to valid loops. (details)
  13. InstCombine] collectBitParts - cleanup variable names. NFCI. (details)
  14. [InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI. (details)
  15. [RDA] isSafeToDefRegAt: Look at global uses (details)
  16. [InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI. (details)
  17. [InstCombine] Add PR47191 bswap tests (details)
  18. [lldb] Fix FreeBSD Arm Process Plugin build (details)
  19. [VPlan] Change recipes to inherit from VPUser instead of a member var. (details)
  20. [lldb] [Process/NetBSD] Fix operating on ftag register (details)
  21. [InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI. (details)
  22. [InstCombine] Remove %tmp variable names from bswap tests (details)
  23. [InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI. (details)
  24. [clangd] Fix invalid UTF8 when extracting doc comments. (details)
  25. [PowerPC] Remove support for VRSAVE save/restore/update. (details)
  26. [GlobalISel] Fix incorrect setting of ValNo when splitting (details)
  27. Move AffineMapAttr into BaseOps.td (details)
Commit 0249df33fec16b728e2d33cae02f5da4c9f74e38 by Mirko.Brkusanin
[AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer

Check if operand of mul is constant value of one for certain atomic
instructions in order to avoid making unnecessary instructions when
-amdgpu-atomic-optimizer is present.

Differential Revision: https://reviews.llvm.org/D88315
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
Commit cdac4492b4a523a888a013d42ea0a968f684ed59 by jay.foad
[SplitKit] Cope with no live subranges in defFromParent

Following on from D87757 "[SplitKit] Only copy live lanes", it is
possible to split a live range at a point when none of its subranges
are live. This patch handles that case by inserting an implicit def
of the superreg.

Patch by Quentin Colombet!

Differential Revision: https://reviews.llvm.org/D88397
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
The file was addedllvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
Commit 9f5da55f5d9299a76a4dfb67ef0324dbc1900826 by paulsson
[SystemZ]  Support bare nop instructions

Add support of "nop" and "nopr" (without operands) to assembler.

Review: Ulrich Weigand
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.td
The file was modifiedllvm/test/MC/SystemZ/insn-good.s
Commit 8c05c7c8d87c7ab02fca2a789dfcca4976c6601b by georgemitenk0v
[MLIR][SPIRV] Support different function control in (de)serialization

Added support for different function control
in serialization and deserialization.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D88280
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp
The file was modifiedmlir/test/Dialect/SPIRV/Serialization/module.mlir
Commit 413577a8790407d75ba834fa5668c2632fe1851e by xiang1.zhang
[X86] Support Intel Key Locker

Key Locker provides a mechanism to encrypt and decrypt data with an AES key without having access
to the raw key value by converting AES keys into “handles”. These handles can be used to perform the
same encryption and decryption operations as the original AES keys, but they only work on the current
system and only until they are revoked. If software revokes Key Locker handles (e.g., on a reboot),
then any previous handles can no longer be used.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D88398
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-32-att.txt
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-64-intel.txt
The file was addedclang/lib/Headers/keylocker_wide_intrin.h
The file was modifiedllvm/lib/Support/X86TargetParser.cpp
The file was addedllvm/test/CodeGen/X86/keylocker-intrinsics.ll
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedclang/include/clang/Basic/BuiltinsX86.def
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-64-att.txt
The file was modifiedclang/lib/Headers/CMakeLists.txt
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was addedllvm/test/MC/X86/KEYLOCKER/x86-64-keylocker-intel.s
The file was modifiedllvm/lib/Support/Host.cpp
The file was modifiedllvm/include/llvm/Support/X86TargetParser.def
The file was addedllvm/lib/Target/X86/X86InstrKL.td
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/IR/Function.cpp
The file was addedclang/lib/Headers/keylockerintrin.h
The file was modifiedclang/test/Preprocessor/x86_target_features.c
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsX86.td
The file was modifiedclang/lib/Basic/Targets/X86.h
The file was addedclang/test/CodeGen/X86/keylocker.c
The file was modifiedclang/test/Driver/x86-target-features.c
The file was modifiedclang/test/CodeGen/attr-target-x86.c
The file was addedllvm/test/MC/X86/KEYLOCKER/x86-64-keylocker-att.s
The file was modifiedllvm/lib/Target/X86/X86.td
The file was modifiedllvm/lib/Target/X86/X86Subtarget.h
The file was modifiedclang/lib/Basic/Targets/X86.cpp
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-32-intel.txt
The file was addedllvm/test/MC/X86/KEYLOCKER/keylocker-att.s
The file was addedllvm/lib/Target/X86/X86InstrInfo.td.rej
The file was addedllvm/test/MC/X86/KEYLOCKER/keylocker-intel.s
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Headers/immintrin.h
Commit e39d7884a1f5c5c7136ba2e493e9ac313ccc78ed by llvmgnsyncbot
[gn build] Port 413577a8790
The file was modifiedllvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Commit ec3f24d4538d1c262377331c7b35ea66e023cf98 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - assert for correct bit providence indices. NFCI.

As suggested by @spatel on D88316
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit af47d40b9c68744eb66aa2ef779065e946aaa099 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - recognise zext(bswap(trunc(x))) patterns (PR39793)

PR39793 demonstrated an issue where we fail to recognize 'partial' bswap patterns of the lower bytes of an integer source.

In fact, most of this is already in place collectBitParts suitably tags zero bits, so we just need to correctly handle this case by finding the zero'd upper bits and reducing the bswap pattern just to the active demanded bits.

Differential Revision: https://reviews.llvm.org/D88316
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 14088a6f5d1ae597960833a366beb9acee8d65cb by limo
[mlir] Added support for rank reducing subviews

This commit adds support for subviews which enable to reduce resulting rank
by dropping static dimensions of size 1.

Differential Revision: https://reviews.llvm.org/D88534
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/test/IR/core-ops.mlir
The file was modifiedmlir/test/IR/invalid-ops.mlir
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit 3cbd01ddb9372b725dcea3dd5fed21ef5b3d9578 by sam.parker
[NFC][ARM] Add more LowOverheadLoop tests.
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
Commit 0b17d4754a94b7129c2483762acd586783802b12 by limo
[mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments

Current setup for conv op vectorization does not enable user to specify tile
sizes as well as dimensions for vectorization. In this commit we change that by
adding tile sizes as pass arguments. Every dimension with corresponding tile
size > 1 is automatically vectorized.

Differential Revision: https://reviews.llvm.org/D88533
The file was modifiedmlir/test/Conversion/LinalgToVector/linalg-to-vector.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-nwc-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ncdhw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ndhwc-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-call.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nchw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-ncw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nhwc-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-call.mlir
The file was modifiedmlir/test/lib/Transforms/TestConvVectorization.cpp
Commit 0eab9d5823815c6520697f8d725c402c88e5d050 by flo
[SCEV] Verify that all mapped SCEV AddRecs refer to valid loops.

This check helps to guard against cases where expressions referring to
invalidated/deleted loops are not properly invalidated.

The additional check is motivated by the reproducer shared for 8fdac7cb7abb
and I think in general make sense as a sanity check.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D88166
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 05290eead3f95e02700890321ccf6719770f91fe by llvm-dev
InstCombine] collectBitParts - cleanup variable names. NFCI.

Fix a number of WShadow warnings (I was used as the instruction and index......) and fix cases to match style.

Also, replaced the Bit APInt mask check in AND instructions with a direct APInt[] bit check.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 413b4998bd722ab671e29e6dff5d458d1869f39b by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI.

Post-commit feedback on D88316
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 3f88c10a6b25668bb99f5eee7867dcbf37df973c by sam.parker
[RDA] isSafeToDefRegAt: Look at global uses

We weren't looking at global uses of a value, so we could happily
overwrite the register incorrectly.

Differential Revision: https://reviews.llvm.org/D88554
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
Commit 621c6c89627972d52796e64a9476a7d05f22f2cd by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI.

Early out if both pattern matches have failed (or we don't want them). Fix case of bit index iterator (and avoid Wshadow issue).
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 08c5720405d5204ec2329b7f6c561062c7dddee2 by llvm-dev
[InstCombine] Add PR47191 bswap tests
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit f794160c6cb7da4b5ef354a91fe498341f651d36 by emaste
[lldb] Fix FreeBSD Arm Process Plugin build

Add a missing include and some definitions in 769533216666.

Patch by: Brooks Davis

Reviewed by: labath

Differential Revision: https://reviews.llvm.org/D88453
The file was modifiedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.h
Commit d8563654701c79fb9ab28ecf94567d9934baed05 by flo
[VPlan] Change recipes to inherit from VPUser instead of a member var.

Now that VPUser is not inheriting from VPValue, we can take the next
step and turn the recipes that already manage their operands via VPUser
into VPUsers directly. This is another small step towards traversing
def-use chains in VPlan.

This is NFC with respect to the generated code, but makes the interface
more powerful.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
Commit 762e8f9bbdaf43300dbc75637a8bce1ce643cc06 by mgorny
[lldb] [Process/NetBSD] Fix operating on ftag register
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
Commit d5545a8993489ee426b757482a64c9373cf7cf38 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 7fcad5583a12026ce19afe487681753ac633064a by llvm-dev
[InstCombine] Remove %tmp variable names from bswap tests

Appease update_test_checks script that was complaining about potential %TMP clashes
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit c722b3259690d3aad20f31d0ffe6c12b1416bccc by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI.

There doesn't seem to be any good reason for having a separate path for when we bswap/bitreverse at a smaller size than the destination size - so merge these to make the instruction generation a lot clearer.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 216af81c39d1cc4e90af7b991d517c4c7acc912e by sam.mccall
[clangd] Fix invalid UTF8 when extracting doc comments.

Differential Revision: https://reviews.llvm.org/D88567
The file was modifiedclang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CodeCompletionStringsTests.cpp
The file was modifiedclang-tools-extra/clangd/CodeCompletionStrings.cpp
Commit dfb717da1f794c235b81a985a57dc238c82318e6 by sd.fertile
[PowerPC] Remove support for VRSAVE save/restore/update.

After removal of Darwin as a PowerPC subtarget, the VRSAVE
save/restore/spill/update code is no longer needed by any supported
subtarget, so remove it while keeping support for vrsave and related instruction
aliases for inline asm. I've pre-commited tests to document the existing vrsave
handling in relation to @llvm.eh.unwind.init and inline asm usage, as
well as a test which shows a beahviour change on AIX related to
returning vector type as we were wrongly emiting VRSAVE_UPDATE on AIX.
The file was modifiedllvm/lib/Target/PowerPC/README_ALTIVEC.txt
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-vector-return.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
Commit 43d239d0fadb1f8ea297580ca39dfbee96c913c1 by mikael.holmen
[GlobalISel] Fix incorrect setting of ValNo when splitting

Before, for each original argument i, ValNo was set to i + PartIdx, but
ValNo is intended to reflect the index of the value before splitting.
Hence, ValNo should always be set to i and not consider the PartIdx.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D86511
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit f33f8a2b30325d89c4b7daef1b7d11d6da38fd56 by benny.kra
Move AffineMapAttr into BaseOps.td

AffineMapAttr is already part of base, it's just impossible to refer to
it from ODS without pulling in the definition from Affine dialect.

Differential Revision: https://reviews.llvm.org/D88555
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/include/mlir/Dialect/GPU/ParallelLoopMapperAttr.td
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td
The file was removedmlir/include/mlir/Dialect/Affine/IR/AffineOpsBase.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td