SuccessChanges

Summary

  1. [NFC][InstSimplify] Some tests for dropping null check after (details)
  2. [InstCombine] fold extract+insert into identity shuffle (details)
  3. Move prop-sink branch to monorepo. (details)
  4. [X86] Teach materializeVectorConstant to not call (details)
  5. [DAGCombiner][X86][ARM] Teach visitMULO to fold multiplies with 0 to 0 (details)
  6. [X86] Use DAG.getConstant instead of getZeroVector in combinePMULDQ. (details)
  7. [X86] X86DAGToDAGISel::combineIncDecVector(): call getSplatBuildVector() (details)
  8. [InstCombine] add tests for icmp with srem operand; NFC (details)
  9. [InstSimplify] simplifyUnsignedRangeCheck(): if we know that X != 0, (details)
  10. [X86] Remove call to getZeroVector from materializeVectorConstant. Add (details)
  11. [X86] Add a hack to combineVSelectWithAllOnesOrZeros to turn selects (details)
  12. [InstCombine][NFC] Some tests for usub overflow+nonzero check (details)
  13. [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add faux shuffle (details)
Commit 64965430db5706a0b235d52663f1fa466b53eed8 by lebedev.ri
[NFC][InstSimplify] Some tests for dropping null check after
uadd.with.overflow of non-null (PR43246)
https://rise4fun.com/Alive/WRzq
Name: C <= Y && Y != 0  -->  C <= Y  iff C != 0 Pre: C != 0
%y_is_nonnull = icmp ne i64 %y, 0
%no_overflow = icmp ule i64 C, %y
%r = and i1 %y_is_nonnull, %no_overflow
=>
%r = %no_overflow
Name: C <= Y || Y != 0  -->  Y != 0  iff C != 0 Pre: C != 0
%y_is_nonnull = icmp ne i64 %y, 0
%no_overflow = icmp ule i64 C, %y
%r = or i1 %y_is_nonnull, %no_overflow
=>
%r = %y_is_nonnull
Name: C > Y || Y == 0  -->  C > Y  iff C != 0 Pre: C != 0
%y_is_null = icmp eq i64 %y, 0
%overflow = icmp ugt i64 C, %y
%r = or i1 %y_is_null, %overflow
=>
%r = %overflow
Name: C > Y && Y == 0  -->  Y == 0  iff C != 0 Pre: C != 0
%y_is_null = icmp eq i64 %y, 0
%overflow = icmp ugt i64 C, %y
%r = and i1 %y_is_null, %overflow
=>
%r = %y_is_null
https://bugs.llvm.org/show_bug.cgi?id=43246
llvm-svn: 371339
The file was addedllvm/test/Transforms/InstSimplify/redundant-null-check-in-uadd_with_overflow-of-nonnull-ptr.ll
Commit aff5bee35fb36897dd5414a52c11c14d2f858822 by spatel
[InstCombine] fold extract+insert into identity shuffle
This is similar to the existing fold for splats added with: rL365379
If we can adjust the shuffle mask to include another element in an
identity mask (if it changes vector length, that's an extract/insert
subvector operation in the backend), then that can eliminate
extractelement/insertelement pairs in IR.
All targets are expected to lower shuffles with identity masks
efficiently.
llvm-svn: 371340
The file was modifiedllvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
Commit 080ecafdd8b3e990e5ad19202d089c91c9c9b164 by gabor.borsik
Move prop-sink branch to monorepo.
llvm-svn: 371342
The file was modifiedclang/lib/StaticAnalyzer/Checkers/GenericTaintChecker.cpp
The file was modifiedclang/test/Analysis/taint-generic.c
Commit 30837abd9623bf2c8582627d2179828ecf361965 by craig.topper
[X86] Teach materializeVectorConstant to not call
getZeroVector/getOnesVector on the types we already have isel patterns
for.
llvm-svn: 371343
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/fold-load-vec.ll
Commit dac34f52d3f94b4b8716ee8f2cc0c086161d326d by craig.topper
[DAGCombiner][X86][ARM] Teach visitMULO to fold multiplies with 0 to 0
and no carry.
I modified the ARM test to use two inputs instead of 0 so the test
hopefully still tests what was intended.
llvm-svn: 371344
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/ARM/select.ll
The file was modifiedllvm/test/CodeGen/X86/xmulo.ll
Commit 97d41b8917438cb391d3c2c6fc7f5f9a01ff713a by craig.topper
[X86] Use DAG.getConstant instead of getZeroVector in combinePMULDQ.
getZeroVector canonicalizes the type to vXi32, but that's a legalization
action. We should use the most correct type if possible.
llvm-svn: 371345
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 94db67f0e1c3e082fd89a84fa79c6d84631227ba by lebedev.ri
[X86] X86DAGToDAGISel::combineIncDecVector(): call getSplatBuildVector()
manually
As reported in post-commit review of r370327, there is some case where
the code crashes.
As discussed with Craig Topper, the problem is that getConstant()
internally calls getSplatBuildVector(), so we don't insert the constant
itself.
If we do that manually we're good.
llvm-svn: 371346
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/X86/combineIncDecVector-crash.ll
Commit 354a46444ce92be73f3859d93a8c6fb237b9e7eb by spatel
[InstCombine] add tests for icmp with srem operand; NFC
llvm-svn: 371348
The file was modifiedllvm/test/Transforms/InstCombine/icmp-div-constant.ll
Commit 6e2c5c87103d76e03cd6f1c5d297bddcad4cf7e1 by lebedev.ri
[InstSimplify] simplifyUnsignedRangeCheck(): if we know that X != 0,
handle more cases (PR43246)
Summary: This is motivated by D67122 sanitizer check enhancement. That
patch seemingly worsens `-fsanitize=pointer-overflow` overhead from 25%
to 50%, which strongly implies missing folds.
In this particular case, given
``` char* test(char& base, unsigned long offset) {
return &base + offset;
}
``` it will end up producing something like https://godbolt.org/z/LK5-iH
which after optimizations reduces down to roughly
``` define i1 @t0(i8* nonnull %base, i64 %offset) {
%base_int = ptrtoint i8* %base to i64
%adjusted = add i64 %base_int, %offset
%non_null_after_adjustment = icmp ne i64 %adjusted, 0
%no_overflow_during_adjustment = icmp uge i64 %adjusted, %base_int
%res = and i1 %non_null_after_adjustment,
%no_overflow_during_adjustment
ret i1 %res
}
``` Without D67122 there was no `%non_null_after_adjustment`, and in
this particular case we can get rid of the overhead:
Here we add some offset to a non-null pointer, and check that the result
does not overflow and is not a null pointer. But since the base pointer
is already non-null, and we check for overflow, that overflow check will
already catch the null pointer, so the separate null check is redundant
and can be dropped.
Alive proofs: https://rise4fun.com/Alive/WRzq
There are more patterns of "unsigned-add-with-overflow", they are not
handled here, but this is the main pattern, that we currently consider
canonical, so it makes sense to handle it.
https://bugs.llvm.org/show_bug.cgi?id=43246
Reviewers: spatel, nikic, vsk
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits, reames
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67332
llvm-svn: 371349
The file was modifiedllvm/test/Transforms/InstSimplify/redundant-null-check-in-uadd_with_overflow-of-nonnull-ptr.ll
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
Commit 9c119012566c1272c6be2c1b141d6443d67cbc88 by craig.topper
[X86] Remove call to getZeroVector from materializeVectorConstant. Add
isel patterns for zero vectors with all types.
The change to avx512-vec-cmp.ll is a regression, but should be easy to
fix. It occurs because the getZeroVector call was canonicalizing both
sides to the same node, then SimplifySelect was able to simplify it. But
since only called getZeroVector on some VTs this isn't a robust way to
combine this.
The change to vector-shuffle-combining-ssse3.ll is more instructions,
but removes a constant pool load so its unclear if its a regression or
not.
llvm-svn: 371350
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-vec-cmp.ll
Commit 77dd86ee4aaed1ffeedf18c7b8a862c465f415f9 by craig.topper
[X86] Add a hack to combineVSelectWithAllOnesOrZeros to turn selects
with two zero/undef vector inputs into an all zeroes vector.
If the two zero vectors have undefs in different places they won't get
combined by simplifySelect.
This fixes a regression from an earlier commit.
llvm-svn: 371351
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/avx512-vec-cmp.ll
Commit 139a9d6c0e0d872f0f41f94f621c616d8459817a by lebedev.ri
[InstCombine][NFC] Some tests for usub overflow+nonzero check
improvement (PR43251)
https://rise4fun.com/Alive/kHq
https://bugs.llvm.org/show_bug.cgi?id=43251
llvm-svn: 371352
The file was addedllvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
Commit e0ea746215c88a713680c32f4589a918e19f385d by llvm-dev
[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add faux shuffle
support.
This patch decodes target and faux shuffles with getTargetShuffleInputs
- a reduced version of resolveTargetShuffleInputs that doesn't resolve
SM_SentinelZero cases, so we can correctly remove zero vectors if they
aren't demanded.
llvm-svn: 371353
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-mul.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp