SuccessChanges

Summary

  1. [NFC][InstCombine] Fixup test i added in rL371352. (details)
  2. [clangd] Add a new highlighting kind for typedefs (details)
  3. Merge note_ovl_builtin_candidate diagnostics; NFC (details)
  4. AMDGPU/GlobalISel: Remove dead patterns (details)
  5. [ARM] Remove some spurious MVE reduction instructions. (details)
  6. AMDGPU/GlobalISel: Try generated matcher before add/sub code (details)
  7. AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic (details)
  8. [clangd] Use pre-populated mappings for standard symbols (details)
  9. AMDGPU/GlobalISel: Use known bits for selection (details)
  10. [NFC] Add aacps bitfields access test (details)
  11. AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads (details)
  12. AMDGPU/GlobalISel: Select G_PTR_MASK (details)
  13. AMDGPU: Remove code address space predicates (details)
  14. AMDGPU/GlobalISel: Fix regbankselect for uniform extloads (details)
  15. Fix typo in comment noticed in D60295. NFCI. (details)
  16. AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant (details)
  17. LLDB - Simplify GetProgramFileSpec (details)
  18. AMDGPU/GlobalISel: Select atomic loads (details)
  19. [ARM] Fix loads and stores for predicate vectors (details)
  20. [yaml2obj] Simplify p_filesz/p_memsz computing (details)
  21. Revert "[MachineCopyPropagation] Remove redundant copies after TailDup (details)
  22. [clangd] Attempt to fix failing Windows buildbots. (details)
  23. AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC (details)
  24. AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE (details)
  25. [GlobalISel][AArch64] Handle tail calls with non-void return types (details)
  26. [SLP] add test for over-vectorization (PR33958); NFC (details)
  27. AMDGPU: Move MnemonicAlias out of instruction def hierarchy (details)
  28. [mips] Fix decoding of microMIPS JALX instruction (details)
  29. [Remarks] Add parser for bitstream remarks (details)
  30. [X86] Allow _MM_FROUND_CUR_DIRECTION and _MM_FROUND_NO_EXC to be used (details)
  31. [SelectionDAG] Remove ISD::FP_ROUND_INREG (details)
  32. AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsics (details)
  33. [x86] add test for false dependency with minsize (PR43239); NFC (details)
  34. [IfConversion] Correctly handle cases where analyzeBranch fails. (details)
  35. AMDGPU/GlobalISel: Select fmed3 (details)
  36. AMDGPU/GlobalISel: Select llvm.amdgcn.class (details)
  37. [Driver] Add -static-openmp driver option (details)
  38. AMDGPU: Make VReg_1 size be 1 (details)
  39. [TSan] Add interceptors for mach_vm_[de]allocate (details)
  40. AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR v2s16 (details)
  41. Introduce infrastructure for an incremental port of SelectionDAG atomic (details)
  42. [UBSan] Do not overwrite the default print_summary sanitizer option. (details)
  43. [Remarks] Fix warning for uint8_t < 0 comparison (details)
  44. [Driver] Handle default case in refactored addOpenMPRuntime (details)
Commit 59608c0049531758b9cbb3c400a68d597b797bf4 by lebedev.ri
[NFC][InstCombine] Fixup test i added in rL371352.
llvm-svn: 371401
The file was modifiedllvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
Commit e237520a8f5006692e25d7e5da7271f1c9832491 by ibiryukov
[clangd] Add a new highlighting kind for typedefs
Summary: We still attempt to highlight them as underlying types, but
fallback to the generic 'typedef' highlighting kind if the underlying
type is too complicated.
Reviewers: hokein
Reviewed By: hokein
Subscribers: nridge, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67290
llvm-svn: 371402
The file was modifiedclang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp
The file was modifiedclang-tools-extra/clangd/SemanticHighlighting.h
The file was modifiedclang-tools-extra/clangd/SemanticHighlighting.cpp
The file was modifiedclang-tools-extra/clangd/test/semantic-highlighting.test
Commit 783fc95f3eedfb44acbfc1f3f100a5eca83e7359 by sven.vanhaastregt
Merge note_ovl_builtin_candidate diagnostics; NFC
There is no difference between the unary and binary case, so merge them.
llvm-svn: 371403
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaOverload.cpp
Commit 508dff2ce15412a6b9a10a27f16d8c10b6e88c6b by Matthew.Arsenault
AMDGPU/GlobalISel: Remove dead patterns
llvm-svn: 371404
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
Commit 0e48bd24e2120e0a9fbf2bc4896266b43496df3d by simon.tatham
[ARM] Remove some spurious MVE reduction instructions.
The family of 'dual-accumulating' vector multiply-add instructions
(VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
unsigned integer types, and they all have an 'exchange' variant (with an
X in the name) that modifies which pairs of vector lanes in the two
inputs are multiplied together. But there's a clause in the spec that
says that the X variants //don't// operate on unsigned integer types,
only signed. You can have X, or unsigned, or neither, but not both.
We didn't notice that clause when we implemented the MC support for
these instructions, so LLVM believes that things like VMLADAVX.U8 do
exist, contradicting the spec. Here I fix that by conditioning them out
in Tablegen.
In order to do that, I've reversed the nesting order of the Tablegen
multiclasses for those instructions. Previously, the innermost
multiclass generated the X and not-X variants, and the one outside that
generated the A and not-A variants. Now X is done by the outer
multiclass, which allows me to bypass that one when I only want the two
not-X variants.
Changing the multiclass nesting order also changes the names of the
instruction ids unless I make a special effort not to. I decided that
while I was changing them anyway I'd make them look nicer; so now the
instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32, instead
of cumbersome _noacc_noexch suffixes.
The corresponding multiply-subtract instructions are unaffected. Those
don't accept unsigned types at all, either in the spec or in LLVM.
Reviewers: ostannard, dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67214
llvm-svn: 371405
The file was modifiedllvm/test/MC/ARM/mve-reductions.s
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/test/MC/Disassembler/ARM/mve-reductions.txt
Commit d50f937378c3cd0d763198c404687dea97e2734d by Matthew.Arsenault
AMDGPU/GlobalISel: Try generated matcher before add/sub code
This will allow optimization patterns which fold adds away to work.
llvm-svn: 371406
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 8e3bc9b572224023eb8536fe934167524ef68ecd by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic
llvm-svn: 371407
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 8b76709bac33f7edf0764416b4e5874c29f23e70 by ibiryukov
[clangd] Use pre-populated mappings for standard symbols
Summary: This takes ~5% of time when running clangd unit tests.
To achieve this, move mapping of system includes out of
CanonicalIncludes and into a separate class
Reviewers: sammccall, hokein
Reviewed By: sammccall
Subscribers: MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67172
llvm-svn: 371408
The file was modifiedclang-tools-extra/clangd/index/CanonicalIncludes.h
The file was modifiedclang-tools-extra/clangd/ParsedAST.cpp
The file was modifiedclang-tools-extra/clangd/index/CanonicalIncludes.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CanonicalIncludesTests.cpp
The file was modifiedclang-tools-extra/clangd/Preamble.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
The file was modifiedclang-tools-extra/clangd/index/IndexAction.cpp
Commit 2dd088ec7d8bf0804fc00e3583cb0bf10ae5c670 by Matthew.Arsenault
AMDGPU/GlobalISel: Use known bits for selection
llvm-svn: 371409
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
Commit 3c8644666c496e983d725859af61624299da67f1 by diogo.sampaio
[NFC] Add aacps bitfields access test
llvm-svn: 371410
The file was addedclang/test/CodeGen/aapcs-bitfield.c
Commit fdb70301172025ee77d3c77c28e18fd02ba5503f by Matthew.Arsenault
AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads
The pointer is always a VGPR. Also fix hardcoding the pointer size to
64.
llvm-svn: 371411
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Commit c34b4036ffe115c7cc03b9236922e98b78adb8b1 by Matthew.Arsenault
AMDGPU/GlobalISel: Select G_PTR_MASK
llvm-svn: 371412
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit ebbd6e49768271297d17bcecd22eae2128e24e26 by Matthew.Arsenault
AMDGPU: Remove code address space predicates
Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due to
not be reported as legal.
llvm-svn: 371413
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
Commit 02eb308387d73de035492c0ae56ce167eaa97a5f by Matthew.Arsenault
AMDGPU/GlobalISel: Fix regbankselect for uniform extloads
There are no scalar extloads.
llvm-svn: 371414
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Commit 9ede7c03956376105130421c786e1360e948b290 by llvm-dev
Fix typo in comment noticed in D60295. NFCI.
llvm-svn: 371415
The file was modifiedllvm/include/llvm/CodeGen/SwitchLoweringUtils.h
Commit d8409b178ed4b5af52eb82190b5d1c846ed8b63c by Matthew.Arsenault
AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant
loads
llvm-svn: 371416
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit f707dac742f39774aef446f275cc70f43586312a by David CARLIER
LLDB - Simplify GetProgramFileSpec
Reviewers: zturner, emaste
Reviewed By: emaste
Differential Revision: https://reviews.llvm.org/D46518
llvm-svn: 371417
The file was modifiedlldb/source/Host/freebsd/HostInfoFreeBSD.cpp
Commit 63e6d8db1cbfe75142669c55819c655c600f00a5 by Matthew.Arsenault
AMDGPU/GlobalISel: Select atomic loads
A new check for an explicitly atomic MMO is needed to avoid incorrectly
matching pattern for non-atomic loads
llvm-svn: 371418
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
Commit 2b7089949eda508203eb23c835d6a295eb00b46b by david.green
[ARM] Fix loads and stores for predicate vectors
These predicate vectors can usually be loaded and stored with a single
instruction, a VSTR_P0. However this instruction will store the entire
P0 predicate, 16 bits, zeroextended to 32bits. Each lane of the the
v4i1/v8i1/v16i1 representing 4/2/1 bits.
As far as I understand, when llvm says "store this v4i1", it really does
need to store 4 bits (or 8, that being the size of a byte, with this
bottom 4 as the interesting bits). For example a bitcast from a v8i1 to
a i8 is defined as a store followed by a load, which is how the code is
expanded.
So this instead lowers the v4i1/v8i1 load/store through some shuffles to
get the bits into the correct positions. This, as you might imagine, is
not as efficient as a single instruction. But I believe it is needed for
correctness. v16i1 equally should not load/store 32bits, only storing
the 16bits of data. Stack loads/stores are still using the VSTR_P0 (as
can be seen by the test not changing). This is fine as they are
self-consistent, it is only "externally observable loads/stores" (from
our point of view) that need to be corrected.
Differential revision: https://reviews.llvm.org/D67085
llvm-svn: 371419
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-store.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-load.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit c28f3e6e2c3ef1323ed18d4c485681bb4ff72ced by maskray
[yaml2obj] Simplify p_filesz/p_memsz computing
This fixes a bug as well. When "FileSize:" (p_filesz) is specified and
different from the actual value, the following code probably should not
use PHeader.p_filesz:
  if (SHeader->sh_offset == PHeader.p_offset + PHeader.p_filesz)
   PHeader.p_memsz += SHeader->sh_size;
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D67256
llvm-svn: 371420
The file was modifiedllvm/test/tools/yaml2obj/program-header-size-offset.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
Commit d9c4060bd5c9e6c24a96cd7e4501be30301dad9d by gribozavr
Revert "[MachineCopyPropagation] Remove redundant copies after TailDup
via machine-cp"
This reverts commit 371359. I'm suspecting a miscompile, I posted a
reproducer to https://reviews.llvm.org/D65267.
llvm-svn: 371421
The file was modifiedllvm/test/CodeGen/X86/mul-i512.ll
The file was modifiedllvm/lib/CodeGen/MachineCopyPropagation.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
The file was modifiedllvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
Commit 6d7fba6aae28e313ba3e457ad9eff13b5e541204 by ibiryukov
[clangd] Attempt to fix failing Windows buildbots.
The assertion is failing on Windows, probably because path separator is
different.
For the failure see:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/28072/steps/test/logs/stdio
llvm-svn: 371422
The file was modifiedclang-tools-extra/clangd/index/CanonicalIncludes.cpp
Commit 182f9248e8f2c11e5aeeb08263c5b56dbf1ea9c6 by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC
Treat this as legal on gfx9 since it can use S_PACK_* instructions for
this.
This isn't used by anything yet. The same will probably apply to 16-bit
G_BUILD_VECTOR without the trunc.
llvm-svn: 371423
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector-trunc.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 64ecca90d4290f670b58111cc46e63b3aa9b72f5 by Matthew.Arsenault
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE
Handle the simple case that lowers to a constant.
llvm-svn: 371424
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-size.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
Commit bfb00e3d536e4a907f257684eba7836951677864 by Jessica Paquette
[GlobalISel][AArch64] Handle tail calls with non-void return types
Just return once you emit the call, which is exactly what SelectionDAG
does in this situation.
Update call-translator-tail-call.ll.
Also update dllimport.ll to show that we tail call here in GISel again.
Add
-verify-machineinstrs to the GISel line too, to defend against verifier
failures.
Differential revision: https://reviews.llvm.org/D67282
llvm-svn: 371425
The file was modifiedllvm/test/CodeGen/AArch64/dllimport.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
Commit c0728eac15b416206a715f4ee84e5956aa169c91 by spatel
[SLP] add test for over-vectorization (PR33958); NFC
llvm-svn: 371426
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
Commit d2a9516a6d08c3edd7c5484f4d10f4b38b48c9d6 by Matthew.Arsenault
AMDGPU: Move MnemonicAlias out of instruction def hierarchy
Unfortunately MnemonicAlias defines a "Predicates" field just like an
instruction or pattern, with a somewhat different interpretation.
This ends up overriding the intended Predicates set by PredicateControl
on the pseudoinstruction defintions with an empty list. This allowed
incorrectly selecting instructions that should have been rejected due to
the SubtargetPredicate from patterns on the instruction definition.
This does remove the divergent predicate from the 64-bit shift patterns,
which were already not used for the 32-bit shift, so I'm not sure what
the point was. This also removes a second, redundant copy of the 64-bit
divergent patterns.
llvm-svn: 371427
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOPInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
Commit 56e4ea2bff9eb2f43b20a68951e6263ad3c9022f by simon
[mips] Fix decoding of microMIPS JALX instruction
microMIPS jump and link exchange instruction stores a target in a
26-bits field. Despite other microMIPS JAL instructions these bits are
target address shifted right 2 bits [1]. The patch fixes the JALX
instruction decoding and uses 2-bit shift.
[1] MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set
Differential Revision: https://reviews.llvm.org/D67320
llvm-svn: 371428
The file was modifiedlld/test/ELF/mips-micro-cross-calls.s
The file was modifiedllvm/lib/Target/Mips/MicroMipsInstrInfo.td
The file was modifiedllvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
The file was modifiedllvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
The file was modifiedllvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
Commit a85d9ef11ae3dd5c840b1087555b04bedc304113 by francisvm
[Remarks] Add parser for bitstream remarks
The bitstream remark serializer landed in r367372.
This adds a bitstream remark parser that parser bitstream remark files
to llvm::remarks::Remark objects through the RemarkParser interface.
A few interesting things to point out:
* There are parsing helpers to parse the different types of blocks
* The main parsing helper allows us to parse remark metadata and open an
external file containing the encoded remarks
* This adds a dependency from the Remarks library to the BitstreamReader
library
* The testing strategy is to create a remark entry through YAML, parse
it, serialize it to bitstream, parse that back and compare the objects.
* There are close to no tests for malformed bitstream remarks, due to
the lack of textual format for the bitstream format.
* This adds a new C API for parsing bitstream remarks:
LLVMRemarkParserCreateBitstream.
* This bumps the REMARKS_API_VERSION to 1.
Differential Revision: https://reviews.llvm.org/D67134
llvm-svn: 371429
The file was modifiedllvm/lib/Remarks/LLVMBuild.txt
The file was modifiedllvm/unittests/Remarks/CMakeLists.txt
The file was modifiedllvm/lib/Remarks/RemarkParser.cpp
The file was addedllvm/include/llvm/Remarks/BitstreamRemarkParser.h
The file was addedllvm/lib/Remarks/BitstreamRemarkParser.cpp
The file was modifiedllvm/include/llvm/Bitstream/BitstreamReader.h
The file was modifiedllvm/include/llvm-c/Remarks.h
The file was addedllvm/unittests/Remarks/BitstreamRemarksParsingTest.cpp
The file was modifiedllvm/lib/Remarks/CMakeLists.txt
The file was modifiedllvm/tools/remarks-shlib/Remarks.exports
The file was addedllvm/lib/Remarks/BitstreamRemarkParser.h
Commit ce2cb0f09e7d66f34e5f2110bfcd9e3dff60feaa by craig.topper
[X86] Allow _MM_FROUND_CUR_DIRECTION and _MM_FROUND_NO_EXC to be used
together on instructions that only support SAE and not embedded
rounding.
Current for SAE instructions we only allow _MM_FROUND_CUR_DIRECTION(bit
2) or _MM_FROUND_NO_EXC(bit 3) to be used as the immediate passed to the
inrinsics. But these instructions don't perform rounding so
_MM_FROUND_CUR_DIRECTION is just sort of a default placeholder when you
don't want to suppress exceptions. Using _MM_FROUND_NO_EXC by itself is
really bit equivalent to (_MM_FROUND_NO_EXC | _MM_FROUND_TO_NEAREST_INT)
since _MM_FROUND_TO_NEAREST_INT is 0. Since we aren't rounding on these
instructions we should also accept (_MM_FROUND_CUR_DIRECTION |
_MM_FROUND_NO_EXC) as equivalent to (_MM_FROUND_NO_EXC). icc allows
this, but gcc does not.
Differential Revision: https://reviews.llvm.org/D67289
llvm-svn: 371430
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics.ll
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/test/Sema/builtins-x86.c
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 5ebd0a6e88a5c70805ec5077289e602c8e16a83f by craig.topper
[SelectionDAG] Remove ISD::FP_ROUND_INREG
I don't think anything in tree creates this node. So all of this code
appears to be dead.
Code coverage agrees
http://lab.llvm.org:8080/coverage/coverage-reports/llvm/coverage/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.html
Differential Revision: https://reviews.llvm.org/D67312
llvm-svn: 371431
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/docs/ReleaseNotes.rst
Commit 6ebf605851db3627bdf51a89b0a36147729014c2 by Matthew.Arsenault
AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsics
This enables GlobalISel to handle various intrinsics. The custom node
pattern will be ignored, and the intrinsic will work. This will also
allow SelectionDAG to directly select the intrinsics, but as they are
all custom lowered to the nodes, this ends up leaving dead code in the
table.
Eventually either GlobalISel should add the equivalent of custom nodes
equivalent, or intrinsics should be directly used. These each have
different tradeoffs.
There are a few more to handle, but these are easy to handle ones. Some
others fail for other reasons.
llvm-svn: 371432
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
Commit c195bde3d4db7bd5746aecd9cbdf6c386968e660 by spatel
[x86] add test for false dependency with minsize (PR43239); NFC
llvm-svn: 371433
The file was modifiedllvm/test/CodeGen/X86/sqrt-partial.ll
Commit 79f0d3a6e58b80e38040c9ef639431a268422058 by efriedma
[IfConversion] Correctly handle cases where analyzeBranch fails.
If analyzeBranch fails, on some targets, the out parameters point to
some blocks in the function. But we can't use that information, so make
sure to clear it out.  (In some places in IfConversion, we assume that
any block with a TrueBB is analyzable.)
The change to the testcase makes it trigger a bug on builds without this
fix: IfConvertDiamond tries to perform a followup "merge" operation,
which isn't legal, and we somehow end up with a branch to a deleted MBB.
I'm not sure how this doesn't crash the compiler.
Differential Revision: https://reviews.llvm.org/D67306
llvm-svn: 371434
The file was modifiedllvm/lib/CodeGen/IfConversion.cpp
The file was modifiedllvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
Commit d6c1f5bb154a0b524b92d15b99a882d654f906ce by Matthew.Arsenault
AMDGPU/GlobalISel: Select fmed3
llvm-svn: 371435
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 77e3e9cafd9642375132e7bb0b13be415872b531 by Matthew.Arsenault
AMDGPU/GlobalISel: Select llvm.amdgcn.class
Also fixes missing SubtargetPredicate on f16 class instructions.
llvm-svn: 371436
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/VOPCInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
Commit d60ff75b562b56177dfe9337f123637bf904f884 by pirama
[Driver] Add -static-openmp driver option
Summary: For Gnu, FreeBSD and NetBSD, this option forces linking with
the static OpenMP host runtime (similar to -static-libgcc and
-static-libstdcxx).
Android's NDK will start the shared OpenMP runtime in addition to the
static libomp.  In this scenario, the linker will prefer to use the
shared library by default.  Add this option to enable linking with the
static libomp.
Reviewers: Hahnfeld, danalbert, srhines, joerg, jdoerfert
Subscribers: guansong, cfe-commits
Tags: #clang
Fixes https://github.com/android-ndk/ndk/issues/1028
Differential Revision: https://reviews.llvm.org/D67200
llvm-svn: 371437
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.h
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp
The file was modifiedclang/lib/Driver/ToolChains/NetBSD.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Driver/ToolChains/FreeBSD.cpp
The file was modifiedclang/lib/Driver/ToolChains/Gnu.cpp
The file was modifiedclang/test/Driver/fopenmp.c
Commit 8bc05d7d603e3964c811fd65235f276858104fbb by Matthew.Arsenault
AMDGPU: Make VReg_1 size be 1
This was getting chosen as the preferred 32-bit register class based on
how TableGen selects subregister classes.
llvm-svn: 371438
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
The file was modifiedllvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
Commit fc910c507e447ae08ca8424ab16353f5371a2e1b by jlettner
[TSan] Add interceptors for mach_vm_[de]allocate
I verified that the test is red without the interceptors.
rdar://40334350
Reviewed By: kubamracek, vitalybuka
Differential Revision: https://reviews.llvm.org/D66616
llvm-svn: 371439
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
The file was addedcompiler-rt/test/tsan/Darwin/mach_vm_allocate.c
The file was modifiedcompiler-rt/lib/tsan/CMakeLists.txt
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors.cpp
The file was addedcompiler-rt/lib/tsan/rtl/tsan_interceptors_mach_vm.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
Commit a0933e6df759787ab7ce4622f693d9b8df774536 by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR v2s16
Handle it the same way as G_BUILD_VECTOR_TRUNC. Arguably only
G_BUILD_VECTOR_TRUNC should be legal for this, but G_BUILD_VECTOR will
probably be more convenient in most cases.
llvm-svn: 371440
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 20aafa31569b5157e792daa8860d71dd0df8a53a by listmail
Introduce infrastructure for an incremental port of SelectionDAG atomic
load/store handling
This is the first patch in a large sequence. The eventual goal is to
have unordered atomic loads and stores - and possibly ordered atomics as
well - handled through the normal ISEL codepaths for loads and stores.
Today, there handled w/instances of AtomicSDNodes. The result of which
is that all transforms need to be duplicated to work for unordered
atomics. The benefit of the current design is that it's harder to
introduce a silent miscompile by adding an transform which forgets about
atomicity.  See the thread on llvm-dev titled "FYI: proposed changes to
atomic load/store in SelectionDAG" for further context.
Note that this patch is NFC unless the experimental flag is set.
The basic strategy I plan on taking is:
    introduce infrastructure and a flag for testing (this patch)
   Audit uses of isVolatile, and apply isAtomic conservatively*
   piecemeal conservative* update generic code and x86 backedge code in
individual reviews w/tests for cases which didn't check volatile, but
can be found with inspection
   flip the flag at the end (with minimal diffs)
   Work through todo list identified in (2) and (3) exposing performance
ops
(*) The "conservative" bit here is aimed at minimizing the number of
diffs involved in (4). Ideally, there'd be none. In practice, getting it
down to something reviewable by a human is the actual goal. Note that
there are (currently) no paths which produce LoadSDNode or StoreSDNode
with atomic MMOs, so we don't need to worry about preserving any
behaviour there.
We've taken a very similar strategy twice before with success - once at
IR level, and once at the MI level (post ISEL).
Differential Revision: https://reviews.llvm.org/D66309
llvm-svn: 371441
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
Commit 9508738cd1d4ad179021314bfe54f2a02cb029cd by mmoroz
[UBSan] Do not overwrite the default print_summary sanitizer option.
Summary: This option is true by default in sanitizer common. The default
false value was added a while ago without any reasoning in
https://github.com/llvm-mirror/compiler-rt/commit/524e934112a593ac081bf2b05aa0d60a67987f05
so, presumably it's safe to remove for consistency.
Reviewers: hctim, samsonov, morehouse, kcc, vitalybuka
Reviewed By: hctim, samsonov, vitalybuka
Subscribers: delcypher, #sanitizers, llvm-commits, kcc
Tags: #llvm, #sanitizers
Differential Revision: https://reviews.llvm.org/D67193
llvm-svn: 371442
The file was addedcompiler-rt/test/ubsan/TestCases/Misc/print_summary.c
The file was modifiedcompiler-rt/lib/ubsan/ubsan_flags.cpp
Commit 3d85013b63ea391ea966358bd5cbd24a78170c94 by francisvm
[Remarks] Fix warning for uint8_t < 0 comparison
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/19109/steps/build-stage1-compiler/logs/stdio
llvm-svn: 371443
The file was modifiedllvm/lib/Remarks/BitstreamRemarkParser.cpp
Commit ff49a52cf3dd785b7e93dd2c9a89b6cf8d3743d4 by pirama
[Driver] Handle default case in refactored addOpenMPRuntime
Summary: Appease failed builds (due to -Werror and -Wswitch) where
OMPRT_Unknown is not handled in the switch statement (even though it's
handled by the early exit).
This fixes -Wswitch triggered by r371442.
Reviewers: srhines, danalbert, jdoerfert
Subscribers: guansong, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67364
llvm-svn: 371444
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp