SuccessChanges

Summary

  1. [zorg] Pass "-DLLVM_POLLY_LINK_INTO_TOOLS=ON" in getPollyBuildFactory (details)
Commit 6ad01600c4e27d7238564346976df22204a5014b by efriedma
[zorg] Pass "-DLLVM_POLLY_LINK_INTO_TOOLS=ON" in getPollyBuildFactory
The default here was changed recently, and the
aosp-O3-polly-before-vectorizer-unprofitable builder assumes polly is
linked into clang.
Differential Revision: https://reviews.llvm.org/D72646
The file was modifiedzorg/buildbot/builders/PollyBuilder.py (diff)

Summary

  1. make -fmodules-codegen and -fmodules-debuginfo work also with PCHs (details)
  2. [mlir] Enable printing of FuncOp in the generic form. (details)
  3. [OPENMP]Do not use RTTI by default for NVPTX devices. (details)
  4. [mlir] Refactor ModuleState into AsmState and expose it to users. (details)
  5. [remark][diagnostics] Using clang diagnostic handler for IR input files (details)
  6. [mlir][spirv] Properly support SPIR-V conversion target (details)
  7. [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. (details)
  8. [LIBOMPTARGET] Do not increment/decrement the refcount for "declare (details)
  9. Fix windows bot failures in c410adb092c9cb51ddb0b55862b70f2aa8c5b16f (details)
  10. [libcxx] Use C11 thread API on Fuchsia (details)
  11. [mlir] : Fix ViewOp shape folder for identity affine maps (details)
  12. [X86] Swap the 0 and the fudge factor in the constant pool for the (details)
  13. [X86] Drop an unneeded FIXME. NFC (details)
  14. [amdgpu] Fix typos in a test case. (details)
  15. [Win64] Handle FP arguments more gracefully under -mno-sse (details)
  16. Allow /D flags absent during PCH creation under msvc-compat (details)
  17. [X86] ABI compat bugfix for MSVC vectorcall (details)
  18. [Concepts] Type Constraints (details)
  19. [BranchAlign] Add master --x86-branches-within-32B-boundaries flag (details)
  20. DWARFDebugLine.cpp: Restore LF line endings (details)
  21. Modify test to use -S instead of -c so that it works when an external (details)
  22. PR44540: Prefer an inherited default constructor over an initializer (details)
  23. CMake: Make most target symbols hidden by default (details)
  24. Relax the rules around objc_alloc and objc_alloc_init optimizations. (details)
  25. [PowerPC] Fix powerpcspe subtarget enablement in llvm backend (details)
Commit cbc9d22e49b434b6ceb2eb94b67079d02e0a7b74 by l.lunak
make -fmodules-codegen and -fmodules-debuginfo work also with PCHs
Allow to build PCH's (with -building-pch-with-obj and the extra .o file)
with -fmodules-codegen -fmodules-debuginfo to allow emitting shared code
into the extra .o file, similarly to how it works with modules. A bit of
a misnomer, but the underlying functionality is the same. This saves up
to 20% of build time here.
Differential Revision: https://reviews.llvm.org/D69778
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was modifiedclang/lib/Serialization/ASTWriter.cpp
The file was modifiedclang/lib/Serialization/ASTReaderDecl.cpp
The file was modifiedclang/lib/Serialization/ASTWriterDecl.cpp
The file was modifiedclang/test/Modules/Inputs/codegen-flags/foo.h
The file was addedclang/test/PCH/codegen.cpp
Commit 20c6e0749461147df19a3b126d1a48106c63c351 by riverriddle
[mlir] Enable printing of FuncOp in the generic form.
Summary: This was previously disabled as FunctionType TypeAttrs could
not be roundtripped in the IR. This has been fixed, so we can now
generically print FuncOp.
Depends On D72429
Reviewed By: jpienaar, mehdi_amini
Differential Revision: https://reviews.llvm.org/D72642
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/test/IR/wrapping_op.mlir
Commit 23058f9dd4d7e18239fd63b6da52549514b45fda by a.bataev
[OPENMP]Do not use RTTI by default for NVPTX devices.
NVPTX does not support RTTI, so disable it by default.
The file was addedclang/test/Driver/openmp-offload-gpu.cpp
The file was modifiedclang/lib/Driver/ToolChain.cpp
Commit fa9dd8336bbd1167926f93fe2018d0c47839d5d6 by riverriddle
[mlir] Refactor ModuleState into AsmState and expose it to users.
Summary: This allows for users to cache printer state, which can be
costly to recompute. Each of the IR print methods gain a new overload
taking this new state class.
Depends On D72293
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D72294
The file was modifiedmlir/include/mlir/IR/Block.h
The file was modifiedmlir/include/mlir/IR/Operation.h
The file was addedmlir/include/mlir/IR/AsmState.h
The file was modifiedmlir/include/mlir/IR/Value.h
The file was modifiedmlir/include/mlir/IR/Module.h
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/include/mlir/IR/OpDefinition.h
Commit 60d39479221d6bc09060f7816bcd7c54eb286603 by xur
[remark][diagnostics] Using clang diagnostic handler for IR input files
For IR input files, we currently use LLVM diagnostic handler even the
compilation is from clang. As a result, we are not able to use -Rpass to
get the transformation reports. Some warnings are not handled properly
either: We found many mysterious warnings in our ThinLTO backend
compilations in SamplePGO and CSPGO. An example of the warning:
"warning: net/proto2/public/metadata_lite.h:51:21: 0.02% (1 / 4999)"
This turns out to be a warning by Wmisexpect, which is supposed to be
filtered out by default. But since the filter is in clang's diagnostic
hander, we emit these incomplete warnings from LLVM's diagnostic
handler.
This patch uses clang diagnostic handler for IR input files. We create a
fake backendconsumer just to install the diagnostic handler.
With this change, we will have proper handling of all the warnings and
we can use -Rpass* options in IR input files compilation. Also note that
with is patch, LLVM's diagnostic options, like
"-mllvm -pass-remarks=*", are no longer be able to get optimization
remarks.
Differential Revision: https://reviews.llvm.org/D72523
The file was modifiedclang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
The file was addedclang/test/CodeGen/thinlto-clang-diagnostic-handler-in-be.c
The file was addedclang/test/CodeGen/Inputs/thinlto_expect1.proftext
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
The file was addedclang/test/CodeGen/Inputs/thinlto_expect2.proftext
Commit 47c6ab2b97773ee5fb360fc093a5824be64b8c68 by antiagainst
[mlir][spirv] Properly support SPIR-V conversion target
This commit defines a new SPIR-V dialect attribute for specifying a
SPIR-V target environment. It is a dictionary attribute containing the
SPIR-V version, supported extension list, and allowed capability list. A
SPIRVConversionTarget subclass is created to take in the target
environment and sets proper dynmaically legal ops by querying the op
availability interface of SPIR-V ops to make sure they are available in
the specified target environment. All existing conversions targeting
SPIR-V is changed to use this SPIRVConversionTarget. It probes whether
the input IR has a `spv.target_env` attribute, otherwise, it uses the
default target environment: SPIR-V 1.0 with Shader capability and no
extra extensions.
Differential Revision: https://reviews.llvm.org/D72256
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVLowering.h
The file was modifiedmlir/lib/Dialect/SPIRV/Transforms/LowerABIAttributesPass.cpp
The file was addedmlir/test/Dialect/SPIRV/target-env.mlir
The file was modifiedmlir/test/Dialect/SPIRV/target-and-abi.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/TargetAndABI.td
The file was modifiedmlir/docs/Dialects/SPIR-V.md
The file was modifiedmlir/lib/Dialect/SPIRV/TargetAndABI.cpp
The file was modifiedmlir/include/mlir/Dialect/SPIRV/TargetAndABI.h
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.cpp
The file was modifiedmlir/test/Dialect/SPIRV/TestAvailability.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVDialect.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVLowering.cpp
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.cpp
Commit 01a4b83154760ea286117ac4de9576b8a215cb8d by michael.hliao
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.
Summary:
- `dead-mi-elimination` assumes MIR in the SSA form and cannot be
arranged after phi elimination or DeSSA. It's enhanced to handle the
dead register definition by skipping use check on it. Once a register
def is `dead`, all its uses, if any, should be `undef`.
- Re-arrange the DIE in RA phase for AMDGPU by placing it directly after
`detect-dead-lanes`.
- Many relevant tests are refined due to different register assignment.
Reviewers: rampitec, qcolombet, sunfish
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl,
dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72709
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
The file was removedllvm/test/CodeGen/AMDGPU/dead-mi-use-same-intr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
The file was addedllvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
The file was modifiedllvm/lib/CodeGen/DeadMachineInstructionElim.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/loop_break.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/select.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/idot8u.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/bswap.ll
Commit e244145ab08ae79ea3d22c2fe479ec084dbd7742 by georgios.rokos
[LIBOMPTARGET] Do not increment/decrement the refcount for "declare
target" objects
The reference counter for global objects marked with declare target is
INF. This patch prevents the runtime from incrementing /decrementing INF
refcounts. Without it, the map(delete: global_object) directive actually
deallocates the global on the device. With this patch, such a directive
becomes a no-op.
Differential Revision: https://reviews.llvm.org/D72525
The file was modifiedopenmp/libomptarget/src/omptarget.cpp
The file was modifiedopenmp/libomptarget/src/device.h
The file was addedopenmp/libomptarget/test/mapping/delete_inf_refcount.c
The file was modifiedopenmp/libomptarget/src/device.cpp
Commit c9ee5e996e3c89a751a35e8b771870e0ec24f3c0 by xur
Fix windows bot failures in c410adb092c9cb51ddb0b55862b70f2aa8c5b16f
(clang diagnostic handler for IR input files)
The file was modifiedclang/test/CodeGen/thinlto-clang-diagnostic-handler-in-be.c
Commit ab9aefee9fa09957d1a3e76fcc47abda0d002255 by phosek
[libcxx] Use C11 thread API on Fuchsia
On Fuchsia, pthread API is emulated on top of C11 thread API. Using C11
thread API directly is more efficient.
While this implementation is only used by Fuchsia at the moment, it's
not Fuchsia specific, and could be used by other platforms that use C11
threads rather than pthreads in the future.
Differential Revision: https://reviews.llvm.org/D64378
The file was modifiedlibcxx/include/__config
The file was modifiedlibcxx/include/__threading_support
Commit ab035647061272b7efa39364c42e48972cebc0ab by ataei
[mlir] : Fix ViewOp shape folder for identity affine maps
Summary: Fix the ViewOpShapeFolder in case of no affine mapping
associated with a Memref construct identity mapping.
Reviewers: nicolasvasilache
Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen,
antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72735
The file was modifiedmlir/lib/Dialect/StandardOps/Ops.cpp
The file was modifiedmlir/test/Transforms/canonicalize.mlir
Commit 57eb56b83926675dd8a554fc8a8e28ee57278f90 by craig.topper
[X86] Swap the 0 and the fudge factor in the constant pool for the
32-bit mode i64->f32/f64/f80 uint_to_fp algorithm.
This allows us to generate better code for selecting the fixup to load.
Previously when the sign was set we had to load offset 0. And when it
was clear we had to load offset 4. This required a testl, setns, zero
extend, and finally a mul by 4. By switching the offsets we can just
shift the sign bit into the lsb and multiply it by 4.
The file was modifiedllvm/test/CodeGen/X86/uint64-to-float.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
The file was modifiedllvm/test/CodeGen/X86/fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/half.ll
The file was modifiedllvm/test/CodeGen/X86/pr15309.ll
The file was modifiedllvm/test/CodeGen/X86/pr44396.ll
The file was modifiedllvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
The file was modifiedllvm/test/CodeGen/X86/vec-strict-inttofp-128.ll
The file was modifiedllvm/test/CodeGen/X86/fp-cvt.ll
The file was modifiedllvm/test/CodeGen/X86/vec-strict-inttofp-512.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/fildll.ll
The file was modifiedllvm/test/CodeGen/X86/scalar-int-to-fp.ll
The file was modifiedllvm/test/CodeGen/X86/fp80-strict-scalar.ll
The file was modifiedllvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
Commit 76291e1158c2aedddfe0be0ea69452ea6dc2db24 by craig.topper
[X86] Drop an unneeded FIXME. NFC
The extload on X87 is free.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 65c8abb14e77b28d8357c52dddb8e0a6b12b4ba2 by michael.hliao
[amdgpu] Fix typos in a test case.
- There are typos introduced due to merge.
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
Commit 40cd26c7008183e01d8276396339aea2a99d83d7 by rnk
[Win64] Handle FP arguments more gracefully under -mno-sse
Pass small FP values in GPRs or stack memory according the the normal
convention. This is what gcc -mno-sse does on Win64.
I adjusted the conditions under which we emit an error to check if the
argument or return value would be passed in an XMM register when SSE is
disabled. This has a side effect of no longer emitting an error for FP
arguments marked 'inreg' when targetting x86 with SSE disabled. Our
calling convention logic was already assigning it to FP0/FP1, and then
we emitted this error. That seems unnecessary, we can ignore 'inreg' and
compile it without SSE.
Reviewers: jyknight, aemerson
Differential Revision: https://reviews.llvm.org/D70465
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was addedllvm/test/CodeGen/X86/no-sse-win64.ll
The file was modifiedllvm/lib/Target/X86/X86CallingConv.td
The file was addedllvm/test/CodeGen/X86/no-sse-x86.ll
The file was removedllvm/test/CodeGen/X86/nosse-error2.ll
Commit 0f9cf42facaf9eff47dc0b9eb7e6ed8803d3bc3b by rnk
Allow /D flags absent during PCH creation under msvc-compat
Summary: Before this patch adding a new /D flag when compiling a source
file that consumed a PCH with clang-cl would issue a diagnostic and then
fail.  With the patch, the diagnostic is still issued but the definition
is accepted.  This matches the msvc behavior.  The fuzzy-pch-msvc.c is a
clone of the existing fuzzy-pch.c tests with some msvc specific rework.
msvc diagnostic:
warning C4605: '/DBAR=int' specified on current command line, but was
not specified when precompiled header was built
Output of the CHECK-BAR test prior to the code change:
<built-in>(1,9): warning: definition of macro 'BAR' does not match
definition in precompiled header [-Wclang-cl-pch]
#define BAR int
         ^
D:\repos\llvm\llvm-project\clang\test\PCH\fuzzy-pch-msvc.c(12,1):
error: unknown type name 'BAR'
BAR bar = 17;
^
D:\repos\llvm\llvm-project\clang\test\PCH\fuzzy-pch-msvc.c(23,4):
error: BAR was not defined
#  error BAR was not defined
    ^
1 warning and 2 errors generated.
Reviewers: rnk, thakis, hans, zturner
Subscribers: mikerice, aganea, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72405
The file was addedclang/test/PCH/ms-pch-macro.c
The file was modifiedclang/lib/Lex/PPDirectives.cpp
Commit 8e780252a7284be45cf1ba224cabd884847e8e92 by rnk
[X86] ABI compat bugfix for MSVC vectorcall
Summary: Before this change, X86_32ABIInfo::classifyArgument would be
called twice on vector arguments to vectorcall functions. This function
has side effects to track GPR register usage, and this would lead to
incorrect GPR usage in some cases.  The specific case I noticed is from
running out of XMM registers with mixed FP and vector arguments and no
aggregates of any kind. Consider this prototype:
  void __vectorcall vectorcall_indirect_vec(
     double xmm0, double xmm1, double xmm2, double xmm3, double xmm4,
     __m128 xmm5,
     __m128 ecx,
     int edx,
     __m128 mem);
classifyArgument has no effects when called on a plain FP type, but when
called on a vector type, it modifies FreeRegs to model GPR consumption.
However, this should not happen during the vector call first pass.
I refactored the code to unify vectorcall HVA logic with regcall HVA
logic. The conventions pass HVAs in registers differently (expanded vs.
not expanded), but if they do not fit in registers, they both pass them
indirectly by address.
Reviewers: erichkeane, craig.topper
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72110
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedclang/include/clang/CodeGen/CGFunctionInfo.h
The file was modifiedclang/test/CodeGen/vectorcall.c
Commit ff1e0fce817e01f0288fad6a2607dd173180aabd by saar
[Concepts] Type Constraints
Add support for type-constraints in template type parameters. Also add
support for template type parameters as pack expansions (where the type
constraint can now contain an unexpanded parameter pack).
Differential Revision: https://reviews.llvm.org/D44352
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.decl/class-template-decl.cpp
The file was modifiedclang/test/SemaTemplate/ms-delayed-default-template-args.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was addedclang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
The file was modifiedclang/include/clang/AST/RecursiveASTVisitor.h
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/lib/AST/DeclPrinter.cpp
The file was modifiedclang/lib/Parse/ParseTemplate.cpp
The file was addedclang/test/SemaTemplate/instantiate-expanded-type-constraint.cpp
The file was addedclang/test/Parser/cxx2a-constrained-template-param.cpp
The file was addedclang/test/CXX/temp/temp.param/p10-2a.cpp
The file was addedclang/test/CXX/temp/temp.constr/temp.constr.decl/p3.cpp
The file was modifiedclang/tools/libclang/CIndex.cpp
The file was modifiedclang/lib/Serialization/ASTReaderStmt.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Parse/ParseDecl.cpp
The file was modifiedclang/include/clang/Basic/TokenKinds.def
The file was modifiedclang/lib/Parse/ParseExprCXX.cpp
The file was addedclang/test/Parser/cxx2a-constrained-template-param-with-partial-id.cpp
The file was modifiedclang/lib/AST/ASTImporter.cpp
The file was modifiedclang/include/clang/AST/ASTNodeTraverser.h
The file was modifiedclang/lib/AST/ExprCXX.cpp
The file was modifiedclang/lib/AST/DeclTemplate.cpp
The file was modifiedclang/include/clang/AST/DeclTemplate.h
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/lib/AST/TextNodeDumper.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/include/clang/AST/ASTConcept.h
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
The file was modifiedclang/include/clang/AST/ExprCXX.h
The file was modifiedclang/lib/Serialization/ASTWriterDecl.cpp
The file was modifiedclang/lib/Sema/SemaCodeComplete.cpp
The file was modifiedclang/lib/Serialization/ASTWriterStmt.cpp
The file was modifiedclang/lib/AST/ODRHash.cpp
The file was modifiedclang/lib/Serialization/ASTReaderDecl.cpp
The file was modifiedclang/include/clang/Sema/ParsedTemplate.h
The file was modifiedclang/include/clang/Parse/Parser.h
Commit 1a7398eca2040d232149f18a75b5d78a6521941c by listmail
[BranchAlign] Add master --x86-branches-within-32B-boundaries flag
This flag was originally part of D70157, but was removed as we carved
away pieces of the review. Since we have the nop support checked in, and
it appears mature(*), I think it's time to add the master flag. For now,
it will default to nop padding, but once the prefix padding support
lands, we'll update the defaults.
(*) I can now confirm that downstream testing of the changes which have
landed to date - nop padding and compiler support for suppressions - is
passing all of the functional testing we've thrown at it. There might
still be something lurking, but we've gotten enough coverage to be
confident of the basic approach.
Note that the new flag can be used either when assembling an .s file, or
when using the integrated assembler directly from the compiler. The
later will use all of the suppression mechanism and should always
generate correct code. We don't yet have assembly syntax for the
suppressions, so passing this directly to the assembler w/a raw .s file
may result in broken code. Use at your own risk.
Also note that this isn't the wiring for the clang option. I think the
most recent review for that is D72227, but I've lost track, so that
might be off.
Differential Revision: https://reviews.llvm.org/D72738
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
The file was modifiedllvm/test/MC/X86/align-branch-64-1a.s
Commit aca3e70d2bc0dd89b7d486c2a8eac70d8a89e790 by hstong
DWARFDebugLine.cpp: Restore LF line endings
rG7e02406f6cf180a8c89ce64665660e7cc9dbc23e switched the file to CRLF
line endings.
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
Commit c6e69880ae4d9ce4d27bf046292a0a20c3ab3540 by douglas.yung
Modify test to use -S instead of -c so that it works when an external
assembler is used that is not present.
The file was modifiedclang/test/Driver/cc1-spawnprocess.c
Commit 1b5404aff37953ce4c10191d04872ed7c2dc6548 by richard
PR44540: Prefer an inherited default constructor over an initializer
list constructor when initializing from {}.
We would previously pick between calling an initializer list constructor
and calling a default constructor unstably in this situation, depending
on whether the inherited default constructor had already been used
elsewhere in the program.
The file was modifiedclang/lib/Sema/SemaInit.cpp
The file was modifiedclang/lib/AST/DeclCXX.cpp
The file was modifiedclang/test/CXX/dcl.decl/dcl.init/dcl.init.list/p3.cpp
Commit 0dbcb3639451a7c20e2d5133b459552281e64455 by tstellar
CMake: Make most target symbols hidden by default
Summary: For builds with LLVM_BUILD_LLVM_DYLIB=ON and
BUILD_SHARED_LIBS=OFF this change makes all symbols in the target
specific libraries hidden by default.
A new macro called LLVM_EXTERNAL_VISIBILITY has been added to mark
symbols in these libraries public, which is mainly needed for the
definitions of the LLVMInitialize* functions.
This patch reduces the number of public symbols in libLLVM.so by about
25%.  This should improve load times for the dynamic library and also
make abi checker tools, like abidiff require less memory when analyzing
libLLVM.so
One side-effect of this change is that for builds with
LLVM_BUILD_LLVM_DYLIB=ON and LLVM_LINK_LLVM_DYLIB=ON some unittests that
access symbols that are no longer public will need to be statically
linked.
Before and after public symbol counts (using gcc 8.2.1, ld.bfd 2.31.1):
nm before/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l 36221 nm
after/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l 26278
Reviewers: chandlerc, beanz, mgorny, rnk, hans
Reviewed By: rnk, hans
Subscribers: merge_guards_bot, luismarques, smeenai, ldionne, lenary,
s.egerton, pzheng, sameer.abuasal, MaskRay, wuzish, echristo, Jim,
hiraditya, michaelplatings, chapuni, jholewinski, arsenm, dschuff,
jyknight, dylanmckay, sdardis, nemanjai, jvesely, javed.absar, sbc100,
jgravelle-google, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso,
simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones,
mgrang, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX,
jocewei, kristina, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54439
The file was modifiedllvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiTargetMachine.cpp
The file was modifiedllvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
The file was modifiedllvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
The file was modifiedllvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/ARM/CMakeLists.txt
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
The file was modifiedllvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
The file was modifiedllvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
The file was modifiedllvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcTargetMachine.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/lib/Target/CMakeLists.txt
The file was modifiedllvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
The file was modifiedllvm/lib/Target/Mips/MipsTargetMachine.cpp
The file was modifiedllvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/PowerPC/CMakeLists.txt
The file was modifiedllvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/BPF/BPFTargetMachine.cpp
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
The file was modifiedllvm/unittests/Target/AArch64/CMakeLists.txt
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
The file was modifiedllvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
The file was modifiedllvm/utils/unittest/CMakeLists.txt
The file was modifiedllvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt
The file was modifiedllvm/lib/Target/ARC/ARCAsmPrinter.cpp
The file was modifiedllvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
The file was modifiedllvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcAsmPrinter.cpp
The file was modifiedllvm/lib/Target/X86/X86AsmPrinter.cpp
The file was modifiedllvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
The file was modifiedllvm/include/llvm/Support/Compiler.h
The file was modifiedllvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
The file was modifiedllvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
The file was modifiedllvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
The file was modifiedllvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreAsmPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
The file was modifiedllvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
The file was modifiedllvm/unittests/CMakeLists.txt
The file was modifiedllvm/lib/Target/MSP430/MSP430TargetMachine.cpp
The file was modifiedllvm/lib/Target/AVR/AVRTargetMachine.cpp
The file was modifiedllvm/lib/Target/BPF/BPFAsmPrinter.cpp
The file was modifiedllvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
The file was modifiedllvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
The file was modifiedllvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
The file was modifiedllvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
The file was modifiedllvm/unittests/Target/WebAssembly/CMakeLists.txt
The file was modifiedllvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
The file was modifiedllvm/lib/Target/Mips/MipsAsmPrinter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
The file was modifiedllvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
The file was modifiedllvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
The file was modifiedllvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
The file was modifiedllvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
The file was modifiedllvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
The file was modifiedllvm/unittests/Target/ARM/CMakeLists.txt
The file was modifiedllvm/lib/Target/AVR/AVRAsmPrinter.cpp
The file was modifiedllvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
The file was modifiedllvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/AArch64/CMakeLists.txt
The file was modifiedllvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
The file was modifiedllvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
The file was modifiedllvm/lib/Target/ARC/TargetInfo/ARCTargetInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetMachine.cpp
The file was modifiedllvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreTargetMachine.cpp
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modifiedllvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modifiedllvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt
The file was modifiedllvm/lib/Target/ARC/ARCTargetMachine.cpp
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
The file was modifiedllvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
Commit d18fbfc09720009c0dc6a1ddf315402ee0a7751d by phabouzit
Relax the rules around objc_alloc and objc_alloc_init optimizations.
Today the optimization is limited to:
- `[ClassName alloc]`
- `[self alloc]` when within a class method
However it means that when code is written this way:
```
   @interface MyObject
   - (id)copyWithZone:(NSZone *)zone
   {
       return [[self.class alloc] _initWith...];
   }
    @end
```
... then the optimization doesn't kick in and `+[NSObject alloc]` ends
up in IMP caches where it could have been avoided. It turns out that
`+alloc` -> `+[NSObject alloc]` is the most cached SEL/IMP pair in the
entire platform which is rather silly).
There's two theoretical risks allowing this optimization:
1. if the receiver is nil (which it can't be today), but it turns out
  that `objc_alloc()`/`objc_alloc_init()` cope with a nil receiver,
2. if the `Clas` type for the receiver is a lie. However, for such a
  code to work today (and not fail witn an unrecognized selector
  anyway) you'd have to have implemented the `-alloc` **instance
  method**.
   Fortunately, `objc_alloc()` doesn't assume that the receiver is a
  Class, it basically starts with a test that is similar to
       `if (receiver->isa->bits & hasDefaultAWZ) { /* fastpath */ }`.
   This bit is only set on metaclasses by the runtime, so if an instance
  is passed to this function by accident, its isa will fail this test,
  and `objc_alloc()` will gracefully fallback to `objc_msgSend()`.
   The one thing `objc_alloc()` doesn't support is tagged pointer
  instances. None of the tagged pointer classes implement an instance
  method called `'alloc'` (actually there's a single class in the
  entire Apple codebase that has such a method).
Differential Revision: https://reviews.llvm.org/D71682 Radar-Id:
rdar://problem/58058316 Reviewed-By: Akira Hatanaka Signed-off-by:
Pierre Habouzit <phabouzit@apple.com>
The file was modifiedclang/lib/CodeGen/CGObjC.cpp
The file was modifiedclang/test/CodeGenObjC/objc-alloc-init.m
Commit 36eedfcb3cea6d4fb0c5998e63596502eb7d32f0 by chmeeedalf
[PowerPC] Fix powerpcspe subtarget enablement in llvm backend
Summary: As currently written, -target powerpcspe will enable SPE
regardless of disabling the feature later on in the command line.
Instead, change this to just set a default CPU to 'e500' instead of a
generic CPU.
As part of this, add FeatureSPE to the e500 definition.
Reviewed By: MaskRay Differential Revision:
https://reviews.llvm.org/D72673
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp

Summary

  1. [zorg] Pass "-DLLVM_POLLY_LINK_INTO_TOOLS=ON" in getPollyBuildFactory (details)
Commit 6ad01600c4e27d7238564346976df22204a5014b by efriedma
[zorg] Pass "-DLLVM_POLLY_LINK_INTO_TOOLS=ON" in getPollyBuildFactory
The default here was changed recently, and the
aosp-O3-polly-before-vectorizer-unprofitable builder assumes polly is
linked into clang.
Differential Revision: https://reviews.llvm.org/D72646
The file was modifiedzorg/buildbot/builders/PollyBuilder.py