AbortedChanges

Summary

  1. [X86] Autogenerate complete checks. NFC (details)
  2. [DAGCombiner] Teach SimplifySetCC SETUGE X, SINTMIN -> SETLT X, 0 and SETULE X, SINTMAX  -> SETGT X, -1. (details)
  3. [MLIR][NFC] Fix misleading diagnostic error + clang-tidy fix (details)
  4. [X86][GlobalISel] Remove unneeded code for handling zext i8->16, i8->i64, i16->i64, i32->i64. (details)
  5. [llvm-readobj] - Remove 3 excessive test cases. (details)
  6. [llvm-readelf/obj] - Refine the implementation of printMipsReginfo(). (details)
  7. [ARM] Some formatting and predicate VRHADD patterns. NFC (details)
  8. [ARM] Allow vecreduce_add in tail predicated loops (details)
  9. [ARM] Add VADDV and VMLAV patterns for v16i16 (details)
  10. [Diagnostics] Turn string concat warning to avoid false positives (details)
  11. [Polly] Reuse LLVM's build rules for gtest/gmock (details)
  12. [SCEVExpander] Avoid re-using existing casts if it means updating users. (details)
  13. [VectorCombine] try to create vector loads from scalar loads (details)
  14. [Diagnostics] Handle string concat pattern and avoid false positives (details)
  15. [Tests] Precommit tests for D85593 (details)
Commit 95e61ed85c1abb7dab20ab665d6204ea66f5bf1f by craig.topper
[X86] Autogenerate complete checks. NFC
The file was modifiedllvm/test/CodeGen/X86/break-false-dep.ll
Commit fdfdee98ac81dc7554bb2d7f5e99614e0086b4f0 by craig.topper
[DAGCombiner] Teach SimplifySetCC SETUGE X, SINTMIN -> SETLT X, 0 and SETULE X, SINTMAX  -> SETGT X, -1.

These aren't the canonical forms we'd get from InstCombine, but
we do have X86 tests for them. Recognizing them is pretty cheap.

While there make use of APInt:isSignedMinValue/isSignedMaxValue
instead of creating a new APInt to compare with. Also use
SelectionDAG::getAllOnesConstant helper to hide the all ones
APInt creation.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-compare-simplify.ll
Commit 231c554abc8aad4240705149f785f9e76398d937 by uday
[MLIR][NFC] Fix misleading diagnostic error + clang-tidy fix

Fix misleading diagnostic error in affine.yield verifier + a clang-tidy fix.

Differential Revision: https://reviews.llvm.org/D85587
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp
Commit bc8be3054067ac822fc6d9f4f8e64c841f530f16 by craig.topper
[X86][GlobalISel] Remove unneeded code for handling zext i8->16, i8->i64, i16->i64, i32->i64.

These all seem to be handled by tablegen pattern imports.
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
The file was modifiedllvm/lib/Target/X86/X86InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/ext.ll
Commit cfd2ee29e0e23fe4174740a97cc001c8b7a21475 by grimar
[llvm-readobj] - Remove 3 excessive test cases.

This patch does the following:

1) Removes mips-options.test and the corresponding Inputs/mips-options.elf-mips64el binary:
This is a test that checks that --dynamic-table is able to print the DT_MIPS_OPTIONS tag.
We are testing it in dynamic-tags-machine-specific.test already.
(https://github.com/llvm/llvm-project/blob/master/llvm/test/tools/llvm-readobj/ELF/dynamic-tags-machine-specific.test#L235)

2) Removes mips-rld-map-rel.test and the corresponding Inputs/mips-rld-map-rel.elf-mipsel binary.
This is a test that checks that --dynamic-table is able to print the DT_MIPS_RLD_MAP_REL tag.
We are testing it in dynamic-tags-machine-specific.test already.
(https://github.com/llvm/llvm-project/blob/master/llvm/test/tools/llvm-readobj/ELF/dynamic-tags-machine-specific.test#L257)

3) Removes ppc64-glink.test test and the corresponding Inputs/ppc64.exe binary.
This is a test that checks that --dynamic-table is able to print the DT_PPC64_GLINK tag.
We are testing it in dynamic-tags-machine-specific.test already.
(https://github.com/llvm/llvm-project/blob/master/llvm/test/tools/llvm-readobj/ELF/dynamic-tags-machine-specific.test#L337)

Differential revision: https://reviews.llvm.org/D85515
The file was removedllvm/test/tools/llvm-readobj/ELF/mips-options.test
The file was removedllvm/test/tools/llvm-readobj/ELF/Inputs/mips-options.elf-mips64el
The file was removedllvm/test/tools/llvm-readobj/ELF/Inputs/mips-rld-map-rel.elf-mipsel
The file was removedllvm/test/tools/llvm-readobj/ELF/Inputs/ppc64.exe
The file was removedllvm/test/tools/llvm-readobj/ELF/mips-rld-map-rel.test
The file was removedllvm/test/tools/llvm-readobj/ELF/ppc64-glink.test
Commit c990455db91e52bd6b8ac9b68b06ef19f7239722 by grimar
[llvm-readelf/obj] - Refine the implementation of printMipsReginfo().

It adds the proper warnings reporting and updates the mips-reginfo.test to
remove using of the precompiled binary.

Differential revision: https://reviews.llvm.org/D85511
The file was removedllvm/test/tools/llvm-readobj/ELF/Inputs/reginfo.obj.elf-mipsel
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-reginfo.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 296faa91ed55c05b40d286be020fc65d2fc262b5 by david.green
[ARM] Some formatting and predicate VRHADD patterns. NFC

This formats some of the MVE patterns, and adds a missing
Predicates = [HasMVEInt] to some VRHADD patterns I noticed
as going through. Although I don't believe NEON would ever
use the patterns (as it would use ADDL and VSHRN instead)
they should ideally be predicated on having MVE instructions.
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit 8590e5abad51257fe9120313b37192f37aef8eec by david.green
[ARM] Allow vecreduce_add in tail predicated loops

This allows vecreduce_add in loops so that we can tailpredicate them.

Differential Revision: https://reviews.llvm.org/D85454
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp
Commit 186a7f81e813a59b68fadfe7ea90c348bb760c56 by david.green
[ARM] Add VADDV and VMLAV patterns for v16i16

This adds patterns for v16i16's vecreduce, using all the existing code
to go via an i32 VADDV/VMLAV and truncating the result.

Differential Revision: https://reviews.llvm.org/D85452
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 04a23f1fe08a6ad0baf1305d7308231d2cb4843b by Dávid Bolvanský
[Diagnostics] Turn string concat warning to avoid false positives
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/Sema/string-concat.c
Commit c8b629a3a5854506dd25e84f9b4174b53f8f667b by mgorny
[Polly] Reuse LLVM's build rules for gtest/gmock

Reuse LLVM's CMakeLists.txt for gtest/gmock instead of reinventing
them in Polly.  This fixes a lot of linking errors due to not linking
LLVMSupport in for me.

Differential Revision: https://reviews.llvm.org/D85280
The file was modifiedpolly/CMakeLists.txt
Commit c70f0b9d4a063df396bb63378963cedbaa357bb8 by flo
[SCEVExpander] Avoid re-using existing casts if it means updating users.

Currently the SCEVExpander tries to re-use existing casts, even if they
are not exactly at the insertion point it was asked to create the cast.
To do so in some case, it creates a new cast at the insertion point and
updates all users to use the new cast.

This behavior is problematic, because it changes the IR outside of the
instructions created during the expansion. Therefore we cannot
completely undo all changes made during expansion.

This re-use should be only an extra optimization, so only using the new
cast in the expanded instructions should not be a correctness issue.
There are many cases equivalent instructions are created during
expansion.

This patch also adjusts findInsertPointAfter to skip instructions
inserted during expansion. This enables re-using existing casts without
the renaming any uses, by picking a better insertion point.

Reviewed By: efriedma, lebedev.ri

Differential Revision: https://reviews.llvm.org/D84399
The file was modifiedllvm/test/Transforms/LoopDistribute/bounds-expansion-bug.ll
The file was modifiedllvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
The file was modifiedllvm/test/Transforms/LoopIdiom/reuse-cast.ll
The file was modifiedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/pr27056.ll
Commit 43bdac290663f4424f9fb3920c47c7288a2aabb4 by spatel
[VectorCombine] try to create vector loads from scalar loads

This patch was adjusted to match the most basic pattern that starts with an insertelement
(so there's no extract created here). Hopefully, that removes any concern about
interfering with other passes. Ie, the transform should almost always be profitable.

We could make an argument that this could be part of canonicalization, but we
conservatively try not to create vector ops from scalar ops in passes like instcombine.

If the transform is not profitable, the backend should be able to re-scalarize the load.

Differential Revision: https://reviews.llvm.org/D81766
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit 975467e4aa7ce1b8fcf4af0e25cdf053cfa8669e by Dávid Bolvanský
[Diagnostics] Handle string concat pattern and avoid false positives
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/Sema/string-concat.c
Commit dee938e5ccdb5b3afe4e5b6e91b41db9c7fe61bd by Dávid Bolvanský
[Tests] Precommit tests for D85593
The file was addedllvm/test/Transforms/InstCombine/not-add.ll