Changes

[zorg][PowerPC] Add tags for builders

Add the tag for all PowerPC builders so that we can identify them
easily.
eg: Check all with http://lab.llvm.org:8011/#/waterfall?tags=%20ppc

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D90263

[libcxx] [docs] [NFC] Fix typo.

[flang][openacc] Enforce no modifier on enter data and exit data clauses

Enter data can have the copyin clause and exit data can have the copyout clause.
Both clauses support modifier with other directive but for these two directives no modifier
are supported. This semantic check enforce this rule.

Reviewed By: kiranktp

Differential Revision: https://reviews.llvm.org/D90280

[mlir][openacc] Add if and device_type to update op

Update op is modelling the update directive (2.14.4) from the OpenACC specs.
An if condition and a device_type list can be attached to the directive. This patch add
these two information to the current op.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D90310

[VE] Support register aliases in llvm-mc

Support register aliases in MC layer to compile existing assembly
files with clang and integrated assembler.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90383

[VE] Add missing symbolic branch patterns

Add missing symbolic branch patterns to a regression test.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90388

Revert "clang-format: Add a consumer to diagnostics engine"

This reverts commit df00267f1fdb0b098dc42f1caa8a59b29c8e0e5f.
clang-format should not depend on Frontend, see comment on
https://reviews.llvm.org/D90121.

[VE] Add missing BCR format

Add missing "BCR %sy, 0, target" format instruction and a regression
test for this format.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90387

[SVE] Remove TypeSize comparison operators

All known instances in the code where we relied upon the TypeSize
comparison operators have now been changed to either use scalar
interger comparisons or one of the TypeSize::isKnownXY functions.
It is now safe to remove the comparison operators.

Differential Revision: https://reviews.llvm.org/D90160

[MLIR] Support walks over regions and blocks

Add specializations for `walk` to allow traversal of regions and blocks.

Differential Revision: https://reviews.llvm.org/D90379

[AMDGPU] Fix double space in disassembly of some DPP instructions

Differential Revision: https://reviews.llvm.org/D90373

[AMDGPU] Fix double space in disassembly of s_set_gpr_idx_mode

Differential Revision: https://reviews.llvm.org/D90374

[AMDGPU] Remove gds operand from ds_gws_* MachineInstrs

The operand value was always 1 (except in some bad MIR tests) so it was
redundant.

Differential Revision: https://reviews.llvm.org/D90378

[libc++] Remove additional uses of std::rand() missed by 63aeadb4849d

[VE] Change to use integrated assembly by defualt

We've implemented integrated assembler.  Now, we change to use
integrated assembler by default.  Update a regression test also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90396

[ARM] Add IT block generation test

D88496 introduces some new behaviour to IT block generation,
behaviour which is not covered by the current unit tests.
This adds one to cover it

Differential Revision: https://reviews.llvm.org/D90398

[ARM] Fix IT block generation after Thumb2SizeReduce with -Oz

Fixes a regression caused by D82439, in which IT blocks were no longer being generated when -Oz is present.

Differential Revision: https://reviews.llvm.org/D88496

[mlir][Linalg] Make Linalg fusion a test pass

Linalg "tile-and-fuse" is currently exposed as a Linalg pass "-linalg-fusion" but only the mechanics of the transformation are currently relevant.
Instead turn it into a "-test-linalg-greedy-fusion" pass which performs canonicalizations to enable more fusions to compose.
This allows dropping the OperationFolder which is not meant to be used with the pattern rewrite infrastructure.

Differential Revision: https://reviews.llvm.org/D90394

[InstCombine] visitShl - ensure inner shifts have inrange amounts

Noticed when fixing OSS Fuzz #26716

[NFC] Add more tests for DISubprogram verifier

Minimum amount of tests to cover (most) of the DISubprogram verifier
checks.

Reviewed By: vsk

Differential Revision: https://reviews.llvm.org/D90340

Change-Id: Icd25dac64f87f6dcf67ff3443eb4f95af18d05a8

[sanitizer] Print errno for report file open failure

To help debug failures, specifically the llvm-avr-linux bot failure from
5c20d7db9f2791367b9311130eb44afecb16829c:

http://lab.llvm.org:8011/#/builders/112/builds/407/steps/5/logs/FAIL__MemProfiler-x86_64-linux-dynamic__log_path_t

Also re-enable the failing test which I temporarily disabled, to
see if this change will help identify why that particular log file can't
be opened for write on that bot (when another log file in the same
directory could earlier in the test).

Differential Revision: https://reviews.llvm.org/D90120

[AMDGPU] Use pseudo instructions for readlane/writelane

This reverts r227987 "R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2".

All the codegen changes are caused by the post-RA scheduler no longer
treating readlane/writelane as scheduling barriers due to having
unmodelled side effects. (The pseudos are hasSideEffects = 0, but the
real instructions are hasSideEffects = ? which TableGen conservatively
treats as 1.)

Differential Revision: https://reviews.llvm.org/D90401

[MC] Error for .globl/.local which change the symbol binding and warn for .weak

GNU as let .weak override .globl since binutils-gdb
5ca547dc2399a0a5d9f20626d4bf5547c3ccfddd (1996) while MC lets the last
directive win (PR38921).

This caused an issue to Linux's powerpc port which has been fixed by
http://git.kernel.org/linus/968339fad422a58312f67718691b717dac45c399

Binding overriding is error-prone. This patch disallows a changed binding.
(https://sourceware.org/pipermail/binutils/2020-March/000299.html )

Our behavior regarding `.globl x; .weak x` matches GNU as. Such usage is
still suspicious but we issue a warning for now. We may upgrade it to an
error in the future.

Reviewed By: jhenderson, nickdesaulniers

Differential Revision: https://reviews.llvm.org/D90108

[x86] add test for umul intrinsic costs; NFC

[AMDGPU] Add __builtin_amdgcn_grid_size

[AMDGPU] Add __builtin_amdgcn_grid_size

Similar to D76772, loads the data from the dispatch pointer. Marked invariant.

Patch also updates the openmp devicertl to use this builtin.

Reviewed By: yaxunl

Differential Revision: https://reviews.llvm.org/D90251

[X86] Add PR46393 test case

[mlir][gpu] Allow gpu.launch_func to be async.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D89324

[ThinLTO] Fix empty .llvmcmd sections

When passing -lto-embed-bitcode=post-merge-pre-opt, we were getting
empty .llvmcmd sections. It turns out that is because the
CodeGenOptions::CmdArgs field was only populated when clang saw
-fembed-bitcode={all|marker}.

This patch always populates the CodeGenOptions::CmdArgs. The overhead
of carrying through in memory in all cases is likely negligible in
the grand schema of things, and it keeps the using code simple.

Differential Revision: https://reviews.llvm.org/D90366

[nfc] [lldb] Remove excessive parentheses in SymbolFileDWARF::GetUID

[MemProf] Augment test to debug avr bot failure

After 81f7b96ed0a2295e0b82ca185019370ac8e1895e, I can see that the
reason this test is failing on llvm-avr-linux is that it doesn't think
the directory exists (error comes during file open for write command).
Not sure why since this is the main test Output directory and we created
a different file there earlier in the test from the same file open
invocation. Print directory contents in an attempt to debug.

Revert "[mlir][gpu] Allow gpu.launch_func to be async."

This reverts commit ec7780ebdab480139596c3cb08ee77d7035457b3.

One of the bot is crashing in a test related to this change.

[AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds

By setting up the AsmStrings correctly we can remove some special cases
from AMDGPUInstPrinter::printOffset.

Differential Revision: https://reviews.llvm.org/D90307

[Support] Make Support/SwapByteOrder.h compile on Fuchsia

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D90279

[sanitizer][fuchsia] Avoid deprecated syscall.

The zx_clock_get syscall on Fuchsia is deprecated - ref
https://fuchsia.dev/fuchsia-src/reference/syscalls/clock_get
This changes to the recommended replacement; calling zx_clock_read on
the userspace UTC clock.

Reviewed By: mcgrathr, phosek

Differential Revision: https://reviews.llvm.org/D90169

[libc++] Minor cleanup in the test suite

[WebAssembly] Implement SIMD signselect instructions

As proposed in https://github.com/WebAssembly/simd/pull/124, using the opcodes
adopted by V8 in
https://chromium-review.googlesource.com/c/v8/v8/+/2486235/2/src/wasm/wasm-opcodes.h.
Uses new builtin functions and a new target intrinsic exclusively to ensure that
the new instructions are only emitted when a user explicitly opts in to using
them since they are still in the prototyping and evaluation phase.

Differential Revision: https://reviews.llvm.org/D90357

Add support of the next Ubuntu (Ubuntu 21.04 - Hirsute Hippo)

[MemProf] Temporarily disable test failing on a couple bots

I finally see why this test is failing (on now 2 bots). Somehow the path
name is getting messed up, and the "linux" converted to "1". I suspect
there is something in the environment causing the macro expansion in the
test to get messed up:

http://lab.llvm.org:8011/#/builders/112/builds/555/steps/5/logs/FAIL__MemProfiler-x86_64-linux__log_path_test_cpp
http://lab.llvm.org:8011/#/builders/37/builds/275/steps/31/logs/stdio

On the avr bot:
-DPROFILE_NAME_VAR="/home/buildbot/llvm-avr-linux/llvm-avr-linux/stage1/projects/compiler-rt/test/memprof/X86_64LinuxConfig/TestCases/Output/log_path_test.cpp.tmp.log2"

after macros expansions becomes:
/home/buildbot/llvm-avr-1/llvm-avr-1/stage1/projects/compiler-rt/test/memprof/X86_64LinuxConfig/TestCases/Output/log_path_test.cpp.tmp.log2

Similar (s/linux/1/) on the other bot.

Disable it while I investigate

[RISCV] Remove include of RISCVRegisterInfo.h from RISCVBaseInfo.h

RISCVRegisterInfo.h is part of the CodeGen layer. The Utils library
is intended to be shared with the MC layer so shouldn't use files
from the CodeGen layer.

The register enum names are already available from
RISCVMCTargetDesc.h. It appears what was coming from this include
was a transitive include of the Register class which I've replaced
with MCRegister. Register has a constructor from MCRegister so it
should be convertible.

[clangd] Add support for multiple DecisionForest model experiments.

With every incremental change, one needs to check-in new model upstream.
This also significantly increases the size of the git repo with every
new model.
Testing and comparing the old and previous model is also not possible as
we run only a single model at any point.

One solution is to have a "staging" decision forest which can be
injected into clangd without pushing it to upstream. Compare the
performance of the staging model with the live model. After a couple of
enhancements have been done to staging model, we can then replace the
live model upstream with the staging model. This reduces upstream churn
and also allows us to compare models with current baseline model.

This is done by having a callback in CodeCompleteOptions which is called
only when we want to use a decision forest ranking model. This allows us
to inject different completion model internally.

Differential Revision: https://reviews.llvm.org/D90014

[zorg][PowerPC] Add tags for builders

Add the tag for all PowerPC builders so that we can identify them
easily.
eg: Check all with http://lab.llvm.org:8011/#/waterfall?tags=%20ppc

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D90263