FailedChanges

Summary

  1. [ELF][test] Improve tests (details)
  2. [SimplifyCFG][NFC] Make merge-cond-stores-cost.ll X86-specific, and (details)
  3. Fix MSVC "32-bit shift implicitly converted to 64 bits" warnings. NFCI. (details)
  4. [DebugInfo] Pre-commit of test case for DW_OP_breg/DW_OP_fbreg folds (details)
  5. [DwarfExpression] Disallow some rewrites to avoid undefined behavior (details)
  6. [X86] Add test for PR43230; NFC (details)
  7. [LVI] Look through extractvalue of insertvalue (details)
  8. [X86] Fix pshuflw formation from repeated shuffle mask (PR43230) (details)
  9. [Intrinsic] Add the llvm.umul.fix.sat intrinsic (details)
  10. [CodeGen] Handle SMULFIXSAT with scale zero in (details)
  11. [SimplifyCFG][NFC] Autogenerate two tests (details)
  12. [SimplifyCFG][NFC] Autogenerate PhiEliminate3.ll (details)
  13. [ELF][MC] Set types of aliases of IFunc to STT_GNU_IFUNC (details)
  14. [mips] Make another set of test cases more tolerant to exact symbol (details)
Commit 0e79890d9b5aef4466d572458c0fbb6031b991f6 by maskray
[ELF][test] Improve tests
Add file-level comments Delete insignificant addresses to make them more
tolerant to layout changes Simplify test output
Delete weak-undef-val.s - covered by relocation-undefined-weak.s Delete
weak-undef-export.s - covered by additional test added to weak-undef.s
Delete version-undef-sym.s - covered by undefined-versioned-symbol.s =>
version-symbol-undef.s Delete symbol-ordering-file2.s - covered by
symbol-ordering-file.s Delete gotpcrelx.s - covered by
gotpc-relax-und-dso.s => x86-64-gotpc-relax-und-dso.s
llvm-svn: 371299
The file was addedlld/test/ELF/x86-64-gotpc-relax-und-dso.s
The file was removedlld/test/ELF/gotpcrelx.s
The file was modifiedlld/test/ELF/x86-64-retpoline-znow.s
The file was modifiedlld/test/ELF/noplt-pie.s
The file was modifiedlld/test/ELF/x86-64-tls-ld-preemptable.s
The file was modifiedlld/test/ELF/pre_init_fini_array_missing.s
The file was modifiedlld/test/ELF/writable-sec-plt-reloc.s
The file was addedlld/test/ELF/version-symbol-undef.s
The file was removedlld/test/ELF/got-plt-header.s
The file was modifiedlld/test/ELF/weak-undef.s
The file was modifiedlld/test/ELF/progname.s
The file was removedlld/test/ELF/weak-undef-val.s
The file was removedlld/test/ELF/weak-undef-export.s
The file was modifiedlld/test/ELF/x86-64-relax-got-abs.s
The file was modifiedlld/test/ELF/x86-64-tls-opt-noplt.s
The file was removedlld/test/ELF/version-undef-sym.s
The file was removedlld/test/ELF/Inputs/progname-ver.s
The file was addedlld/test/ELF/end-dso-defined.s
The file was removedlld/test/ELF/gotpc-relax-nopic.s
The file was modifiedlld/test/ELF/version-script-extern.s
The file was removedlld/test/ELF/Inputs/version-undef-sym.so
The file was modifiedlld/test/ELF/local-symbols-order.s
The file was modifiedlld/test/ELF/x86-64-tls-dynamic.s
The file was modifiedlld/test/ELF/emit-relocs-icf2.s
The file was modifiedlld/test/ELF/emit-relocs-mergeable2.s
The file was modifiedlld/test/ELF/ehdr_start.s
The file was modifiedlld/test/ELF/icf-symbol-type.s
The file was removedlld/test/ELF/gotpc-relax.s
The file was modifiedlld/test/ELF/x86-64-retpoline.s
The file was modifiedlld/test/ELF/relative-dynamic-reloc.s
The file was addedlld/test/ELF/x86-64-got-plt-header.s
The file was removedlld/test/ELF/gotpc-relax-und-dso.s
The file was removedlld/test/ELF/resolution-end.s
The file was modifiedlld/test/ELF/x86-64-relax-offset.s
The file was addedlld/test/ELF/x86-64-gotpc-relax.s
The file was modifiedlld/test/ELF/icf7.s
The file was removedlld/test/ELF/undefined-versioned-symbol.s
The file was addedlld/test/ELF/x86-64-gotpc-relax-nopic.s
The file was removedlld/test/ELF/symbol-ordering-file2.s
Commit 395f254bf0e53ee2e268a717d7f063fbff6a6cca by lebedev.ri
[SimplifyCFG][NFC] Make merge-cond-stores-cost.ll X86-specific, and
rewrite it
We clearly perform store-merging, even though div is really costly.
llvm-svn: 371300
The file was modifiedllvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll
The file was addedllvm/test/Transforms/SimplifyCFG/X86/merge-cond-stores-cost.ll
Commit d7d8bb937ad0e27a95ae722826697fc449c77fde by llvm-dev
Fix MSVC "32-bit shift implicitly converted to 64 bits" warnings. NFCI.
llvm-svn: 371302
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit e85acf946d3b5bd62c97ac9d49e95e4b8a4cbe83 by bjorn.a.pettersson
[DebugInfo] Pre-commit of test case for DW_OP_breg/DW_OP_fbreg folds
This currently triggers undefined behavior if executed with an ubsan
build. It is just a precommit of the test case to show that we got a
problem.
Fix is proposed in https://reviews.llvm.org/D67263 and plan is to commit
the fix directly after this patch.
llvm-svn: 371303
The file was addedllvm/test/DebugInfo/X86/dw_op_constu.mir
Commit 2b698a13a11e0b007c9e1d71bc69fcf4a194eab1 by bjorn.a.pettersson
[DwarfExpression] Disallow some rewrites to avoid undefined behavior
Summary: The value operand in DW_OP_plus_uconst/DW_OP_constu value can
be large (it uses uint64_t as representation internally in LLVM). This
means that in the uint64_t to int conversions, previously done by
DwarfExpression::addMachineRegExpression, could lose information. Also,
the negation done in "-Offset" was undefined behavior in case Offset was
exactly INT_MIN.
To avoid the above problems, we now avoid transformation like
[Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset] and
[Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset] when
Offset > INT_MAX.
And we avoid to transform
[Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset] when
Offset > INT_MAX+1.
The patch also adjusts DwarfCompileUnit::constructVariableDIEImpl to
make sure that "DW_OP_constu, Offset, DW_OP_minus" is used instead of
"DW_OP_plus_uconst, Offset" when creating DIExpressions with negative
frame index offsets.
Notice that this might just be the tip of the iceberg. There are lots of
fishy handling related to these constants. I think both
DIExpression::appendOffset and DIExpression::extractIfOffset may trigger
undefined behavior for certain values.
Reviewers: sdesmalen, rnk, JDevlieghere
Reviewed By: JDevlieghere
Subscribers: jholewinski, aprantl, hiraditya, ychen, uabelho,
llvm-commits
Tags: #debug-info, #llvm
Differential Revision: https://reviews.llvm.org/D67263
llvm-svn: 371304
The file was modifiedllvm/test/DebugInfo/X86/dw_op_constu.mir
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was modifiedllvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
Commit 5d02f259c098a2c965f30803de3a53476309ab1f by nikita.ppv
[X86] Add test for PR43230; NFC
llvm-svn: 371305
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
Commit fdc6977ff3c0cb6c729c38c86f96e1281cb3171c by nikita.ppv
[LVI] Look through extractvalue of insertvalue
This addresses the issue mentioned on D19867. When we simplify
with.overflow instructions in CVP, we leave behind extractvalue of
insertvalue sequences that LVI no longer understands. This means that we
can not simplify any instructions based on the with.overflow anymore
(until some over pass like InstCombine cleans them up).
This patch extends LVI extractvalue handling by calling
SimplifyExtractValueInst (which doesn't do anything more than constant
folding + looking through insertvalue) and using the block value of the
simplification.
A possible alternative would be to do something similar to
SimplifyIndVars, where we instead directly try to replace extractvalue
users of the with.overflow. This would need some additional structural
changes to CVP, as it's currently not legal to remove anything but the
current instruction -- we'd have to introduce a worklist with
instructions scheduled for deletion or similar.
Differential Revision: https://reviews.llvm.org/D67035
llvm-svn: 371306
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/overflows.ll
The file was modifiedllvm/lib/Analysis/LazyValueInfo.cpp
Commit 314893cc4ba05e65da4be26afb21b2fb50eab7b3 by nikita.ppv
[X86] Fix pshuflw formation from repeated shuffle mask (PR43230)
Fix for https://bugs.llvm.org/show_bug.cgi?id=43230.
When creating PSHUFLW from a repeated shuffle mask, we have to apply the
checks to the repeated mask, not the original one. For the test case
from PR43230 the inspected part of the original mask is all undef.
Differential Revision: https://reviews.llvm.org/D67314
llvm-svn: 371307
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 5e331e4ce85ad37dca45739846c2a801f06ab573 by bjorn.a.pettersson
[Intrinsic] Add the llvm.umul.fix.sat intrinsic
Summary: Add an intrinsic that takes 2 unsigned integers with the scale
of them provided as the third argument and performs fixed point
multiplication on them. The result is saturated and clamped between the
largest and smallest representable values of the first 2 operands.
This is a part of implementing fixed point arithmetic in clang where
some of the more complex operations will be implemented as intrinsics.
Patch by: leonardchan, bjope
Reviewers: RKSimon, craig.topper, bevinh, leonardchan, lebedev.ri,
spatel
Reviewed By: leonardchan
Subscribers: ychen, wuzish, nemanjai, MaskRay, jsji, jdoerfert, Ka-Ka,
hiraditya, rjmccall, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57836
llvm-svn: 371308
The file was modifiedllvm/test/CodeGen/X86/mulfix_combine.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/Analysis/VectorUtils.cpp
The file was modifiedllvm/test/Verifier/intrinsic-immarg.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-mulfix-legalize.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/test/Transforms/Scalarizer/intrinsics.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was addedllvm/test/CodeGen/X86/umul_fix_sat.ll
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was addedllvm/test/CodeGen/PowerPC/umulfixsat.ll
Commit d065c811649f0d0df5429741a9a3dd643e88a9fe by bjorn.a.pettersson
[CodeGen] Handle SMULFIXSAT with scale zero in
TargetLowering::expandFixedPointMul
Summary: Normally TargetLowering::expandFixedPointMul would handle
SMULFIXSAT with scale zero by using an SMULO to compute the product and
determine if saturation is needed (if overflow happened). But if SMULO
isn't custom/legal it falls through and uses the same technique, using
MULHS/SMUL_LOHI, as used for non-zero scales.
Problem was that when checking for overflow (handling saturation) when
not using MULO we did not expect to find a zero scale. So we ended up in
an assertion when doing
APInt::getLowBitsSet(VTSize, Scale - 1)
This patch fixes the problem by adding a new special case for how
saturation is computed when scale is zero.
Reviewers: RKSimon, bevinh, leonardchan, spatel
Reviewed By: RKSimon
Subscribers: wuzish, nemanjai, hiraditya, MaskRay, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67071
llvm-svn: 371309
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/smulfixsat.ll
Commit 88bab08a886b46409a97297af3f25e8992b5ca83 by lebedev.ri
[SimplifyCFG][NFC] Autogenerate two tests
llvm-svn: 371310
The file was modifiedllvm/test/Transforms/SimplifyCFG/speculate-math.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/SpeculativeExec.ll
Commit 4e76f880723a4a1a25a94f556aea72f63da8f17a by lebedev.ri
[SimplifyCFG][NFC] Autogenerate PhiEliminate3.ll
llvm-svn: 371311
The file was modifiedllvm/test/Transforms/SimplifyCFG/PhiEliminate3.ll
Commit 72e99e63a2f9b51853cf74eddae37d7eaf106ca5 by maskray
[ELF][MC] Set types of aliases of IFunc to STT_GNU_IFUNC
```
.type  foo,@gnu_indirect_function
.set   foo,foo_resolver
.set foo2,foo
.set foo3,foo2
```
The types of foo2 and foo3 should be STT_GNU_IFUNC, but we currently
resolve them to the type of foo_resolver. This patch fixes it.
Differential Revision: https://reviews.llvm.org/D67206 Patch by Senran
Zhang
llvm-svn: 371312
The file was addedllvm/test/MC/ELF/ifunc-alias.s
The file was modifiedllvm/lib/MC/ELFObjectWriter.cpp
Commit fcef13344db8883d2ba5adfca1499b605a136c5b by simon
[mips] Make another set of test cases more tolerant to exact symbol
addresses. NFC
llvm-svn: 371313
The file was modifiedlld/test/ELF/mips-hilo-hi-only.s
The file was modifiedlld/test/ELF/mips-gprel32-relocs.s
The file was modifiedlld/test/ELF/mips-higher-highest.s
The file was modifiedlld/test/ELF/mips-hilo.s
The file was addedlld/test/ELF/mips-jalr.s
The file was modifiedlld/test/ELF/mips-gp-local.s
The file was modifiedlld/test/ELF/mips-got16-relocatable.s
The file was modifiedlld/test/ELF/mips-got16.s
The file was modifiedlld/test/ELF/mips-got-relocs.s
The file was modifiedlld/test/ELF/mips-gprel32-relocs-gp0.s
The file was modifiedlld/test/ELF/mips-got-weak.s
The file was modifiedlld/test/ELF/mips-gp-disp.s
The file was removedlld/test/ELF/mips-jalr.test
The file was modifiedlld/test/ELF/mips-mgot.s
The file was modifiedlld/test/ELF/mips-hilo-gp-disp.s
The file was modifiedlld/test/ELF/mips-gprel-sec.s