FailedChanges

Summary

  1. The setUp/tearDown methods I added mssed up the test function; reorder. (details)
  2. [Target] Move InferiorCall to Process (details)
  3. DAG/GlobalISel: Correct type profile of bitcount ops (details)
  4. AMDGPU/GlobalISel: Select G_CTPOP (details)
  5. Revert r371785. (details)
  6. AMDGPU/GlobalISel: Legalize G_FMAD (details)
  7. [ScopBuilder] Skip getting leader when merging statements to close (details)
  8. Temporarily revert r371640 "LiveIntervals: Split live intervals on (details)
  9. AMDGPU/GlobalISel: Legalize G_FFLOOR (details)
  10. [ELF] Delete a redundant assignment to SectionBase::assigned. NFC (details)
  11. For PR17164: split -fno-lax-vector-conversion into three different (details)
  12. [RISCV] Support stack offset exceed 32-bit for RV64 (details)
  13. AMDGPU/GlobalISel: Select 16-bit VALU bit ops (details)
  14. AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else (details)
  15. Revert "[RISCV] Support stack offset exceed 32-bit for RV64" (details)
  16. [RISCV] Support stack offset exceed 32-bit for RV64 (details)
  17. AMDGPU/GlobalISel: Legalize s32->s16 G_SITOFP/G_UITOFP (details)
  18. AMDGPU/GlobalISel: Fix assert on multi-return side effect intrinsics (details)
Commit 0a39ef4704a5934d6cecbd3afdc771732bed107d by Jason Molenda
The setUp/tearDown methods I added mssed up the test function; reorder.
Thanks to Ted Woodward for catching this one.
llvm-svn: 371795
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestWriteMemory.py
Commit 5b2b38e053b4638c08da4104e8bb5bd643fde737 by apl
[Target] Move InferiorCall to Process
Summary: InferiorCall is only ever used in Process, and it is not
specific to POSIX. By moving it to Process, we can remove all
dependencies on plugins from Process. Moving InferiorCall to Process
seems to achieve this quite well. Additionally, the name InferiorCall is
a little vague now, so we rename it something a bit more specific.
Reviewers: JDevlieghere, clayborg, compnerd, labath
Subscribers: lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D67472
llvm-svn: 371796
The file was modifiedlldb/source/Target/Process.cpp
The file was modifiedlldb/source/Plugins/Process/Utility/InferiorCallPOSIX.cpp
The file was modifiedlldb/include/lldb/Target/Process.h
The file was modifiedlldb/source/Plugins/Process/Utility/InferiorCallPOSIX.h
Commit b366329a34a1f2dc277f030df239236d43792fba by Matthew.Arsenault
DAG/GlobalISel: Correct type profile of bitcount ops
The result integer does not need to be the same width as the input.
AMDGPU, NVPTX, and Hexagon all have patterns working around the types
matching. GlobalISel defines these as being different type indexes.
llvm-svn: 371797
The file was modifiedllvm/lib/Target/NVPTX/NVPTXInstrInfo.td
The file was modifiedllvm/lib/Target/Sparc/SparcInstr64Bit.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.td
The file was modifiedllvm/lib/Target/Sparc/SparcInstrInfo.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonPatterns.td
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
Commit 4a73c6eadae0c92771106f85fc77c32f60a1b30e by Matthew.Arsenault
AMDGPU/GlobalISel: Select G_CTPOP
llvm-svn: 371798
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 38f6b3fd8dd7dc3a3b4eae63738d5d3a741b2227 by manojgupta
Revert r371785.
r371785 is causing fails on clang-hexagon-elf buildbots.
llvm-svn: 371799
The file was modifiedclang/lib/Frontend/InitHeaderSearch.cpp
The file was removedclang/test/Frontend/warning-poison-system-directories.c
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/include/c++/.keep
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/lib/.keep
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/lib/gcc/.keep
The file was modifiedclang/include/clang/Basic/DiagnosticCommonKinds.td
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/include/.keep
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/lib/.keep
Commit 4d3391803462433b05a3344e6c37435f725637c4 by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize G_FMAD
Unlike SelectionDAG, treat this as a normally legalizable operation. In
SelectionDAG this is supposed to only ever formed if it's legal, but
I've found that to be restricting. For AMDGPU this is contextually legal
depending on whether denormal flushing is allowed in the use function.
Technically we currently treat the denormal mode as a subtarget feature,
so custom lowering could be avoided. However I consider this to be a
defect, and this should be contextually dependent on the controllable
rounding mode of the parent function.
llvm-svn: 371800
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 87baae85cdee84b43986f1d8d0fac469c7e9521b by llvm
[ScopBuilder] Skip getting leader when merging statements to close
holes.
Function joinOrderedInstructions merges instructions when a leader is
encountered twice. It also notices that leaders in SeenLeaders may lose
their leadership in previous merging, and tries to handle the case using
following code:
    Instruction *PrevLeader =
UnionFind.getLeaderValue(SeenLeaders.back());
However, this is wrong because it always gets leader for the last
element of SeenLeaders, and I believe it's wrong even we get leader for
Prev here.  As a result, Statements in cases like the one in patch
aren't merged as expected.  After investigation, I believe it's
unnecessary to get leader instruction at all.  This is based on fact:
Although leaders in SeenLeaders could lose leadership, they only lose to
others in SeenLeaders, in other words, one existing leader will be
chosen as new leader of merged equivalent statements.  We can take
advantage of this and simply check if current leader equals to Prev and
break merging if it does.
The patch also adds a new test.
Patch by bin.narwal <bin.narwal@gmail.com>
Differential Revision: https://reviews.llvm.org/D67007
llvm-svn: 371801
The file was addedpolly/test/ScopInfo/granularity_scalar-indep_ordered-2.ll
The file was modifiedpolly/lib/Analysis/ScopBuilder.cpp
Commit a31c521f5ebd3b26ba132361b14d0e6393b851bb by timshen91
Temporarily revert r371640 "LiveIntervals: Split live intervals on
multiple dead defs".
It reveals a miscompile on Hexagon. See PR43302 for details.
llvm-svn: 371802
The file was modifiedllvm/lib/CodeGen/LiveIntervals.cpp
The file was removedllvm/test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mir
Commit f457dd2bd437b7d65024194d1f3b4e6c6b0e07ec by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize G_FFLOOR
llvm-svn: 371803
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
Commit 51ead00bf81cd92a868bdd1551a06ec5efdb563b by maskray
[ELF] Delete a redundant assignment to SectionBase::assigned. NFC
LinkerScript::discard marks a section dead. It is unnecessary to set the
`assigned` bit.
llvm-svn: 371804
The file was modifiedlld/ELF/LinkerScript.cpp
Commit 49c4e58b75ecec8dce75dd13c61aaeb30e14b531 by richard-llvm
For PR17164: split -fno-lax-vector-conversion into three different
levels:
-- none: no lax vector conversions [new GCC default]
-- integer: only conversions between integer vectors [old GCC default]
-- all: all conversions between same-size vectors [Clang default]
For now, Clang still defaults to "all" mode, but per my proposal on
cfe-dev (2019-04-10) the default will be changed to "integer" as soon as
that doesn't break lots of testcases. (Eventually I'd like to change the
default to "none" to match GCC and general sanity.)
Following GCC's behavior, the driver flag -flax-vector-conversions is
translated to -flax-vector-conversions=integer.
llvm-svn: 371805
The file was modifiedclang/test/CodeGen/builtins-systemz-zvector2-error.c
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/test/CodeGen/builtins-systemz-vector2.c
The file was modifiedclang/test/Headers/x86intrin.c
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/test/Headers/arm-neon-header.c
The file was modifiedclang/test/Sema/typedef-retain.c
The file was modifiedclang/test/CodeGen/builtins-systemz-zvector.c
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedclang/test/SemaCXX/vector-no-lax.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/CodeGen/builtins-systemz-zvector-error.c
The file was modifiedclang/test/CodeGen/builtins-systemz-zvector2.c
The file was modifiedclang/test/Sema/ext_vector_casts.c
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/CodeGen/builtins-systemz-zvector3.c
The file was modifiedclang/test/CodeGen/builtins-systemz-zvector3-error.c
The file was modifiedclang/test/Headers/altivec-header.c
The file was modifiedclang/test/SemaCXX/vector.cpp
The file was modifiedclang/test/Sema/zvector2.c
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was modifiedclang/test/Headers/x86-intrinsics-headers-clean.cpp
The file was modifiedclang/test/Sema/zvector.c
The file was modifiedclang/test/Headers/x86intrin-2.c
The file was modifiedclang/test/CodeGen/builtins-systemz-vector.c
The file was modifiedclang/test/Headers/x86-intrinsics-headers.c
The file was modifiedclang/test/SemaCXX/altivec.cpp
The file was modifiedclang/test/CodeGen/builtins-systemz-vector3.c
The file was modifiedclang/test/CodeGenCXX/builtins-systemz-zvector.cpp
Commit eaa230fe3c868beeaea70b7621acc9bfaf126d04 by shiva0217
[RISCV] Support stack offset exceed 32-bit for RV64
Differential Revision: https://reviews.llvm.org/D61884
llvm-svn: 371806
The file was modifiedllvm/test/CodeGen/RISCV/stack-realignment.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
The file was addedllvm/test/CodeGen/RISCV/rv64-large-stack.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Commit 638f802381178350c0897659515607b92bd20dcb by Matthew.Arsenault
AMDGPU/GlobalISel: Select 16-bit VALU bit ops
llvm-svn: 371807
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
Commit 67d9349dad3f4a950e6a389748feb028abb00537 by Matthew.Arsenault
AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else
llvm-svn: 371808
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
Commit ea530ba3ed757de7ffc45114e9b5e9fa72475fe3 by shiva0217
Revert "[RISCV] Support stack offset exceed 32-bit for RV64"
This reverts commit 1c340c62058d4115d21e5fa1ce3a0d094d28c792.
llvm-svn: 371809
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was removedllvm/test/CodeGen/RISCV/rv64-large-stack.ll
The file was modifiedllvm/test/CodeGen/RISCV/stack-realignment.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
Commit a49a16ddd0eb06cd0d84e2f073364397d94a1e84 by shiva0217
[RISCV] Support stack offset exceed 32-bit for RV64
Differential Revision: https://reviews.llvm.org/D61884
llvm-svn: 371810
The file was modifiedllvm/test/CodeGen/RISCV/stack-realignment.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was addedllvm/test/CodeGen/RISCV/rv64-large-stack.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Commit a4be3eff5c957fb280dbcc693c5cd966e9e3c158 by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize s32->s16 G_SITOFP/G_UITOFP
llvm-svn: 371811
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
Commit 3b7ffc6ae75a98827880c85c5f78099a044c8e09 by Matthew.Arsenault
AMDGPU/GlobalISel: Fix assert on multi-return side effect intrinsics
llvm.amdgcn.else hits this.
llvm-svn: 371812
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp