FailedChanges

Summary

  1. Revert "[IRSim] Adding IRSimilarityCandidate that contains a region of IRInstructionData." (details)
  2. [test][NewPM] Fix update-scev.ll under NPM (details)
  3. [CostModel][X86] add CostModel for SK_Select(v8f64, v8i64, v16f32, v16i32, v32i16, v64i8) (details)
  4. [test][NewPM] Clean up ScalarEvolution tests to work under NPM (details)
  5. [lld-macho] In the context of relocs, s/target/referent/ for sections & symbols (details)
  6. [ThinLTO] Avoid temporaries when loading global decl attachment metadata (details)
  7. [lld-maco] fix build breakage (details)
  8. [Sanitizers] Fix test case that doesn't clean up after itself (details)
  9. [sanitizers] Remove the message queue with IPC_RMID after D82897 (details)
  10. [RISCV][ASAN] updated platform macros to simplify detection of RISCV64 platform (details)
  11. [Analyzer][WebKit] Use tri-state types for relevant predicates (details)
  12. [RISCV][ASAN] implementation of internal syscalls wrappers for riscv64 (details)
  13. [RISCV][ASAN] implementation of clone interceptor for riscv64 (details)
  14. [RISCV][ASAN] implementation for vfork interceptor for riscv64 (details)
  15. [RISCV][ASAN] implementation of ThreadSelf  for riscv64 (details)
  16. Add a dump() method on the pass manager for debugging purpose (NFC) (details)
  17. [MC] [Win64EH] Try to generate packed unwind info where possible (details)
  18. [InstCombine] Add parentheses in assert to silence GCC warning. NFC. (details)
  19. [CVP] Remove a redundant trailing semicolon, fixing GCC warnings. NFC. (details)
  20. [PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins (details)
  21. Revert "[RISCV][ASAN] implementation of ThreadSelf  for riscv64" (details)
  22. [NFC] Reformat preprocessor directives (details)
  23. [RISCV][ASAN] implementation of ThreadSelf  for riscv64 (details)
  24. [mlir][Linalg] Add pattern to fold linalg.tensor_reshape that add unit extent dims. (details)
  25. [AMDGPU] Fix merging m0 inits (details)
  26. [SVE] Fix InstCombinerImpl::PromoteCastOfAllocation for scalable vectors (details)
Commit 88bc59c3001b3b20f55994f9fa9dbaf45991df1d by andrew.litteken
Revert "[IRSim] Adding IRSimilarityCandidate that contains a region of IRInstructionData."

This reverts commit 4944bb190fed8861d4d043eaf45e3c1e12aa2dc5.
The file was modifiedllvm/include/llvm/Analysis/IRSimilarityIdentifier.h
The file was modifiedllvm/lib/Analysis/IRSimilarityIdentifier.cpp
The file was modifiedllvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
Commit d6746ecb73c3892bd9a353c3b1b3facbd285c450 by aeubanks
[test][NewPM] Fix update-scev.ll under NPM
The file was modifiedllvm/test/Transforms/LICM/update-scev.ll
Commit ec24e505536fe50636fcbc759b821aca6295aa45 by bing1.yu
[CostModel][X86] add CostModel for SK_Select(v8f64, v8i64, v16f32, v16i32, v32i16, v64i8)

add CostModel for SK_Select(v8f64, v8i64, v16f32, v16i32, v32i16, v64i8)

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D87884
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-select.ll
Commit 2d0de5f9a4c58e2fcdd8f00dabca505ba47abbd0 by aeubanks
[test][NewPM] Clean up ScalarEvolution tests to work under NPM
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/trivial-phis.ll
Commit 1a3ef0417c7ca9498895186c96da452f6e2f15a0 by gkm
[lld-macho] In the context of relocs, s/target/referent/ for sections & symbols

The word "target" is overloaded, so lighten its load by using another word to denote the symbol or section to which a reloc points. While more stilted than "target", "referent" is rather less pompous than "designatum" or "denotatum". :P

Along the way, make a few neighboring variable names more descriptive.

Reviewed By: #lld-macho, int3

Differential Revision: https://reviews.llvm.org/D87584
The file was modifiedlld/MachO/InputSection.cpp
The file was modifiedlld/MachO/InputFiles.cpp
The file was modifiedlld/MachO/InputSection.h
Commit ab1b4810b55279bcf6fdd87be74a403440be3991 by tejohnson
[ThinLTO] Avoid temporaries when loading global decl attachment metadata

When performing ThinLTO importing, the metadata loader attempts to lazy
load, by building an index. However, module level global decl attachment
metadata was being parsed early while building the index, since the
associated (module level) global values aren't materialized on demand.
This results in the creation of forward reference temporary metadatas,
which are expensive.

Normally, these module level global values don't have much attached
metadata. However, in the case of -fwhole-program-vtables (e.g. for
whole program devirtualization), the vtables may have many attached type
metadatas. This was resulting in very slow performance when performing
ThinLTO importing with the default lazy loading.

This patch restructures the handling of these global decl attachment
records, delaying their parsing until after the lazy loading index has
been built. Then the parser can use the interface that loads from the
index, which resolves forward references immediately instead of creating
expensive temporaries.

For one ThinLTO backend that imports from modules containing huge
numbers of vtables and associated types, I measured the following
compile times for the metadata materialization during function
importing, rounded to nearest second:

No -fwhole-program-vtables:
  Lazy loading on (head):  1s
  Lazy loading off (head): 3s
  Lazy loading on (patch): 1s

With -fwhole-program-vtables:
  Lazy loading on (head):  440s
  Lazy loading off (head): 4s
  Lazy loading on (patch): 2s

Differential Revision: https://reviews.llvm.org/D87970
The file was modifiedllvm/lib/Bitcode/Reader/MetadataLoader.cpp
The file was modifiedllvm/test/ThinLTO/X86/devirt2.ll
Commit ab903560a466194d4350600ad946934eb72f1a14 by gkm
[lld-maco] fix build breakage
The file was modifiedlld/MachO/Writer.cpp
Commit f1746be66673bc2b59f7aaad1c6a7938ed98194b by nemanja.i.ibm
[Sanitizers] Fix test case that doesn't clean up after itself

Commit https://reviews.llvm.org/rG144e57fc9535 added this test
case that creates message queues but does not remove them. The
message queues subsequently build up on the machine until the
system wide limit is reached. This has caused failures for a
number of bots running on a couple of big PPC machines.

This patch just adds the missing cleanup.
The file was modifiedcompiler-rt/test/sanitizer_common/TestCases/Linux/sysmsg.c
Commit cabe31f415054b45b4fa6c17e4ddf09cc39bf4e8 by i
[sanitizers] Remove the message queue with IPC_RMID after D82897
The file was modifiedcompiler-rt/test/sanitizer_common/TestCases/Linux/sysmsg.c
Commit dfd295431a50aa8bccc0b89da9acf3c48b3d4b29 by Vitaly Buka
[RISCV][ASAN] updated platform macros to simplify detection of RISCV64 platform

[2/11] patch series to port ASAN for riscv64

Depends On D87997

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87998
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
Commit 47e6851423fd32f0685a643236ad946e23ab14ff by Jan Korous
[Analyzer][WebKit] Use tri-state types for relevant predicates

Some of the predicates can't always be decided - for example when a type
definition isn't available. At the same time it's necessary to let
client code decide what to do about such cases - specifically we can't
just use true or false values as there are callees with
conflicting strategies how to handle this.

This is a speculative fix for PR47276.

Differential Revision: https://reviews.llvm.org/D88133
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/NoUncountedMembersChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/RefCntblBaseVirtualDtorChecker.cpp
Commit 6c22d00d7896bd7aaad567aa98016c26e78d8dcf by Vitaly Buka
[RISCV][ASAN] implementation of internal syscalls wrappers for riscv64

implements glibc-like wrappers over Linux syscalls.

[3/11] patch series to port ASAN for riscv64

Depends On D87998

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87572
The file was modifiedcompiler-rt/lib/sanitizer_common/CMakeLists.txt
The file was addedcompiler-rt/lib/sanitizer_common/sanitizer_syscall_linux_riscv64.inc
Commit 96034cb3d1d6d0e4ebe6848ef93707943aeca5dc by Vitaly Buka
[RISCV][ASAN] implementation of clone interceptor for riscv64

[4/11] patch series to port ASAN for riscv64

Depends On D87572

Reviewed By: eugenis, vitalybuka

Differential Revision: https://reviews.llvm.org/D87573
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.h
Commit aa1b1d35cbf60f63c7830e6711bf849902975943 by Vitaly Buka
[RISCV][ASAN] implementation for vfork interceptor for riscv64

[5/11] patch series to port ASAN for riscv64

Depends On D87573

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87574
The file was modifiedcompiler-rt/lib/asan/asan_interceptors.h
The file was addedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_vfork_riscv64.inc.S
The file was modifiedcompiler-rt/lib/asan/asan_interceptors_vfork.S
The file was modifiedcompiler-rt/lib/hwasan/hwasan_interceptors_vfork.S
Commit 00f6ebef6e347e0d24a8f940fe43656719e88cb8 by Vitaly Buka
[RISCV][ASAN] implementation of ThreadSelf  for riscv64

[6/11] patch series to port ASAN for riscv64

Depends On D87574

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87575
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit fe3c1195cfd027fdd28b6d373b3cd9519d5253ec by joker.eph
Add a dump() method on the pass manager for debugging purpose (NFC)

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D88008
The file was modifiedmlir/include/mlir/Pass/Pass.h
The file was modifiedmlir/include/mlir/Pass/PassManager.h
The file was modifiedmlir/lib/Pass/Pass.cpp
Commit f69e090d7dca6bf2786145a9e97b0a7ddb3b514a by martin
[MC] [Win64EH] Try to generate packed unwind info where possible

In practice, this only gives modest savings (for a 6.5 MB DLL with
230 KB xdata, the xdata sections shrinks by around 2.5 KB); to
gain more, the frame lowering would need to be tweaked to more often
generate frame layouts that match the canonical layouts that can
be written in packed form.

Differential Revision: https://reviews.llvm.org/D87371
The file was modifiedllvm/lib/MC/MCWin64EH.cpp
The file was addedllvm/test/MC/AArch64/seh-packed-unwind.s
The file was modifiedllvm/include/llvm/MC/MCWinEH.h
Commit 2c4c659666b400b0502e8504a708e050d0a03d6c by martin
[InstCombine] Add parentheses in assert to silence GCC warning. NFC.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
Commit b90132399aa994ac6405d0d6437735043bff9314 by martin
[CVP] Remove a redundant trailing semicolon, fixing GCC warnings. NFC.
The file was modifiedllvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
Commit d7eb917a7cb793f49e16841fc24826b988dd5c8f by albionapc
[PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

This patch implements 128-bit Binary Vector Mod and Sign Extend builtins for PowerPC10.

Differential: https://reviews.llvm.org/D87394#inline-815858
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedclang/test/CodeGen/builtins-ppc-p9vector.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-modulo.ll
The file was addedllvm/test/CodeGen/PowerPC/p10-vector-sign-extend.ll
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was addedllvm/test/CodeGen/PowerPC/p9-vector-sign-extend.ll
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
Commit 1fbb5969424493344f1159d53bda5a640e3b27ae by Vitaly Buka
Revert "[RISCV][ASAN] implementation of ThreadSelf  for riscv64"

Merged two unrelated commits

This reverts commit 00f6ebef6e347e0d24a8f940fe43656719e88cb8.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit d721a2bc335ad01ff6b3838bc4759cfc35b6c8fa by Vitaly Buka
[NFC] Reformat preprocessor directives
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit 809a42e3d53518b824aad28882f9f9397f25b5b3 by Vitaly Buka
[RISCV][ASAN] implementation of ThreadSelf  for riscv64

[6/11] patch series to port ASAN for riscv64

Depends On D87574

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87575
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit b62f9f4407a5ed6e5722e177e906efcebebce9eb by ravishankarm
[mlir][Linalg] Add pattern to fold linalg.tensor_reshape that add unit extent dims.

A sequence of two reshapes such that one of them is just adding unit
extent dims can be folded to a single reshape.

Differential Revision: https://reviews.llvm.org/D88057
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Commit 8d7fd73c3a8ce069cfe48dfcf949b4a59c05c673 by Piotr Sobczak
[AMDGPU] Fix merging m0 inits

Fix incorrect merges of m0 inits in loops.

It was assumed that if a clobbering instruction appears in
the same block as an init and the clobbering instruction
does not dominate the init then it does not interfere with
init.

This does not work in the presence of loops, where in this
scenario, the clobbering instruction does interfere with
the init in another iteration.

To fix this, do not check for block equality and defer the
decision to the predecessor check.

Differential Revision: https://reviews.llvm.org/D87882
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-m0.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
Commit 59c4d5aad060927fa95b917c11aad4e310849a4b by david.sherwood
[SVE] Fix InstCombinerImpl::PromoteCastOfAllocation for scalable vectors

In this patch I've fixed some warnings that arose from the implicit
cast of TypeSize -> uint64_t. I tried writing a variety of different
cases to show how this optimisation might work for scalable vectors
and found:

1. The optimisation does not work for cases where the cast type
is scalable and the allocated type is not. This because we need to
know how many times the cast type fits into the allocated type.
2. If we pass all the various checks for the case when the allocated
type is scalable and the cast type is not, then when creating the
new alloca we have to take vscale into account. This leads to
sub-optimal IR that is worse than the original IR.
3. For the remaining case when both the alloca and cast types are
scalable it is hard to find examples where the optimisation would
kick in, except for simple bitcasts, because we typically fail the
ABI alignment checks.

For now I've changed the code to bail out if only one of the alloca
and cast types is scalable. This means we continue to support the
existing cases where both types are fixed, and also the specific case
when both types are scalable with the same size and alignment, for
example a simple bitcast of an alloca to another type.

I've added tests that show we don't attempt to promote the alloca,
except for simple bitcasts:

  Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll

Differential revision: https://reviews.llvm.org/D87378
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
The file was addedllvm/test/Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll