FailedChanges

Summary

  1. [zorg] [PowerPC] Limit number of threads to 64 on clang-ppc64le-rhel buildbot (details)
Commit c2cc01b14ef84bee845318bde3ae623091934b96 by saghir
[zorg] [PowerPC] Limit number of threads to 64 on clang-ppc64le-rhel buildbot

This patch reduces the number of threads from 256 to 64 on the
clang-ppc64le-rhel buildbot.

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D88586
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. InstCombine] collectBitParts - cleanup variable names. NFCI. (details)
  2. [InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI. (details)
  3. [RDA] isSafeToDefRegAt: Look at global uses (details)
  4. [InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI. (details)
  5. [InstCombine] Add PR47191 bswap tests (details)
  6. [lldb] Fix FreeBSD Arm Process Plugin build (details)
  7. [VPlan] Change recipes to inherit from VPUser instead of a member var. (details)
  8. [lldb] [Process/NetBSD] Fix operating on ftag register (details)
  9. [InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI. (details)
  10. [InstCombine] Remove %tmp variable names from bswap tests (details)
  11. [InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI. (details)
  12. [clangd] Fix invalid UTF8 when extracting doc comments. (details)
  13. [PowerPC] Remove support for VRSAVE save/restore/update. (details)
  14. [GlobalISel] Fix incorrect setting of ValNo when splitting (details)
  15. Move AffineMapAttr into BaseOps.td (details)
  16. [sanitizers] Fix internal__exit on Solaris (details)
  17. [NFC][FE] Replace TypeSize with StorageUnitSize (details)
  18. Reapply "RegAllocFast: Rewrite and improve" (details)
  19. RegAllocFast: Add extra DBG_VALUE for live out spills (details)
  20. LiveDebugValues: Fix typos and indentation (details)
  21. GlobalISel: Assert if MoreElements uses a non-vector type (details)
  22. [InstCombine] Remove %tmp variable names from bswap-fold tests (details)
  23. [FE] Use preferred alignment instead of ABI alignment for complete object when applicable (details)
  24. [mlir][Linalg] Generalize the logic to compute reassociation maps (details)
  25. [InstCombine] Add bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector tests (details)
  26. [InstCombine] Fix bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector support (details)
  27. [PowerPC] Avoid unused variable warning in Release builds (details)
  28. [PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9 (details)
  29. [InstCombine] Add tests for 'partial' bswap patterns (details)
  30. [NFC][regalloc] Make VirtRegAuxInfo part of allocator state (details)
  31. [DA][SDA] SyncDependenceAnalysis re-write (details)
  32. [VE] Support TargetBlockAddress (details)
  33. [ObjCARCAA][NewPM] Add already ported objc-arc-aa to PassRegistry.def (details)
  34. [mlir][openacc] Remove -allow-unregistred-dialect from ops and invalid tests (details)
  35. [llvm-exegesis] Add option to check the hardware support for a given feature before benchmarking. (details)
  36. scudo: Make it thread-safe to set some runtime configuration flags. (details)
  37. [test][SampleProfile][NewPM] Fix some tests under NPM (details)
  38. [asan][test] Several Posix/unpoison-alternate-stack.cpp fixes (details)
  39. [AArch64] Avoid pairing loads when the base reg is modified (details)
  40. [CodeGen] add test for NAN creation; NFC (details)
  41. [Sema] Support Comma operator for fp16 vectors. (details)
Commit 05290eead3f95e02700890321ccf6719770f91fe by llvm-dev
InstCombine] collectBitParts - cleanup variable names. NFCI.

Fix a number of WShadow warnings (I was used as the instruction and index......) and fix cases to match style.

Also, replaced the Bit APInt mask check in AND instructions with a direct APInt[] bit check.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 413b4998bd722ab671e29e6dff5d458d1869f39b by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI.

Post-commit feedback on D88316
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 3f88c10a6b25668bb99f5eee7867dcbf37df973c by sam.parker
[RDA] isSafeToDefRegAt: Look at global uses

We weren't looking at global uses of a value, so we could happily
overwrite the register incorrectly.

Differential Revision: https://reviews.llvm.org/D88554
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
Commit 621c6c89627972d52796e64a9476a7d05f22f2cd by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI.

Early out if both pattern matches have failed (or we don't want them). Fix case of bit index iterator (and avoid Wshadow issue).
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 08c5720405d5204ec2329b7f6c561062c7dddee2 by llvm-dev
[InstCombine] Add PR47191 bswap tests
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit f794160c6cb7da4b5ef354a91fe498341f651d36 by emaste
[lldb] Fix FreeBSD Arm Process Plugin build

Add a missing include and some definitions in 769533216666.

Patch by: Brooks Davis

Reviewed by: labath

Differential Revision: https://reviews.llvm.org/D88453
The file was modifiedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.h
The file was modifiedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.cpp
Commit d8563654701c79fb9ab28ecf94567d9934baed05 by flo
[VPlan] Change recipes to inherit from VPUser instead of a member var.

Now that VPUser is not inheriting from VPValue, we can take the next
step and turn the recipes that already manage their operands via VPUser
into VPUsers directly. This is another small step towards traversing
def-use chains in VPlan.

This is NFC with respect to the generated code, but makes the interface
more powerful.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
Commit 762e8f9bbdaf43300dbc75637a8bce1ce643cc06 by mgorny
[lldb] [Process/NetBSD] Fix operating on ftag register
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
Commit d5545a8993489ee426b757482a64c9373cf7cf38 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 7fcad5583a12026ce19afe487681753ac633064a by llvm-dev
[InstCombine] Remove %tmp variable names from bswap tests

Appease update_test_checks script that was complaining about potential %TMP clashes
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit c722b3259690d3aad20f31d0ffe6c12b1416bccc by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI.

There doesn't seem to be any good reason for having a separate path for when we bswap/bitreverse at a smaller size than the destination size - so merge these to make the instruction generation a lot clearer.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 216af81c39d1cc4e90af7b991d517c4c7acc912e by sam.mccall
[clangd] Fix invalid UTF8 when extracting doc comments.

Differential Revision: https://reviews.llvm.org/D88567
The file was modifiedclang-tools-extra/clangd/unittests/CodeCompletionStringsTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
The file was modifiedclang-tools-extra/clangd/CodeCompletionStrings.cpp
Commit dfb717da1f794c235b81a985a57dc238c82318e6 by sd.fertile
[PowerPC] Remove support for VRSAVE save/restore/update.

After removal of Darwin as a PowerPC subtarget, the VRSAVE
save/restore/spill/update code is no longer needed by any supported
subtarget, so remove it while keeping support for vrsave and related instruction
aliases for inline asm. I've pre-commited tests to document the existing vrsave
handling in relation to @llvm.eh.unwind.init and inline asm usage, as
well as a test which shows a beahviour change on AIX related to
returning vector type as we were wrongly emiting VRSAVE_UPDATE on AIX.
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/README_ALTIVEC.txt
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/aix-vector-return.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Commit 43d239d0fadb1f8ea297580ca39dfbee96c913c1 by mikael.holmen
[GlobalISel] Fix incorrect setting of ValNo when splitting

Before, for each original argument i, ValNo was set to i + PartIdx, but
ValNo is intended to reflect the index of the value before splitting.
Hence, ValNo should always be set to i and not consider the PartIdx.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D86511
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit f33f8a2b30325d89c4b7daef1b7d11d6da38fd56 by benny.kra
Move AffineMapAttr into BaseOps.td

AffineMapAttr is already part of base, it's just impossible to refer to
it from ODS without pulling in the definition from Affine dialect.

Differential Revision: https://reviews.llvm.org/D88555
The file was modifiedmlir/include/mlir/Dialect/GPU/ParallelLoopMapperAttr.td
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was removedmlir/include/mlir/Dialect/Affine/IR/AffineOpsBase.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
Commit dc261d23d07cccfa7b10a3d1a43903138aee94dc by ro
[sanitizers] Fix internal__exit on Solaris
`TestCases/log-path_test.cpp` currently `FAIL`s on Solaris:

  $ env ASAN_OPTIONS=log_path=`for((i=0;i<10000;i++)); do echo -n $i; done`  ./log-path_test.cpp.tmp
  ==5031==ERROR: Path is too long: 01234567...
  Segmentation Fault (core dumped)

The `SEGV` happens here:

  Thread 2 received signal SIGSEGV, Segmentation fault.
  [Switching to Thread 1 (LWP 1)]
  0x00000000 in ?? ()
  (gdb) where
  #0  0x00000000 in ?? ()
  #1  0x080a1e63 in __interceptor__exit (status=1)
      at /vol/gcc/src/llvm/llvm/local/projects/compiler-rt/lib/asan/../sanitizer_common/sanitizer_common_interceptors.inc:3808
  #2  0x08135ea8 in __sanitizer::internal__exit (exitcode=1)
      at /vol/gcc/src/llvm/llvm/local/projects/compiler-rt/lib/sanitizer_common/sanitizer_solaris.cc:139

when `__interceptor__exit` tries to call `__interception::real__exit` which
is `NULL` at this point because the interceptors haven't been initialized yet.

Ultimately, the problem lies elsewhere, however: `internal__exit` in
`sanitizer_solaris.cpp` calls `_exit` itself since there doesn't exit a
non-intercepted version in `libc`.  Using the `syscall` interface instead
isn't usually an option on Solaris because that interface isn't stable.
However, in the case of `SYS_exit` it can be used nonetheless: `SYS_exit`
has remained unchanged since at least Solaris 2.5.1 in 1996, and this is
what this patch does.

Tested on `amd64-pc-solaris2.11`.

Differential Revision: https://reviews.llvm.org/D88404
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_solaris.cpp
Commit 944691f0b7fa8d99790a4544545e55f014c37295 by Xiangling.Liao
[NFC][FE] Replace TypeSize with StorageUnitSize

On some targets like AIX, last bitfield size is not always equal to last
bitfield type size. Some bitfield like bool will have the same alignment
as [unsigned]. So we'd like to use a more general term `StorageUnit` to
replace type in this field.

Differential Revision: https://reviews.llvm.org/D88260
The file was modifiedclang/lib/AST/RecordLayoutBuilder.cpp
Commit 89baeaef2fa9a2441d087a218ac82e11a5d4e548 by Matthew.Arsenault
Reapply "RegAllocFast: Rewrite and improve"

This reverts commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4.
The file was modifiedllvm/test/CodeGen/ARM/stack-guard-reassign.ll
The file was modifiedllvm/test/DebugInfo/AArch64/frameindices.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-vararg.ll
The file was modifiedllvm/test/CodeGen/ARM/crash-greedy-v6.ll
The file was modifiedllvm/test/CodeGen/Mips/implicit-sret.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-nontemporal.ll
The file was modifiedllvm/test/CodeGen/ARM/Windows/alloca.ll
The file was modifiedllvm/test/CodeGen/PowerPC/stack-guard-reassign.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address_pic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
The file was modifiedlldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
The file was modifiedllvm/test/CodeGen/X86/pr39733.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll
The file was modifiedllvm/test/DebugInfo/X86/reference-argument.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr.mir
The file was modifiedllvm/test/CodeGen/X86/atomic32.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-null.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_constants.ll
The file was modifiedllvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/X86/atomic6432.ll
The file was modifiedllvm/test/CodeGen/X86/x86-32-intrcc.ll
The file was modifiedllvm/test/CodeGen/X86/pr34653.ll
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-overflow-toc.py
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-fastisel.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
The file was modifiedllvm/test/CodeGen/X86/win64_eh.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/swift-return.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
The file was modifiedllvm/test/DebugInfo/X86/pieces-1.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
The file was addedllvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
The file was modifiedllvm/test/CodeGen/X86/pr27591.ll
The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
The file was modifiedllvm/test/CodeGen/Mips/msa/ldr_str.ll
The file was modifiedllvm/test/CodeGen/AArch64/br-cond-not-merge.ll
The file was modifiedllvm/test/CodeGen/ARM/debug-info-blocks.ll
The file was modifiedllvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
The file was modifiedllvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
The file was addedllvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
The file was modifiedllvm/test/CodeGen/X86/pr32284.ll
The file was modifiedllvm/test/CodeGen/X86/x86-64-intrcc.ll
The file was modifiedllvm/test/CodeGen/ARM/swifterror.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
The file was modifiedllvm/test/CodeGen/X86/pr32451.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vector-spill.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
The file was modifiedllvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
The file was modifiedllvm/test/CodeGen/X86/pr32345.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-loads.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
The file was modifiedllvm/test/CodeGen/SPARC/fp16-promote.ll
The file was modifiedllvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
The file was modifiedllvm/test/CodeGen/ARM/cmpxchg-O0.ll
The file was modifiedllvm/test/CodeGen/X86/stack-protector-msvc.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll
The file was modifiedllvm/test/DebugInfo/Mips/prologue_end.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
The file was modifiedllvm/test/DebugInfo/X86/sret.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
The file was modifiedllvm/test/DebugInfo/X86/subreg.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-monotonic.ll
The file was modifiedllvm/test/CodeGen/Mips/micromips-eva.mir
The file was modifiedllvm/test/CodeGen/PowerPC/vsx-args.ll
The file was modifiedllvm/test/CodeGen/AArch64/cmpxchg-O0.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
The file was modifiedllvm/test/CodeGen/Thumb2/high-reg-spill.mir
The file was modifiedllvm/test/CodeGen/Mips/atomic.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic-min-max.ll
The file was modifiedllvm/test/CodeGen/Mips/copy-fp64.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll
The file was modifiedllvm/test/CodeGen/X86/pr34592.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
The file was modifiedllvm/test/CodeGen/X86/atomic64.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select-sse.ll
The file was modifiedllvm/test/CodeGen/X86/pr11415.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll
The file was modifiedllvm/test/CodeGen/PowerPC/popcount.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-x86-64.ll
The file was modifiedllvm/test/CodeGen/AArch64/swifterror.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll
The file was modifiedllvm/test/DebugInfo/X86/dbg-declare-arg.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_split_because_of_memsize_or_align.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic64.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
The file was addedllvm/test/CodeGen/PowerPC/spill-nor0.mir
The file was modifiedllvm/test/CodeGen/Mips/atomicCmpSwapPW.ll
The file was modifiedllvm/test/DebugInfo/X86/spill-indirect-nrvo.ll
The file was modifiedllvm/test/CodeGen/X86/crash-O0.ll
The file was modifiedllvm/test/CodeGen/X86/swifterror.ll
The file was modifiedllvm/test/CodeGen/ARM/pr47454.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
The file was modifiedllvm/test/CodeGen/X86/pr47000.ll
The file was modifiedllvm/test/CodeGen/X86/pr44749.ll
The file was addedllvm/test/CodeGen/X86/bug47278.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
The file was modifiedllvm/test/CodeGen/X86/swift-return.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
The file was modifiedllvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir
The file was modifiedllvm/test/CodeGen/ARM/legalize-bitcast.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
The file was modifiedllvm/test/CodeGen/PowerPC/spill-nor0.ll
The file was modifiedllvm/test/CodeGen/X86/pr32340.ll
The file was modifiedllvm/test/DebugInfo/ARM/prologue_end.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
The file was modifiedllvm/test/DebugInfo/X86/prologue-stack.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll
The file was modifiedllvm/test/CodeGen/PowerPC/elf-common.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-m0.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved.ll
The file was modifiedllvm/test/CodeGen/SystemZ/swift-return.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctpop.ll
The file was modifiedllvm/test/CodeGen/X86/pr30813.ll
The file was modifiedllvm/test/DebugInfo/Mips/delay-slot.ll
The file was modifiedllvm/test/CodeGen/X86/volatile.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
The file was modifiedllvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll
The file was modifiedllvm/test/CodeGen/X86/pr30430.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp64-to-int16.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
The file was modifiedllvm/test/DebugInfo/X86/fission-ranges.ll
The file was modifiedllvm/test/CodeGen/PowerPC/addegluecrash.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
The file was modifiedllvm/test/CodeGen/X86/avx-load-store.ll
The file was modifiedllvm/test/DebugInfo/X86/parameters.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/builtin-return-address-pacret.ll
The file was modifiedllvm/test/CodeGen/X86/pr32484.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved.ll
The file was modifiedllvm/test/CodeGen/ARM/ldrd.ll
The file was modifiedllvm/test/CodeGen/X86/pr32241.ll
The file was modifiedllvm/test/CodeGen/SystemZ/swifterror.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill192.mir
The file was modifiedllvm/test/CodeGen/ARM/thumb-big-stack.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll
The file was addedllvm/test/CodeGen/X86/bug47278-eflags-error.mir
The file was modifiedllvm/test/CodeGen/X86/pr1489.ll
The file was modifiedllvm/test/DebugInfo/AArch64/prologue_end.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
The file was addedllvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
The file was modifiedllvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
The file was modifiedllvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
The file was modifiedllvm/test/CodeGen/X86/phys-reg-local-regalloc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/anon_aggr.ll
The file was modifiedllvm/test/CodeGen/X86/pr42452.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/var_arg.ll
Commit a66fca44ac926b25820f0e9344db1947d966291b by Matthew.Arsenault
RegAllocFast: Add extra DBG_VALUE for live out spills

This allows LiveDebugValues to insert the proper DBG_VALUEs in live
out blocks if a spill is inserted before the use of a
register. Previously, this would see the register use as the last
DBG_VALUE, even though the stack slot should be treated as the live
out value.

This avoids an lldb test regression when D52010 is re-applied.
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
The file was addedllvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/DebugInfo/X86/fission-ranges.ll
The file was modifiedllvm/test/DebugInfo/X86/parameters.ll
The file was modifiedllvm/test/DebugInfo/X86/sret.ll
The file was modifiedllvm/test/DebugInfo/X86/subreg.ll
Commit d93459992e559e774e7b14208e5bd8bf27a58280 by Matthew.Arsenault
LiveDebugValues: Fix typos and indentation
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
Commit 5aa1119537fe6569b54d0da4d9d649a6940decff by Matthew.Arsenault
GlobalISel: Assert if MoreElements uses a non-vector type
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
Commit 2ef73025afda6481625b74eb99cdbc2eb1cfef95 by llvm-dev
[InstCombine] Remove %tmp variable names from bswap-fold tests

Appease update_test_checks script that was complaining about potential %TMP clashes
The file was modifiedllvm/test/Transforms/InstCombine/bswap-fold.ll
Commit 3a7487f903e2a6be29de39058eee2372e30798d5 by Xiangling.Liao
[FE] Use preferred alignment instead of ABI alignment for complete object when applicable

On some targets, preferred alignment is larger than ABI alignment in some cases. For example,
on AIX we have special power alignment rules which would cause that. Previously, to support
those cases, we added a “PreferredAlignment” field in the `RecordLayout` to store the AIX
special alignment values in “PreferredAlignment” as the community suggested.

However, that patch alone is not enough. There are places in the Clang where `PreferredAlignment`
should have been used instead of ABI-specified alignment. This patch is aimed at fixing those
spots.

Differential Revision: https://reviews.llvm.org/D86790
The file was addedclang/test/CodeGen/aix-alignment.c
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedclang/lib/CodeGen/ItaniumCXXABI.cpp
The file was modifiedclang/lib/CodeGen/CGExprCXX.cpp
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was addedclang/test/CodeGenCXX/aix-alignment.cpp
Commit 892fdc923f06adbef507ebe594fa7b48224d93f0 by ravishankarm
[mlir][Linalg] Generalize the logic to compute reassociation maps
while folding tensor_reshape op.

While folding reshapes that introduce unit extent dims, the logic to
compute the reassociation maps can be generalized to handle some
corner cases, for example, when the folded shape still has unit-extent
dims but corresponds to folded unit extent dims of the expanded shape.

Differential Revision: https://reviews.llvm.org/D88521
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
Commit b85de2c69cf3d6fbc2ad3439a6224667a58f704c by llvm-dev
[InstCombine] Add bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector tests

Add tests showing failure to correctly fold vector bswap(trunc(bswap(x))) intrinsic patterns
The file was modifiedllvm/test/Transforms/InstCombine/bswap-fold.ll
Commit 323d08e50a7bb80786dc00a8ade6ae49e1358393 by llvm-dev
[InstCombine] Fix bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector support

Use getScalarSizeInBits not getPrimitiveSizeInBits to determine the shift value at the element level.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/bswap-fold.ll
Commit 2c394bd4071d32000e2eed0f7d90fe7c576d7050 by benny.kra
[PowerPC] Avoid unused variable warning in Release builds

PPCFrameLowering.cpp:632:8: warning: unused variable 'isAIXABI' [-Wunused-variable]
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Commit 052c5bf40a9fc9ffe1bb2669763d8a0d2dea2b2e by zarko
[PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9

It looks like in some circumstances when compiling with `-mcpu=pwr9` we create an EXTSWSLI node when which causes llc to fail. No such error occurs in pwr8 or lower.

This occurs in 32BIT AIX and BE Linux. the cause seems to be that the default return in combineSHL is to create an EXTSWSLI node.  Adding a check for whether we are in PPC64 before that fixes the issue.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D87046
The file was addedllvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit f425418fc4ebd989c6c3d59d20e7fe37cb29259c by llvm-dev
[InstCombine] Add tests for 'partial' bswap patterns

As mentioned on PR47191, if we're bswap'ing some bytes and the zero'ing the remainder we can perform this as a bswap+mask which helps us match 'partial' bswaps as a first step towards folding into a more complex bswap pattern.
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit d6de40f8865e2c016731f9b63d8a0a218ce1b74f by mtrofin
[NFC][regalloc] Make VirtRegAuxInfo part of allocator state

All the state of VRAI is allocator-wide, so we can avoid creating it
every time we need it. In addition, the normalization function is
allocator-specific. In a next change, we can simplify that design in
favor of just having it as a virtual member.

Differential Revision: https://reviews.llvm.org/D88499
The file was modifiedllvm/include/llvm/CodeGen/CalcSpillWeights.h
The file was modifiedllvm/lib/CodeGen/RegAllocBasic.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was modifiedllvm/lib/CodeGen/CalcSpillWeights.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocPBQP.cpp
Commit 05ae04c396519cca9ef50d3b9cafb0cd9c87d1d7 by simon.moll
[DA][SDA] SyncDependenceAnalysis re-write

This patch achieves two things:
1. It breaks up the `join_blocks` interface between the SDA to the DA to
   return two separate sets for divergent loops exits and divergent,
disjoint path joins.
2. It updates the SDA algorithm to run in O(n) time and improves the
   precision on divergent loop exits.

This fixes `https://bugs.llvm.org/show_bug.cgi?id=46372` (by virtue of
the improved `join_blocks` interface) and revealed an imprecise expected
result in the `Analysis/DivergenceAnalysis/AMDGPU/hidden_loopdiverge.ll`
test.

Reviewed By: sameerds

Differential Revision: https://reviews.llvm.org/D84413
The file was modifiedllvm/lib/Analysis/SyncDependenceAnalysis.cpp
The file was modifiedllvm/test/Analysis/DivergenceAnalysis/AMDGPU/hidden_loopdiverge.ll
The file was modifiedllvm/include/llvm/Analysis/SyncDependenceAnalysis.h
The file was modifiedllvm/include/llvm/Analysis/DivergenceAnalysis.h
The file was modifiedllvm/lib/Analysis/DivergenceAnalysis.cpp
The file was modifiedllvm/test/Analysis/DivergenceAnalysis/AMDGPU/trivial-join-at-loop-exit.ll
Commit 1034262e0a38f0bd755e68aa41b6bb856ebd2eb8 by jam
[VE] Support TargetBlockAddress

Change to handle TargetBlockAddress and add a regression test for it.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D88576
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was addedllvm/test/CodeGen/VE/blockaddress.ll
The file was modifiedllvm/lib/Target/VE/VEMCInstLower.cpp
Commit 4fbd83c716dbc1d68e0aac5d71d201b664762489 by aeubanks
[ObjCARCAA][NewPM] Add already ported objc-arc-aa to PassRegistry.def

Also add missing AnalysisKey definition.
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/test/Transforms/ObjCARC/gvn.ll
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/lib/Analysis/ObjCARCAliasAnalysis.cpp
Commit dd4fb7c8cfe394a3290bd19a1eac03435472ccfa by clementval
[mlir][openacc] Remove -allow-unregistred-dialect from ops and invalid tests

Switch to a dummy op in the test dialect so we can remove the -allow-unregistred-dialect
on ops.mlir and invalid.mlir. Change after comment on D88272.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D88587
The file was modifiedmlir/test/Dialect/OpenACC/invalid.mlir
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir
Commit 4fcd1a8e6528ca42fe656f2745e15d2b7f5de495 by vyng
[llvm-exegesis] Add option to check the hardware support for a given feature before benchmarking.

This is mostly for the benefit of the LBR latency mode.
Right now, it performs no checking. If this is run on non-supported hardware, it will produce all zeroes for latency.

Differential Revision: https://reviews.llvm.org/D85254
The file was modifiedllvm/tools/llvm-exegesis/lib/Target.h
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/Target.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/X86Counter.cpp
The file was modifiedllvm/tools/llvm-exegesis/llvm-exegesis.cpp
The file was modifiedllvm/test/tools/llvm-exegesis/X86/lbr/lit.local.cfg
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/X86Counter.h
Commit 719ab7309eb7b7b5d802273b0f1871d6cdb965b1 by peter
scudo: Make it thread-safe to set some runtime configuration flags.

Move some of the flags previously in Options, as well as the
UseMemoryTagging flag previously in the primary allocator, into an
atomic variable so that it can be updated while other threads are
running. Relaxed accesses are used because we only have the requirement
that the other threads see the new value eventually.

The code is set up so that the variable is generally loaded once per
allocation function call with the exception of some rarely used code
such as error handlers. The flag bits can generally stay in a register
during the execution of the allocation function which means that they
can be branched on with minimal overhead (e.g. TBZ on aarch64).

Differential Revision: https://reviews.llvm.org/D88523
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
The file was modifiedcompiler-rt/lib/scudo/standalone/primary32.h
The file was modifiedcompiler-rt/lib/scudo/standalone/primary64.h
The file was addedcompiler-rt/lib/scudo/standalone/options.h
The file was modifiedcompiler-rt/lib/scudo/standalone/wrappers_c.inc
The file was modifiedcompiler-rt/lib/scudo/standalone/atomic_helpers.h
Commit 2ab87702231e193ca170aa8ad4caa9f98bc7ced1 by aeubanks
[test][SampleProfile][NewPM] Fix some tests under NPM
The file was modifiedllvm/test/Transforms/SampleProfile/discriminator.ll
The file was modifiedllvm/test/Transforms/SampleProfile/branch.ll
The file was modifiedllvm/test/Transforms/SampleProfile/fnptr.ll
The file was modifiedllvm/test/Transforms/SampleProfile/propagate.ll
The file was modifiedllvm/test/Transforms/SampleProfile/offset.ll
The file was modifiedllvm/test/Transforms/SampleProfile/remap.ll
The file was modifiedllvm/test/Transforms/SampleProfile/calls.ll
Commit 73fb9698c0573778787e77a8ffa57e7fa3caebd4 by ro
[asan][test] Several Posix/unpoison-alternate-stack.cpp fixes

`Posix/unpoison-alternate-stack.cpp` currently `FAIL`s on Solaris/i386.
Some of the problems are generic:

- `clang` warns compiling the testcase:

  compiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp:83:7: warning: nested designators are a C99 extension [-Wc99-designator]
        .sa_sigaction = signalHandler,
        ^~~~~~~~~~~~~
  compiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp:84:7: warning: ISO C++ requires field designators to be specified in declaration order; field '_funcptr' will be initialized after field 'sa_flags' [-Wreorder-init-list]
        .sa_flags = SA_SIGINFO | SA_NODEFER | SA_ONSTACK,
        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

  and some more instances.  This can all easily be avoided by initializing
  each field separately.

- The test `SEGV`s in `__asan_memcpy`.  The default Solaris/i386 stack size
  is only 4 kB, while `__asan_memcpy` tries to allocate either 5436
  (32-bit) or 10688 bytes (64-bit) on the stack.  This patch avoids this by
  requiring at least 16 kB stack size.

- Even without `-fsanitize=address` I get an assertion failure:

  Assertion failed: !isOnSignalStack(), file compiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp, line 117

  The fundamental problem with this testcase is that `longjmp` from a
  signal handler is highly unportable; XPG7 strongly warns against it and
  it is thus unspecified which stack is used when `longjmp`ing from a
  signal handler running on an alternative stack.

  So I'm `XFAIL`ing this testcase on Solaris.

Tested on `amd64-pc-solaris2.11` and `x86_64-pc-linux-gnu`.

Differential Revision: https://reviews.llvm.org/D88501
The file was modifiedcompiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp
Commit 8d8cb1ad80b7074ac60d070fae89261894d34a0d by dancgr
[AArch64] Avoid pairing loads when the base reg is modified

When pairing loads, we should check if in between the two loads the
base register has been modified. If that is the case then avoid pairing
them because the second load actually loads from a different address.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D86956
The file was modifiedllvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
The file was addedllvm/test/CodeGen/AArch64/aarch64-ldst-modified-baseReg.mir
Commit 187686bea3878c0bf2b150d784e7eab223434e25 by spatel
[CodeGen] add test for NAN creation; NFC

This goes with the APFloat change proposed in
D88238.
This is copied from the MIPS-specific test in
builtin-nan-legacy.c to verify that the normal
behavior is correct on other targets without the
complication of an inverted quiet bit.
The file was addedclang/test/CodeGen/builtin-nan-exception.c
Commit 700e63293eea4a23440f300b1e9125ca2e80c6e9 by flo
[Sema] Support Comma operator for fp16 vectors.

The current half vector was enforcing an assert expecting
"(LHS is half vector) == (RHS is half vector)"
for comma.

Reviewed By: ahatanak, fhahn

Differential Revision: https://reviews.llvm.org/D88265
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/Sema/fp16vec-sema.c

Summary

  1. [zorg] [PowerPC] Limit number of threads to 64 on clang-ppc64le-rhel buildbot (details)
Commit c2cc01b14ef84bee845318bde3ae623091934b96 by saghir
[zorg] [PowerPC] Limit number of threads to 64 on clang-ppc64le-rhel buildbot

This patch reduces the number of threads from 256 to 64 on the
clang-ppc64le-rhel buildbot.

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D88586
The file was modifiedbuildbot/osuosl/master/config/builders.py