SuccessChanges

Summary

  1. [SCEV] Limited support for unsigned preds in isImpliedViaOperations (details)
  2. [MLIR] Updates around MemRef Normalization (details)
  3. [AArch64] Omit SEH directives for the epilogue if none are needed (details)
  4. [SVE][CodeGen] Add new EVT/MVT getFixedSizeInBits() functions (details)
  5. [SVE][CodeGen] Fix implicit TypeSize->uint64_t casts in TypePromotion (details)
  6. [WebAssembly] Emulate v128.const efficiently (details)
  7. [clangd] Drop dependence on standard library in check.test (details)
  8. Handle unused variable without asserts (details)
  9. [yaml2obj][elf2yaml] - Add a support for the `EntSize` field for `SHT_HASH` sections. (details)
  10. Fix limit behavior of dynamic alloca (details)
  11. [clangd] Remove Tweak::Intent, use CodeAction kind directly. NFC (details)
  12. [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV. (details)
  13. [ARM] Prevent constants from iCmp instruction from being hoisted if part of a min(max()) pattern (details)
  14. [InstCombine] Add partial bswap test from D88578 (details)
  15. [mlir] Add a subtensor operation (details)
  16. [mlir] Add canonicalization for the `subtensor` op (details)
  17. [InstCombine] Add some basic vector bswap tests (details)
  18. [clangd][lit] Update document-link.test to respect custom resource-dir locations (details)
  19. [mlir] Add subtensor_insert operation (details)
  20. [MLIR][LLVM] Fixed `topologicalSort()` to iterative version (details)
  21. [GVN LoadPRE] Add test to show an opportunty. (details)
  22. [PhaseOrdering] Add test that requires peeling before vectorization. (details)
  23. [clangd] Make PopulateSwitch a fix. (details)
  24. [AArch64] Add CPU Cortex-R82 (details)
  25. [InstCombine] Add partial bswap vector test from D88578 (details)
  26. [SLP] Add test where reduction result is used in PHI. (details)
  27. LoopAccessAnalysis.cpp - use const reference in for-range loops. NFCI. (details)
  28. BlockFrequencyInfoImpl.h - use const references to avoid FrequencyData copies. NFCI. (details)
  29. [libc++] Move the weak symbols list to libc++abi (details)
Commit b8ac19cf1cca5faec8b4404bb0f666cb63c9e1de by mkazantsev
[SCEV] Limited support for unsigned preds in isImpliedViaOperations

The logic there only considers `SLT/SGT` predicates. We can use the same logic
for proving `ULT/UGT` predicates if all involved values are non-negative.

Adding full-scale support for unsigned might be challenging because of code amount,
so we can consider this in the future.

Differential Revision: https://reviews.llvm.org/D88087
Reviewed By: reames
The file was modifiedllvm/unittests/Analysis/ScalarEvolutionTest.cpp
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 47df8c57e4ed01fa0101aa0b320fc7cf5a90df28 by stephen.neuendorffer
[MLIR] Updates around MemRef Normalization

The documentation for the NormalizeMemRefs pass and the associated MemRefsNormalizable
traits was confusing and not on the website.  This update clarifies the language
around the difference between a MemRef Type, an operation that accesses the value of
MemRef Type, and better documents the limitations of the current implementation.
This patch also includes some basic debugging information for the pass so people
might have a chance of figuring out why it doesn't work on their code.

Differential Revision: https://reviews.llvm.org/D88532
The file was modifiedmlir/lib/Transforms/NormalizeMemRefs.cpp
The file was modifiedmlir/docs/Traits.md
The file was modifiedmlir/include/mlir/Transforms/Passes.td
The file was modifiedmlir/include/mlir/IR/OpDefinition.h
Commit afb4e0f289ac6d020faafda078642a3716629abd by martin
[AArch64] Omit SEH directives for the epilogue if none are needed

For these cases, we already omit the prologue directives, if
(!AFI->hasStackFrame() && !windowsRequiresStackProbe && !NumBytes).

When writing the epilogue (after the prolog has been written), if
the function doesn't have the WinCFI flag set (i.e. if no prologue
was generated), assume that no epilogue will be needed either,
and don't emit any epilog start pseudo instruction. After completing
the epilogue, make sure that it actually matched the prologue.

Previously, when epilogue start/end was generated, but no prologue,
the unwind info for such functions actually was huge; 12 bytes xdata
(4 bytes header, 4 bytes for one non-folded epilogue header, 4 bytes
for padded opcodes) and 8 bytes pdata. Because the epilog consisted of
one opcode (end) but the prolog was empty (no .seh_endprologue), the
epilogue couldn't be folded into the prologue, and thus couldn't be
considered for packed form either.

On a 6.5 MB DLL with 110 KB pdata and 166 KB xdata, this gets rid of
38 KB pdata and 62 KB xdata.

Differential Revision: https://reviews.llvm.org/D88641
The file was modifiedllvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll
The file was modifiedllvm/test/CodeGen/AArch64/win64-nocfi.ll
The file was modifiedllvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll
The file was modifiedllvm/test/CodeGen/AArch64/lround-conv-win.ll
The file was modifiedllvm/test/CodeGen/AArch64/win_cst_pool.ll
The file was modifiedllvm/test/CodeGen/AArch64/powi-windows.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/lrint-conv-win.ll
Commit b8ce6a67568ba16683a2b1a5e8ebd28d5d537874 by david.sherwood
[SVE][CodeGen] Add new EVT/MVT getFixedSizeInBits() functions

When we know that a particular type is always going to be fixed
width we have so far been writing code like this:

  getSizeInBits().getFixedSize()

Since we are doing this in quite a few places now it seems to make
sense to add a new helper function that allows us to replace
these calls with a single getFixedSizeInBits() call.

Differential Revision: https://reviews.llvm.org/D88649
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.h
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Commit b0ce9f0f4cff7df243b72e308ec863f012724475 by david.sherwood
[SVE][CodeGen] Fix implicit TypeSize->uint64_t casts in TypePromotion

The TypePromotion pass only operates on scalar types so I've fixed up
all places where we were relying upon the implicit cast from
TypeSize->uint64_t.

Differential Revision: https://reviews.llvm.org/D88575
The file was modifiedllvm/lib/CodeGen/TypePromotion.cpp
Commit 542523a61a21c13e7f244bcf821b0fdeb8c6bb24 by tlively
[WebAssembly] Emulate v128.const efficiently

v128.const was recently implemented in V8, but until it rolls into Chrome
stable, we can't enable it in the WebAssembly backend without breaking origin
trial users. So far we have been lowering build_vectors that would otherwise
have been lowered to v128.const to splats followed by sequences of replace_lane
instructions to initialize each lane individually. That produces large and
inefficient code, so this patch introduces new logic to lower integer vector
constants to a single i64x2.splat where possible, with at most a single
i64x2.replace_lane following it if necessary.

Adapted from a patch authored by @omnisip.

Differential Revision: https://reviews.llvm.org/D88591
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-build-vector.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
Commit bc18d8d9b705d31a94c51900c8b18e4feaf9c7fb by sam.mccall
[clangd] Drop dependence on standard library in check.test
The file was modifiedclang-tools-extra/clangd/test/check.test
Commit bfd7ee92ccec2904d98b20b475f48addadc4ec5f by tpopp
Handle unused variable without asserts
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertSkips.cpp
Commit 5829dc925002aaf5e80189924e59d238d3d2a4d1 by grimar
[yaml2obj][elf2yaml] - Add a support for the `EntSize` field for `SHT_HASH` sections.

Specification  for SHT_HASH table says (https://refspecs.linuxbase.org/elf/gabi4+/ch5.dynamic.html#hash)
that it contains Elf32_Word entries for both 32/64 bit objects.

Currently both GNU linkers and LLD sets the `sh_entsize` field to `4`.

At the same time, `yaml2obj` ignores the `EntSize` field for SHT_HASH sections.
This patch fixes this and also adds a support for obj2yaml: it will not
dump this field when the `sh_entsize` contains the default value (`4`).

Differential revision: https://reviews.llvm.org/D88652
The file was modifiedllvm/test/tools/obj2yaml/ELF/hash-section.yaml
The file was modifiedllvm/test/tools/yaml2obj/ELF/section-headers-exclude.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
The file was modifiedllvm/test/tools/yaml2obj/ELF/hash-section.yaml
Commit 9573c9f2a363da71b2c07a3add4e52721e6028a0 by sguelton
Fix limit behavior of dynamic alloca

When the allocation size is 0, we shouldn't probe. Within [1,  PAGE_SIZE], we
should probe once etc.

This fixes https://bugs.llvm.org/show_bug.cgi?id=47657

Differential Revision: https://reviews.llvm.org/D88548
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll
Commit 17747d2ec8ec4471748197db54c8703f0c07c91c by sam.mccall
[clangd] Remove Tweak::Intent, use CodeAction kind directly. NFC

Intent was a nice idea but it ends up being a bit awkward/heavyweight
without adding much.

In particular, it makes it hard to implement `CodeActionParams.only` properly
(there's an inheritance hierarchy for kinds).

Differential Revision: https://reviews.llvm.org/D88427
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/PopulateSwitch.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/RemoveUsingNamespace.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ExtractFunction.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/SwapIfBranches.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Tweak.h
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ExpandAutoType.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ExtractVariable.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ObjCLocalizeStringLiteral.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/DumpAST.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ExpandMacro.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/AnnotateHighlightings.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/RawStringLiteral.cpp
Commit 067add7b5fd22c879bd2bbf5d55f4fb9b63047bf by kai.wang
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.

Implement vmsge{u}.vx pseudo instruction.

According to RISC-V V specification, there are different scenarios for this
pseudo instruction. I list them below.

unmasked va >= x

  pseudoinstruction: vmsge{u}.vx vd, va, x
  expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd

masked va >= x, vd != v0

  pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
  expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0

masked va >= x, vd == v0

  pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
  expansion: vmslt{u}.vx vt, va, x;  vmandnot.mm vd, vd, vt

Use pseudo instruction to model vmsge{u}.vx. The pseudo instruction will convert
to different expansion according to the condition.

Differential Revision: https://reviews.llvm.org/D84732
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
The file was modifiedllvm/test/MC/RISCV/rvv/compare.s
The file was modifiedllvm/test/MC/RISCV/rvv/invalid.s
Commit f7c0e2b8f26fc6573f663f482aa64443ab6a6e71 by meera.nakrani
[ARM] Prevent constants from iCmp instruction from being hoisted if part of a min(max()) pattern

Marks constants of an ICmp instruction as free if it's only user is a select
instruction that is part of a min(max()) pattern. Ensures that in loops, in
particular when loop unrolling is turned on, SSAT will still be correctly generated.

Differential Revision: https://reviews.llvm.org/D88662
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was addedllvm/test/CodeGen/ARM/ssat-unroll-loops.ll
Commit 670e60c0238bb8e9fb39947017dc3b5459c8ee60 by llvm-dev
[InstCombine] Add partial bswap test from D88578
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit e3de249a4c94d6962b36c2b4747c134d152bed37 by ntv
[mlir] Add a subtensor operation

This revision introduces a `subtensor` op, which is the counterpart of `subview` for a tensor operand. This also refactors the relevant pieces to allow reusing the `subview` implementation where appropriate.

This operation will be used to implement tiling for Linalg on tensors.
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.h
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/test/lib/Transforms/TestLinalgTransforms.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/test/IR/core-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Loops.cpp
The file was modifiedmlir/test/IR/invalid-ops.mlir
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
Commit 787bf5e383a32b3ebc87332ff9e868db8f937056 by ntv
[mlir] Add canonicalization for the `subtensor` op

Differential revision: https://reviews.llvm.org/D88656
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/Transforms/canonicalize.mlir
Commit ec07ae2a833ef5b2282811f51fdfbd043c611936 by llvm-dev
[InstCombine] Add some basic vector bswap tests

We get the vNi16 cases already via matching as a rotate followed by the fshl -> bswap combines
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit 54c03d8f7da72fdf1a9e122391c51c2f0ea7b298 by kadircet
[clangd][lit] Update document-link.test to respect custom resource-dir locations

Differential Revision: https://reviews.llvm.org/D88721
The file was modifiedclang-tools-extra/clangd/test/document-link.test
Commit cf9503c1b752062d9abfb2c7922a50574d9c5de4 by ntv
[mlir] Add subtensor_insert operation

Differential revision: https://reviews.llvm.org/D88657
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/IR/core-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit d4568ed74328a28f79bee0738edf3d065232ced5 by georgemitenk0v
[MLIR][LLVM] Fixed `topologicalSort()` to iterative version

Instead of recursive helper method `topologicalSortImpl()`,
sort's implementation is moved to `topologicalSort()` function's
body directly. `llvm::ReversePostOrderTraversal` is used to create
a traversal of blocks in reverse post order.

Reviewed By: kiranchandramohan, rriddle

Differential Revision: https://reviews.llvm.org/D88544
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
Commit 8ae1369f794c1e6da6aaf1b540e3c98d1e8a16c4 by serguei.katkov
[GVN LoadPRE] Add test to show an opportunty.

We can use context to prove that load can be safely executed
at a point where load is being hoisted.
The file was addedllvm/test/Transforms/GVN/loadpre-context.ll
Commit 6481a764950055a08a5b8e0ba728e7f7299f932c by flo
[PhaseOrdering] Add test that requires peeling before vectorization.

Test case for PR47671.
The file was addedllvm/test/Transforms/PhaseOrdering/X86/peel-before-lv-to-enable-vectorization.ll
Commit 57ac47d78885c9a3d712692b1476d99840591db1 by sam.mccall
[clangd] Make PopulateSwitch a fix.

It fixes the -Wswitch warning, though we mark it as a fix even if that is off.
This makes it the "recommended" action on an incomplete switch, which seems OK.

Differential Revision: https://reviews.llvm.org/D88726
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/PopulateSwitch.cpp
Commit 8825fec37e73eea1bc3e4f5c125e1fd02d002d6c by sjoerd.meijer
[AArch64] Add CPU Cortex-R82

This adds support for -mcpu=cortex-r82. Some more information about this
core can be found here:

https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r82

One note about the system register: that is a bit of a refactoring because of
small differences between v8.4-A AArch64 and v8-R AArch64.

This is based on patches from Mark Murray and Mikhail Maltsev.

Differential Revision: https://reviews.llvm.org/D88660
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.h
The file was modifiedclang/test/Preprocessor/aarch64-target-features.c
The file was modifiedclang/test/Driver/aarch64-dotprod.c
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.cpp
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/include/llvm/Support/AArch64TargetParser.def
The file was modifiedclang/lib/Driver/ToolChains/Arch/AArch64.cpp
The file was modifiedllvm/lib/Support/AArch64TargetParser.cpp
The file was modifiedllvm/unittests/Support/TargetParserTest.cpp
The file was modifiedclang/test/Driver/aarch64-cpus.c
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
The file was modifiedclang/lib/Basic/Targets/AArch64.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SystemOperands.td
Commit 53fb9d062b42e4d46c88766aaac8fb88bab8fb77 by llvm-dev
[InstCombine] Add partial bswap vector test from D88578
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit bb448a248371b48dbca8d647b7aaf9393154cf3d by flo
[SLP] Add test where reduction result is used in PHI.

Test case for PR47670.
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
Commit 71b89b14934d99f32da150f62042aa9e09113b5f by llvm-dev
LoopAccessAnalysis.cpp - use const reference in for-range loops. NFCI.
The file was modifiedllvm/lib/Analysis/LoopAccessAnalysis.cpp
Commit 4edd74a1986f5e347a1f2e060df7f6372938fa9e by llvm-dev
BlockFrequencyInfoImpl.h - use const references to avoid FrequencyData copies. NFCI.
The file was modifiedllvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
Commit c7d4aa711ab7981358b5e17e56f1fb6f7f585ac1 by Louis Dionne
[libc++] Move the weak symbols list to libc++abi

Those symbols are exported from libc++abi in the first place, so it
makes more sense to have them there.
The file was modifiedlibcxx/src/CMakeLists.txt
The file was addedlibcxxabi/lib/weak.exp
The file was removedlibcxx/lib/weak.exp
The file was modifiedlibcxxabi/src/CMakeLists.txt