SuccessChanges

Summary

  1. [Coroutines][NewPM] Fix coroutine tests under new pass manager (details)
  2. Revert "[RFC] Factor out repetitive cmake patterns for llvm-style projects" (details)
  3. [X86] Remove usesCustomInserter from MWAITX_SAVE_EBX and MWAITX_SAVE_RBX. NFC (details)
  4. [X86] Correct the implicit defs/uses for the MWAITX pseudo instructions. (details)
  5. [DomTree] findNearestCommonDominator: assert the nodes are in tree (details)
  6. llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits (details)
  7. [NFCI] Remove unnecessary trailing undef in RuntimeLibcalls.def (details)
  8. [NewPM] collapsing nested pass mangers of the same type (details)
  9. llvm-dwarfdump: Print addresses in debug_line to the parsed address size (details)
  10. [X86] Remove MWAITX_SAVE_EBX pseudo instruction. Always save/restore the full %rbx register even in gnux32. (details)
  11. llvm-dwarfdump: Add support for DW_RLE_startx_endx (details)
  12. [HIP] Add option --gpu-instrument-lib= (details)
  13. Revert "[HIP] Add option --gpu-instrument-lib=" (details)
  14. Recommit "[HIP] Add option --gpu-instrument-lib=" (details)
  15. [HIP] Fix default output file for -E (details)
  16. [HIP] Fix -fgpu-allow-device-init option (details)
  17. llvm-dwarfdump: Don't try to parse rnglist tables when dumping CUs (details)
  18. [X86] MWAITX_SAVE_RBX should not have EBX as an implicit use. (details)
  19. [lldb] [test/Register] Attempt to fix x86-fp-read.test on Darwin (details)
  20. [llvm] Rename DwarfFile to DWARFFile to fix ODR violation (NFC) (details)
  21. [RISCV][ASAN] mark asan as supported for RISCV64 and enable tests (details)
  22. [DebugInfo] Improve dbg preservation in LSR. (details)
  23. [AST][RecoveryExpr] Popagate the error-bit from a VarDecl's initializer to DeclRefExpr. (details)
  24. [TableGen][GlobalISel] add handling of nested *_SUBREG (details)
  25. [AMDGPU] Split R600 and GCN bfe patterns (details)
  26. [AMDGPU] Make bfe patterns divergence-aware (details)
  27. Promote transpose from linalg to standard dialect (details)
  28. [VE] Support register and frame-index pair correctly (details)
  29. [mlir] Fix SubViewOp doc in .td (details)
  30. [AMDGPU] Use tablegen for argument indices (details)
  31. Reland "[lldb] Don't send invalid region addresses to lldb server" (details)
  32. [AST][RecoveryExpr] Fix a crash on undeduced type. (details)
  33. [clangd] Remove unused using-decls in TypeHierarchyTests, NFC. (details)
  34. [TableGen] Added a function for identification of unsupported opcodes. (details)
  35. [AMDGPU][RegAlloc][SplitKit] Pre-commit test for D88821 (details)
  36. [ASTImporter][AST] Fix structural equivalency crash on dependent FieldDecl (details)
Commit 37010d4ddf477d3cc60792a92918af5f2f6e42c3 by aeubanks
[Coroutines][NewPM] Fix coroutine tests under new pass manager

Some new function parameter attributes are derived under NPM.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D88760
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-value.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-once-value.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-swifterror.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-alloca.ll
Commit b0dce6b37f15f487064223f7e3e6a5701a9d7bff by stephen.neuendorffer
Revert "[RFC] Factor out repetitive cmake patterns for llvm-style projects"

This reverts commit e9b87f43bde8b5f0d8a79c5884fdce639b12e0ca.

There are issues with macros generating macros without an obvious simple fix
so I'm going to revert this and try something different.
The file was modifiedmlir/examples/toy/CMakeLists.txt
The file was modifiedmlir/tools/mlir-linalg-ods-gen/CMakeLists.txt
The file was modifiedmlir/CMakeLists.txt
The file was modifiedmlir/cmake/modules/AddMLIR.cmake
The file was modifiedmlir/test/Examples/standalone/test.toy
The file was removedllvm/cmake/modules/LLVMProjectOptions.cmake
The file was modifiedmlir/tools/mlir-rocm-runner/CMakeLists.txt
The file was modifiedmlir/tools/mlir-cpu-runner/CMakeLists.txt
The file was modifiedmlir/tools/mlir-translate/CMakeLists.txt
The file was modifiedmlir/tools/mlir-opt/CMakeLists.txt
The file was removedllvm/cmake/modules/LLVMProjectTargets.cmake
The file was modifiedmlir/tools/mlir-vulkan-runner/CMakeLists.txt
The file was modifiedmlir/examples/standalone/CMakeLists.txt
The file was modifiedmlir/examples/standalone/standalone-opt/CMakeLists.txt
The file was modifiedmlir/examples/standalone/standalone-translate/CMakeLists.txt
The file was modifiedmlir/tools/mlir-reduce/CMakeLists.txt
The file was modifiedmlir/tools/mlir-cuda-runner/CMakeLists.txt
Commit 0db97234cf490e464c82f2191fef2d8a163106fb by craig.topper
[X86] Remove usesCustomInserter from MWAITX_SAVE_EBX and MWAITX_SAVE_RBX. NFC

These are now emitted by a CustomInserter rather than using a custom
inserter themselves.
The file was modifiedllvm/lib/Target/X86/X86InstrCompiler.td
Commit 952dfd76c6696207cc290c4f6f15d5dea5cca795 by craig.topper
[X86] Correct the implicit defs/uses for the MWAITX pseudo instructions.

MWAITX doesn't touch EFLAGS so no pseudos should def EFLAGS.

The SAVE_EBX/RBX pseudos only needs to def the EBX register that
the expansion overwrites. The EAX and ECX registers are only read.

The pseudo emitted during isel that is used by the custom inserter
shouldn't have any implicit defs or uses since everything is in
vregs.
The file was modifiedllvm/lib/Target/X86/X86InstrCompiler.td
Commit 1065f3439bad59323f16e7c8ee568c7d94dcd952 by i
[DomTree] findNearestCommonDominator: assert the nodes are in tree

i.e. they cannot be unreachable from the entry (which usually indicate usage errors).
This change allows the removal of some nullptr checks.

Reviewed By: kuhar

Differential Revision: https://reviews.llvm.org/D88758
The file was modifiedllvm/include/llvm/Support/GenericDomTree.h
Commit ea83e0b17ecf5dc0cf228afb334aa72ce9b5aec1 by dblaikie
llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits

Few places did this already - refactor them all into a common helper.
The file was modifiedllvm/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s
The file was modifiedllvm/test/MC/MachO/gen-dwarf.s
The file was modifiedllvm/test/MC/WebAssembly/debug-localvar.ll
The file was modifiedllvm/test/DebugInfo/MIR/Hexagon/bundled-call-pr44001.mir
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/gnu_call_site.s
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDie.cpp
The file was modifiedllvm/test/DebugInfo/MIR/ARM/subregister-full-piece.mir
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugArangeSet.cpp
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFFormValue.h
The file was modifiedllvm/test/DebugInfo/X86/debug-loc-offset.mir
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFFormValue.cpp
The file was modifiedllvm/test/MC/WebAssembly/dwarfdump.ll
The file was modifiedllvm/test/DebugInfo/X86/debug_addr.ll
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugRnglists.cpp
The file was modifiedllvm/test/MC/ARM/dwarf-asm-nonstandard-section.s
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/tombstone.s
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFAddressRange.cpp
The file was modifiedllvm/test/DebugInfo/Mips/dbg-call-site-low-pc.ll
The file was modifiedllvm/test/MC/ARM/dwarf-asm-single-section.s
Commit 83cc498c38d2e4baaf3a233ae73fc49e24ac8898 by Yuanfang Chen
[NFCI] Remove unnecessary trailing undef in RuntimeLibcalls.def

All uses of the file undef the macro already.
The file was modifiedllvm/include/llvm/IR/RuntimeLibcalls.def
Commit 2c94d88e076990a7b533578a392a150d4b9b0fa8 by Yuanfang Chen
[NewPM] collapsing nested pass mangers of the same type

This is one of the reason for extra invalidations in D84959. In
practice, I don't think we have use cases needing this. This simplifies
the pipeline a bit and prune corner cases when considering
invalidations.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D85676
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedllvm/test/Other/new-pass-manager.ll
The file was modifiedclang/test/CodeGen/thinlto-distributed-newpm.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was modifiedllvm/test/Other/pass-pipeline-parsing.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/include/llvm/IR/PassManager.h
The file was modifiedllvm/test/Other/new-pm-defaults.ll
Commit 628a319475dceac307add6953df028ec372e7f4e by dblaikie
llvm-dwarfdump: Print addresses in debug_line to the parsed address size
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/tombstone.s
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
Commit 4b38ceb0ebd7ed5fe1d5cbaf981060227515fb6e by craig.topper
[X86] Remove MWAITX_SAVE_EBX pseudo instruction. Always save/restore the full %rbx register even in gnux32.

ebx/rbx only needs to be saved when 64-bit registers are supported
anyway. It should be fine to save/restore the whole rbx register
even in gnux32 where the base is technically just ebx.

This matches what we do for cmpxchg16b where rbx is saved/restored
regardless of gnux32.
The file was modifiedllvm/lib/Target/X86/X86InstrCompiler.td
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp
The file was modifiedllvm/test/CodeGen/X86/base-pointer-and-mwaitx.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 92c45e4ee2511399484e8af26b66ba37ad0ed8e7 by dblaikie
llvm-dwarfdump: Add support for DW_RLE_startx_endx
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/debug_rnglists.s
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugRnglists.cpp
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/tombstone.s
Commit 64f7790e7d2309b5d38949921a256acf8068e659 by Yaxun.Liu
[HIP] Add option --gpu-instrument-lib=

Add an option --gpu-instrument-lib= to allow users to specify
an instrument device library. This is for supporting -finstrument
in device code for debugging/profiling tools.

Differential Revision: https://reviews.llvm.org/D88557
The file was modifiedclang/test/Driver/hip-device-libs.hip
The file was modifiedclang/include/clang/Driver/Options.td
The file was addedclang/test/Driver/Inputs/hip_multiple_inputs/instrument.bc
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
Commit fef0ebbc0b39167656bd11283e3084b000b309dd by Yaxun.Liu
Revert "[HIP] Add option --gpu-instrument-lib="

This reverts commit 64f7790e7d2309b5d38949921a256acf8068e659 due
to regression in hip-device-libs.hip.
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/Driver/hip-device-libs.hip
The file was removedclang/test/Driver/Inputs/hip_multiple_inputs/instrument.bc
Commit 9756a402f297d0030689aaade3651785b7496649 by Yaxun.Liu
Recommit "[HIP] Add option --gpu-instrument-lib="

recommit 64f7790e7d2309b5d38949921a256acf8068e659 after
fixing hip-device-libs.hip.
The file was addedclang/test/Driver/Inputs/hip_multiple_inputs/instrument.bc
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
The file was modifiedclang/test/Driver/hip-device-libs.hip
Commit 5b551b79d3bba5a8a282bf5f72c7baaccf925870 by Yaxun.Liu
[HIP] Fix default output file for -E

By convention the default output file for -E is "-" (stdout).
This is expected by tools like ccache, which uses output
of -E to determine if a file and its dependence has changed.

Currently clang does not use stdout as default output file for -E
for HIP, which causes ccache not working.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D88730
The file was modifiedclang/lib/Driver/Driver.cpp
The file was modifiedclang/test/Driver/hip-output-file-name.hip
Commit e372c1d7624e2402a5f91a640780fb32649922b6 by Yaxun.Liu
[HIP] Fix -fgpu-allow-device-init option

The option needs to be passed to both host and device compilation.

Differential Revision: https://reviews.llvm.org/D88550
The file was modifiedclang/test/Driver/hip-options.hip
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
Commit 6d0be74af5555f7bc56ac72cbd98ff270fd1291b by dblaikie
llvm-dwarfdump: Don't try to parse rnglist tables when dumping CUs

It's not possible to do this in complete generality - a CU using a
sec_offset DW_AT_ranges has no way of knowing where its rnglists
contribution starts, so should not attempt to parse any full rnglist
table/header to do so. And even using FORM_rnglistx there's no need to
parse the header - the offset can be computed using the CU's DWARF
format (32 or 64) to compute offset entry sizes, and then the list
parsed at that offset without ever trying to find a rnglist contribution
header immediately prior to the rnglists_base.
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFListTable.h
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/tombstone.s
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h
The file was modifiedllvm/test/DebugInfo/X86/dwarfdump-rnglists.s
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFUnit.cpp
The file was modifiedllvm/test/DebugInfo/X86/dwarfdump-rnglists-dwarf64.s
Commit b18026114ab1410d531559ad6d9f1b445b98a35f by craig.topper
[X86] MWAITX_SAVE_RBX should not have EBX as an implicit use.

RBX was copied to a virtual register before this instruction
was created. And the EBX input for the final MWAITX is still
in a virtual register. So EBX isn't read by this pseudo.
The file was modifiedllvm/lib/Target/X86/X86InstrCompiler.td
Commit e8beb6988bab71ee4917288f07674b4982736109 by Jonas Devlieghere
[lldb] [test/Register] Attempt to fix x86-fp-read.test on Darwin

Darwin seems to use stmmN instead of stN. Use a regex to accept both.

Also try to actually clear st(7).

Differential revision: https://reviews.llvm.org/D88795
The file was modifiedlldb/test/Shell/Register/x86-fp-read.test
The file was modifiedlldb/test/Shell/Register/Inputs/x86-fp-read.cpp
Commit a58b20e5a4fb64404cb62d2bb6a5e6dc40d22784 by Jonas Devlieghere
[llvm] Rename DwarfFile to DWARFFile to fix ODR violation (NFC)

Rename the DwarfFile class in DWARFLinker to DWARFFile. This is
consistent with the other DWARF classes and avoids a ODR violation with
the DwarfFile class in AsmPrinter.
The file was modifiedllvm/lib/DWARFLinker/DWARFLinker.cpp
The file was modifiedllvm/include/llvm/DWARFLinker/DWARFLinker.h
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.cpp
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.h
Commit cf4aa68388025a731236bc6dbe113ffdfe14c6c2 by kupokupokupopo
[RISCV][ASAN] mark asan as supported for RISCV64 and enable tests

[11/11] patch series to port ASAN for riscv64

These changes allow using ASAN on RISCV64 architecture.
The majority of existing tests are passing. With few exceptions (see below).
Tests we run on qemu and on "HiFive Unleashed" board.

Tests run:

```
Asan-riscv64-inline-Test  - pass
Asan-riscv64-inline-Noinst-Test  - pass
Asan-riscv64-calls-Noinst-Test  - pass
Asan-riscv64-calls-Test  - pass
```

Lit tests:

```
RISCV64LinuxConfig (282 supported, few failures)
RISCV64LinuxDynamicConfig (289 supported, few failures)
```

Lit failures:

```
TestCases/malloc_context_size.cpp - asan works, but backtrace misses some calls
TestCases/Linux/malloc_delete_mismatch.cpp - asan works, but backtrace misses some calls
TestCases/Linux/static_tls.cpp - "Can't guess glibc version" (under debugging)
TestCases/asan_and_llvm_coverage_test.cpp - missing libclang_rt.profile-riscv64.a
```

These failures are under debugging currently and shall be addressed in a
subsequent commits.

Depends On D87581

Reviewed By: eugenis, vitalybuka

Differential Revision: https://reviews.llvm.org/D87582
The file was modifiedcompiler-rt/lib/asan/tests/asan_test.cpp
The file was modifiedcompiler-rt/test/asan/CMakeLists.txt
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/vfork.cpp
The file was modifiedcompiler-rt/cmake/config-ix.cmake
The file was modifiedcompiler-rt/lib/asan/scripts/asan_symbolize.py
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/CMakeLists.txt
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/ptrace.cpp
Commit a3caf7f6102dc863425f9714b099af58397f0cd2 by markus.lavin
[DebugInfo] Improve dbg preservation in LSR.

Use SCEV to salvage additional @llvm.dbg.value that have turned into
referencing undef after transformation (and traditional
salvageDebugInfo). Before transformation compute SCEV for each
@llvm.dbg.value in the loop body and store it (along side its current
DIExpression). After transformation update those @llvm.dbg.value now
referencing undef by comparing its stored SCEV to the SCEV of the
current loop-header PHI-nodes. Allow match with offset by inserting
compensation code in the DIExpression.

Fixes : PR38815

Differential Revision: https://reviews.llvm.org/D87494
The file was modifiedllvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolution.h
The file was addedllvm/test/Transforms/LoopStrengthReduce/dbg-preserve-0.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Commit 3423d5c9da812b0076d1cf14e96ce453e35257b6 by hokein.wu
[AST][RecoveryExpr] Popagate the error-bit from a VarDecl's initializer to DeclRefExpr.

The error-bit was missing, if a DeclRefExpr (which refers to a VarDecl
with a contains-errors initializer).

It could cause different violations in clang -- the DeclRefExpr is value-dependent,
but not contains-errors, `ABC<DeclRefExpr>` could produce a non-error
and non-dependent type in non-template context, which will lead to
crashes in constexpr evaluation.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D86048
The file was modifiedclang/lib/AST/ComputeDependence.cpp
The file was modifiedclang/test/Sema/invalid-member.cpp
Commit 64b879ae2a8a4a4e541404c19d96d18c4aed810e by mikael.holmen
[TableGen][GlobalISel] add handling of nested *_SUBREG

When nesting INSERT_SUBREG and EXTRACT_SUBREG, GlobalISelEmitter would
fail to find the register class of the nested node. This patch fixes
that for registers with subregs.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D88487
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was addedllvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
Commit 0d5989bb24934802a9e6fcca63848a57a91efcc8 by jay.foad
[AMDGPU] Split R600 and GCN bfe patterns

This is in preparation for making the GCN patterns divergence-aware.
NFC.

Differential Revision: https://reviews.llvm.org/D88579
The file was modifiedllvm/lib/Target/AMDGPU/EvergreenInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
Commit 16778b19f2c2756a9e0dd04636fb2c269f684917 by jay.foad
[AMDGPU] Make bfe patterns divergence-aware

This tends to increase code size but more importantly it reduces vgpr
usage, and could avoid costly readfirstlanes if the result needs to be
in an sgpr.

Differential Revision: https://reviews.llvm.org/D88580
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/bfe-patterns.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit 6e2b267d1c85ce0de0e91eb446831607896a0f2b by benny.kra
Promote transpose from linalg to standard dialect

While affine maps are part of the builtin memref type, there is very
limited support for manipulating them in the standard dialect. Add
transpose to the set of ops to complement the existing view/subview ops.
This is a metadata transformation that encodes the transpose into the
strides of a memref.

I'm planning to use this when lowering operations on strided memrefs,
using the transpose to remove the stride without adding a dependency on
linalg dialect.

Differential Revision: https://reviews.llvm.org/D88651
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/docs/Dialects/Linalg.md
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/test/Dialect/Linalg/llvm.mlir
The file was modifiedmlir/test/Dialect/Linalg/standard.mlir
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
The file was modifiedmlir/test/Conversion/StandardToLLVM/standard-to-llvm.mlir
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
The file was modifiedmlir/test/Dialect/Standard/invalid.mlir
The file was modifiedmlir/lib/Conversion/LinalgToStandard/LinalgToStandard.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Commit 5b5e78a43124c0ced813f378195b36098f716c8f by jam
[VE] Support register and frame-index pair correctly

Support register and frame-index pair correctly as operands of
generic load/store instrucitons, e.g. LD1BZXrri, STLrri, and etc.
Add regression tests also.

Differential Revision: https://reviews.llvm.org/D88779
The file was modifiedllvm/lib/Target/VE/VEISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/VE/loadrri.ll
Commit d52211e384773ae06aabf476c78f16d2976660b0 by ntv
[mlir] Fix SubViewOp doc in .td
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit 6a089ce0e40abbe4e0f26f05540e3caa60d98a29 by sebastian.neubauer
[AMDGPU] Use tablegen for argument indices

Use tablegen generic tables to get the index of image intrinsic
arguments.
Before, the computation of which image intrinsic argument is at which
index was scattered in a few places, tablegen, the SDag instruction
selection and GlobalISel. This patch changes that, so only tablegen
contains code to compute indices and the ImageDimIntrinsicInfo table
provides these information.

Differential Revision: https://reviews.llvm.org/D86270
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MIMGInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsAMDGPU.td
Commit 71cf97e95b8c888367284d1d12925f79b38034eb by david.spickett
Reland "[lldb] Don't send invalid region addresses to lldb server"

This reverts commit c65627a1fe3be7521fc232d633bb6df577f55269.

The test immediately after the new invalid symbol test was
failing on Windows. This was because when we called
VirtualQueryEx to get the region info for 0x0,
even if it succeeded we would call GetLastError.

Which must have picked up the last error that was set while
trying to lookup "not_an_address". Which happened to be 2.
("The system cannot find the file specified.")

To fix this only call GetLastError when we know VirtualQueryEx
has failed. (when it returns 0, which we were also checking for anyway)

Also convert memory region to an early return style
to make the logic clearer.

Reviewed By: labath, stella.stamenova

Differential Revision: https://reviews.llvm.org/D88229
The file was modifiedlldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
The file was modifiedlldb/test/API/functionalities/memory-region/TestMemoryRegion.py
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
Commit 7f05fe1aeeb005b552c6a3093b61659e7b578b14 by hokein.wu
[AST][RecoveryExpr] Fix a crash on undeduced type.

We should not capture the type if the function return type is undeduced.

Reviewed By: adamcz

Differential Revision: https://reviews.llvm.org/D87350
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/test/SemaCXX/recovery-expr-type.cpp
The file was modifiedclang/test/AST/ast-dump-recovery.cpp
Commit 96c8a17c800b2370f6d43fe67559ca10d5e44196 by hokein.wu
[clangd] Remove unused using-decls in TypeHierarchyTests, NFC.
The file was modifiedclang-tools-extra/clangd/unittests/TypeHierarchyTests.cpp
Commit e70e7d1019ca8562b614a67c26995da42c0336ad by dmitry.preobrazhensky
[TableGen] Added a function for identification of unsupported opcodes.

This change implements generation of a function which may be used by a backend to check if a given instruction is supported for a specific subtarget.

Reviewers: sdesmalen

Differential Revision: https://reviews.llvm.org/D88214
The file was modifiedllvm/utils/TableGen/AsmMatcherEmitter.cpp
Commit 707c3d4d4210f5386a79ef7a7e771f36bc7ad9ef by carl.ritson
[AMDGPU][RegAlloc][SplitKit] Pre-commit test for D88821
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
Commit 007dd12d546814977519b33ca38b1cc8b31fee26 by gabor.marton
[ASTImporter][AST] Fix structural equivalency crash on dependent FieldDecl

Differential Revision: https://reviews.llvm.org/D88665
The file was modifiedclang/test/ASTMerge/struct/test.c
The file was modifiedclang/unittests/AST/StructuralEquivalenceTest.cpp
The file was modifiedclang/lib/AST/ASTStructuralEquivalence.cpp