SuccessChanges

Summary

  1. Fix unused variable warning when compiling with asserts disabled. (details)
  2. [flang] Fix build with BUILD_SHARED_LIBS=ON and FLANG_BUILD_NEW_DRIVER=ON (details)
  3. [LLD][ELF] Improve ICF for relocations to ineligible sections via "aliases" (details)
  4. [Statepoints] Remove MI limit on number of tied operands. (details)
  5. [SVE]Fix implicit TypeSize casts in EmitCheckValue (details)
  6. [AMDGPU] Minimize number of s_mov generated by copyPhysReg (details)
  7. [InstCombine] visitXor - refactor ((X^C1)>>C2)^C3 -> (X>>C2)^((C1>>C2)^C3) fold. NFCI. (details)
  8. AMDGPU: Fix verifier error on killed spill of partially undef register (details)
  9. Add "not" to an llvm-symbolizer test that expects to fail (details)
  10. [RISCV] [TableGen] Modify RISCVCompressInstEmitter.cpp to use getAllDerivedDefinitions(). (details)
  11. [TableGen] Add the !not and !xor operators. (details)
  12. [NFC] Fix license header from D87841 (details)
  13. [mlir][standard] Fix parsing of scalar subview and canonicalize (details)
  14. [openmp][libomptarget] Include header from LLVM source tree (details)
  15. [InstCombine] InstCombineAndOrXor - refactor cast<ConstantInt> usages to PatternMatch. NFCI. (details)
  16. [InstCombine] SimplifyDemandedUseBits - xor - refactor cast<ConstantInt> usage to PatternMatch. NFCI. (details)
  17. [InstCombine] Use m_SpecificInt instead of m_APInt + comparison. NFCI. (details)
  18. [RISCV] fix a mistake in RISCVInstrInfoV.td (details)
  19. [WebAssembly] v128.load{8,16,32,64}_lane instructions (details)
  20. [LLD] [COFF] Fix a condition that was missed in 7f0e6c31c255. NFC. (details)
  21. [LLD] [COFF] Implement a GNU/ELF like -wrap option (details)
  22. [lldb] [Process/FreeBSDRemote] Initial multithreading support (details)
  23. Revert "[WebAssembly] v128.load{8,16,32,64}_lane instructions" (details)
  24. [x86] add no 'unwind' to reduce test noise; NFC (details)
  25. [libc++] Allow building libc++ on platforms without a random device (details)
Commit ead2aa7098cfd693ed1842a88346ba67cfccd7df by akuegel
Fix unused variable warning when compiling with asserts disabled.

Differential Revision: https://reviews.llvm.org/D89454
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
Commit 50df5f24dc333e912f6eb8500ef84e648d43af93 by sguelton
[flang] Fix build with BUILD_SHARED_LIBS=ON and FLANG_BUILD_NEW_DRIVER=ON

As usual, it's difficult to handle all different configuration in the first row,
but this one has been extensively tested

Differential Revision: https://reviews.llvm.org/D89452
The file was modifiedflang/unittests/Runtime/CMakeLists.txt
The file was modifiedflang/unittests/Frontend/CMakeLists.txt
The file was modifiedflang/unittests/Evaluate/CMakeLists.txt
The file was modifiedflang/lib/Evaluate/CMakeLists.txt
Commit 88ce27c39c5e42d8a85ac1144d2ae0fae68e8853 by andrew.ng
[LLD][ELF] Improve ICF for relocations to ineligible sections via "aliases"

ICF was not able to merge equivalent sections because of relocations to
sections ineligible for ICF that use alternative symbols, e.g. symbol
aliases or section relative relocations.

Merging in this scenario has been enabled by giving the sections that
are ineligible for ICF a unique ID, i.e. an equivalence class of their
own. This approach also provides another benefit as it improves the
hashing that is used to perform the initial equivalance grouping for
ICF. This is because the ICF ineligible sections can now contribute a
unique value towards the hashes instead of the same value of zero. This
has been seen to reduce link time with ICF by ~68% for objects compiled
with -fprofile-instr-generate.

In order to facilitate this use of a unique ID, the existing
inconsistent approach to the setting of the InputSection eqClass in ICF
has been changed so that there is a clear distinction between the
eqClass values of ICF eligible sections and those of the ineligible
sections that have a unique ID. This inconsistency could have caused
incorrect equivalence class equality in the past, although it appears
that no issues were encountered in actual use.

Differential Revision: https://reviews.llvm.org/D88830
The file was addedlld/test/ELF/icf-ineligible.s
The file was modifiedlld/ELF/ICF.cpp
Commit 8f0ddd4a1a0d2e7b8004d8c3283bddf1a2e27a18 by dantrushin
[Statepoints] Remove MI limit on number of tied operands.

After D87915 statepoint can have more than 15 tied operands.
Remove this restriction from statepoint lowering code.
The file was addedllvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
Commit 145e44bb18853bc9beeac0e64fffd9e6895e71f9 by caroline.concatto
[SVE]Fix implicit TypeSize casts in EmitCheckValue

Using TypeSize::getFixedSize() instead of relying upon the implicit
TypeSize->uint64_cast as the type is always fixed width.

Differential Revision: https://reviews.llvm.org/D89313
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
Commit b70cb5020416413bf5fbfe8111891912153f3034 by carl.ritson
[AMDGPU] Minimize number of s_mov generated by copyPhysReg

Generate the minimal set of s_mov instructions required when
expanding a SGPR copy operation in copyPhysReg.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D89187
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit 09be7623e4e8e81f559b1c2dc74b0b3332261491 by llvm-dev
[InstCombine] visitXor - refactor ((X^C1)>>C2)^C3 -> (X>>C2)^((C1>>C2)^C3) fold. NFCI.

This is still ConstantInt-only (scalar) but is refactored to use PatternMatch to make adding vector support in the future relatively trivial.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 663f16684d1a5f129874b7be9e1f486682977bfa by Matthew.Arsenault
AMDGPU: Fix verifier error on killed spill of partially undef register

This does unfortunately end up with extra waitcnts getting inserted
that were avoided before. Ideally we would avoid the spills of these
undef components in the first place.
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
The file was addedllvm/test/CodeGen/AMDGPU/vgpr-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
The file was addedllvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
Commit 5e656ee48bccc73f1328db1770770acaec90a7c9 by jeremy.morse
Add "not" to an llvm-symbolizer test that expects to fail

In a7b209a6d40d77b, llvm-symbolizer was adjusted to return a failure status
code when it produced an error, to flag up DWARF parsing problems. The
test for missing PDB file is analogous, and returns a failure status now
too.

This should fix the llvm-clang-win-x-armv7l buildbot croaking:

  http://lab.llvm.org:8011/#/builders/60/builds/77
The file was modifiedllvm/test/tools/llvm-symbolizer/pdb/missing_pdb.test
Commit 81cec3943ab695c344900c1bcdeeda264ee41a30 by paul
[RISCV] [TableGen] Modify RISCVCompressInstEmitter.cpp to use getAllDerivedDefinitions().
The file was modifiedllvm/utils/TableGen/RISCVCompressInstEmitter.cpp
Commit 4767bb2c0c746eaf146927c8bcb0528bd36c7b8f by paul
[TableGen] Add the !not and !xor operators.
Update the TableGen Programmer's Reference.
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
The file was modifiedllvm/lib/TableGen/TGLexer.h
The file was modifiedllvm/test/TableGen/arithmetic.td
The file was modifiedllvm/lib/TableGen/TGParser.cpp
The file was modifiedllvm/include/llvm/TableGen/Record.h
The file was modifiedllvm/lib/TableGen/Record.cpp
The file was modifiedllvm/docs/TableGen/ProgRef.rst
The file was modifiedllvm/test/TableGen/math.td
The file was modifiedllvm/test/TableGen/if.td
Commit c66e091023b87b23459ed67158fd566ebc1f8a13 by jonchesterfield
[NFC] Fix license header from D87841
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPGridValues.h
Commit 307124535f326d75725ecf6d3f4e9e0321162e9a by herhut
[mlir][standard] Fix parsing of scalar subview and canonicalize

Parsing of a scalar subview did not create the required static_offsets attribute.
This also adds support for folding scalar subviews away.

Differential Revision: https://reviews.llvm.org/D89467
The file was modifiedmlir/test/Transforms/constant-fold.mlir
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/IR/core-ops.mlir
Commit 7d2ecef5ed11698ae106bfbf295c44d761c7f946 by jonchesterfield
[openmp][libomptarget] Include header from LLVM source tree

[openmp][libomptarget] Include header from LLVM source tree

The change is to the amdgpu plugin so is unlikely to break anything.

The point of contention is whether libomptarget can depend on LLVM.
A community discussion was cautiously not opposed yesterday.

This introduces a compile time dependency on the LLVM source tree, in this case
expressed as skipping the building of the plugin if LLVM_MAIN_INCLUDE_DIR is not
set. One the source files will #include llvm/Frontend/OpenMP/OMPGridValues.h,
instead of copy&pasting the numbers across.

For users that download the monorepo, the llvm tree is already on disk. This will
inconvenience users who download only the openmp source as a tar, as they would
now also have to download (at least a file or two) from the llvm source, if they want
to build the parts of the openmp project that (post this patch) depend on llvm.

There was interest expressed in going further - using llvm tools as part of
building libomp, or linking against llvm libraries. That seems less clear cut
an improvement and worthy of further discussion. This patch seeks only to change
policy to support openmp depending on the llvm source tree. Including in the
other direction, or using libraries / tools etc, are purposefully out of scope.

Reviewers are a best guess at interested parties, please feel free to add others

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D87841
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/CMakeLists.txt
Commit 2b45639ea0f3fcafbc647874e0902c5798903afa by llvm-dev
[InstCombine] InstCombineAndOrXor - refactor cast<ConstantInt> usages to PatternMatch. NFCI.

First step towards replacing these to add full vector support.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit b3330ae42c73b204f6809b808308ee90a75bc921 by llvm-dev
[InstCombine] SimplifyDemandedUseBits - xor - refactor cast<ConstantInt> usage to PatternMatch. NFCI.

First step towards replacing these to add full vector support.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Commit 23f161662645d145a6f4621150ab5a43762f6972 by llvm-dev
[InstCombine] Use m_SpecificInt instead of m_APInt + comparison. NFCI.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 2de693756fefbb8a093ffd511b6684ef132f4e11 by llvm
[RISCV] fix a mistake in RISCVInstrInfoV.td

A commit of VALUVVNoVm was wrong, fixed it.

Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D88142
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
Commit 7c6bfd90ab2ddaa60de62878c8512db0645e8452 by tlively
[WebAssembly] v128.load{8,16,32,64}_lane instructions

Prototype the newly proposed load_lane instructions, as specified in
https://github.com/WebAssembly/simd/pull/350. Since these instructions are not
available to origin trial users on Chrome stable, make them opt-in by only
selecting them from intrinsics rather than normal ISel patterns. Since we only
need rough prototypes to measure performance right now, this commit does not
implement all the load and store patterns that would be necessary to make full
use of the offset immediate. However, the full suite of offset tests is included
to make it easy to track improvements in the future.

Since these are the first instructions to have a memarg immediate as well as an
additional immediate, the disassembler needed some additional hacks to be able
to parse them correctly. Making that code more principled is left as future
work.

Differential Revision: https://reviews.llvm.org/D89366
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/test/MC/WebAssembly/simd-encodings.s
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was addedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedllvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
Commit 9803cf57d6fe5c7189255ad74b289c2a0d4a8a6a by martin
[LLD] [COFF] Fix a condition that was missed in 7f0e6c31c255. NFC.

This should fix cases when e.g. auto import is enabled without
mingw mode in total being enabled.

Differential Revision: https://reviews.llvm.org/D89006
The file was modifiedlld/COFF/SymbolTable.cpp
Commit a012c704b5e5b60f9d2a7304d27cbc84a3619571 by martin
[LLD] [COFF] Implement a GNU/ELF like -wrap option

Add a simple forwarding option in the MinGW frontend, and implement
the private -wrap option in the COFF linker.

The feature in lld-link isn't gated by the -lldmingw option, but
the option is left as a private, undocumented option primarily
used by the MinGW driver.

The implementation is significantly based on the support for --wrap
in the ELF linker, but many small nuance details are different
between the ELF and COFF linkers, ending up with more than a few
implementation differences.

This fixes https://bugs.llvm.org/show_bug.cgi?id=47384.

Differential Revision: https://reviews.llvm.org/D89004
The file was addedlld/test/COFF/wrap-real-missing.s
The file was addedlld/test/COFF/wrap-lto-2.ll
The file was modifiedlld/COFF/LTO.cpp
The file was addedlld/test/COFF/wrap.s
The file was modifiedlld/COFF/Symbols.h
The file was modifiedlld/MinGW/Options.td
The file was modifiedlld/COFF/MinGW.h
The file was modifiedlld/MinGW/Driver.cpp
The file was addedlld/test/COFF/wrap-lto-1.ll
The file was modifiedlld/test/MinGW/driver.test
The file was modifiedlld/COFF/Options.td
The file was modifiedlld/COFF/InputFiles.h
The file was addedlld/test/COFF/wrap-import.ll
The file was addedlld/test/COFF/wrap-with-archive.s
The file was modifiedlld/COFF/SymbolTable.cpp
The file was modifiedlld/COFF/Driver.cpp
The file was modifiedlld/COFF/MinGW.cpp
The file was addedlld/test/COFF/wrap-i386.s
Commit 87d38831d909bf937039a97aa63220929d498047 by mgorny
[lldb] [Process/FreeBSDRemote] Initial multithreading support

Implement initial support for watching thread creation and termination.
Update ptrace() calls to correctly indicate requested thread.
Watchpoints are not supported yet.

This patch fixes at least multithreaded register tests.

Differential Revision: https://reviews.llvm.org/D89413
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeProcessFreeBSD.h
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeProcessFreeBSD.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeThreadFreeBSD.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD.h
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD.cpp
Commit 7c8385a352ba21cb388046290d93b53dc273cd9f by tlively
Revert "[WebAssembly] v128.load{8,16,32,64}_lane instructions"

This reverts commit 7c6bfd90ab2ddaa60de62878c8512db0645e8452.
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
The file was removedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedllvm/test/MC/WebAssembly/simd-encodings.s
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedclang/test/CodeGen/builtins-wasm.c
Commit e9df9028a7ca67dc6198108e6ea621cb554aa3c7 by spatel
[x86] add no 'unwind' to reduce test noise; NFC

I suggested this in D89412, but the comment was missed.
The file was modifiedllvm/test/CodeGen/X86/ctpop-combine.ll
Commit e0d01294bc124211a8ffb55e69162eb34a242680 by Louis Dionne
[libc++] Allow building libc++ on platforms without a random device

Some platforms, like several embedded platforms, do not provide a source
of randomness through a random device. This commit makes it possible to
build and test libc++ for such platforms, i.e. without std::random_device.

Surprisingly, the only functionality that doesn't work on such platforms
is std::random_device itself -- everything else in <random> still works,
one just has to find alternative ways to seed the PRNGs.
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was addedlibcxx/test/libcxx/numerics/rand/rand.device/has-no-random-device.verify.cpp
The file was addedlibcxx/cmake/caches/Generic-no-random_device.cmake
The file was modifiedlibcxx/include/__config_site.in
The file was modifiedlibcxx/utils/ci/run-buildbot.sh
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.copy_file/copy_file_large.pass.cpp
The file was modifiedlibcxx/src/CMakeLists.txt
The file was modifiedlibcxx/test/std/numerics/rand/rand.device/entropy.pass.cpp
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxx/test/std/numerics/rand/rand.device/eval.pass.cpp
The file was modifiedlibcxx/include/random
The file was modifiedlibcxx/test/std/numerics/rand/rand.device/ctor.pass.cpp
The file was modifiedlibcxx/test/support/filesystem_test_helper.h
The file was modifiedlibcxx/utils/libcxx/test/features.py