FailedChanges

Summary

  1. [gn build] Port be39a6fe6fc (details)
  2. [RISCV][NFC] Add more tests for 32-bit constant materialization (details)
  3. [SCEV][NFC] Simplify internals of BackedgeTakenInfo (details)
  4. [mlir] Add MemRefReshapeOp definition to Standard. (details)
  5. [clang-tidy] Add links to check docs in comments (details)
  6. [x86 testing] NFC: Create exhaustive vector popcnt ULT/UGT tests (details)
  7. [DebugInstrRef] Substitute debug value numbers to handle optimizations (details)
  8. Test I added requires X86 to be built. (details)
  9. [AArch64] Add cost model tests for min/max intrinsics. (details)
  10. [lldb][NFC] Make GetShellSafeArgument return std::string and unittest it. (details)
  11. [mlir] Add MemRefReinterpretCastOp definition to Standard. (details)
  12. [llvm-mca] Add few ldm* instructions to cortex-a57 test case (details)
  13. [CodeGen] Split MVT::changeTypeToInteger() functionality from EVT::changeTypeToInteger(). (details)
  14. [Clang] [TableGen] Clean up !if(!eq(bool, 1) and related booleans (details)
  15. [lldb] Explicitly use the configuration architecture when building test executables (details)
  16. [mlir] Convert from Async dialect to LLVM coroutines (details)
  17. [TableGen] Continue improving the comments for the data structures. (details)
  18. [OpenMP] Emit calls to int64_t functions for amdgcn (details)
  19. Limit debug instr-referencing tests to X86 (details)
  20. ScheduleDAGInstrs: Skip debug instructions at end of scheduling region (details)
  21. AMDGPU: Implement getNoPreservedMask (details)
  22. AMDGPU: Fix not always reserving VGPRs used for SGPR spilling (details)
  23. [lldb] Fix TestTargetAPI.py on Apple simulators (details)
  24. [AArch64] Add min/max cost-model tests for v4i16. (details)
  25. [DebugInstrRef] Pass DBG_INSTR_REFs through register allocation (details)
  26. [X86] Return const& in IntelExprStateMachine::getIdentifierInfo(). NFCI. (details)
  27. [X86] X86AsmParser - make methods const where possible. NFCI. (details)
  28. [ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate (details)
  29. [AArch64] Add min/max cost-model tests for v2i32. (details)
  30. [AMDGPU] Fix expansion of i16 MULH (details)
Commit 1c3bbdb866ab9b660583f5bc8d161b7ee8771cd2 by llvmgnsyncbot
[gn build] Port be39a6fe6fc
The file was modifiedllvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Commit 89840380d56e7cf4511d03cb9f42b6bed322e0bc by luismarques
[RISCV][NFC] Add more tests for 32-bit constant materialization

The existing tests were mostly for 64-bit constants.

Differential Revision: https://reviews.llvm.org/D83210
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll
Commit cc2eb3b5e2582da2412f6d30955ddbd9b0f3a16a by mkazantsev
[SCEV][NFC] Simplify internals of BackedgeTakenInfo
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolution.h
Commit d2ed2f16b853a936c8d0c1c1fc406e7b8e54526c by pifon
[mlir] Add MemRefReshapeOp definition to Standard.

https://llvm.discourse.group/t/rfc-standard-memref-cast-ops/1454/15

Differential Revision: https://reviews.llvm.org/D89784
The file was modifiedmlir/test/Dialect/Standard/ops.mlir
The file was modifiedmlir/test/Dialect/Standard/invalid.mlir
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
Commit 37558fd29ee0af2302c051b8e70543cfc3e7ca91 by alexfh
[clang-tidy] Add links to check docs in comments
The file was modifiedclang-tools-extra/clang-tidy/google/AvoidCStyleCastsCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/AvoidUnderscoreInGoogletestNameCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/IntegerTypesCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/OverloadedUnaryAndCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/GlobalNamesInHeadersCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/DefaultArgumentsCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/UsingNamespaceDirectiveCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/ExplicitMakePairCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/ExplicitConstructorCheck.h
The file was modifiedclang-tools-extra/clang-tidy/google/TodoCommentCheck.h
Commit 8556f38b0d6268103a6da08dc01c360f8e20fc32 by dave
[x86 testing] NFC: Create exhaustive vector popcnt ULT/UGT tests

There are bunch of optimization opportunities right now in the vector
popcnt code gen when doing simple less-than/greater-than comparisons, so
let's examine them all to ensure that things don't regress as different
scenarios are fixed. We can always delete some later once some fixes are
made.

Please note: the new files were auto-generated. If people want, I can
commit the short C code that printed out the various combinations.
The file was addedllvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
The file was addedllvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
The file was modifiedllvm/test/CodeGen/X86/vector-popcnt-256.ll
The file was addedllvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
The file was modifiedllvm/test/CodeGen/X86/vector-popcnt-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-popcnt-128.ll
Commit d73275993bbc19b38b7818e96953f84decf0653b by jeremy.morse
[DebugInstrRef] Substitute debug value numbers to handle optimizations

This patch touches two optimizations, TwoAddressInstruction and X86's
FixupLEAs pass, both of which optimize by re-creating instructions. For
LEAs, various bits of arithmetic are better represented as LEAs on X86,
while TwoAddressInstruction sometimes converts instrs into three address
instructions if it's profitable.

For debug instruction referencing, both of these require substitutions to
be created -- the old instruction number must be pointed to the new
instruction number, as illustrated in the added test. If this isn't done,
any variable locations based on the optimized instruction are
conservatively dropped.

Differential Revision: https://reviews.llvm.org/D85756
The file was modifiedllvm/lib/Target/X86/X86FixupLEAs.cpp
The file was addedllvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
The file was modifiedllvm/lib/CodeGen/TwoAddressInstructionPass.cpp
Commit cb668d2e76e73ab45913d9dd3d0c44d48a21d36a by jeremy.morse
Test I added requires X86 to be built.

This the second time I've stepped on this landmine, I'll look at setting
a lit local config. All the tests in this dir are going to be X86 for now.
The file was modifiedllvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
Commit fbb6375db0be912451646f14a35231d18cd91adf by flo
[AArch64] Add cost model tests for min/max intrinsics.
The file was addedllvm/test/Analysis/CostModel/AArch64/min-max.ll
Commit bb1d702e25f5f23e8d5a755295f2921caaea2abb by Raphael Isemann
[lldb][NFC] Make GetShellSafeArgument return std::string and unittest it.
The file was modifiedlldb/include/lldb/Utility/Args.h
The file was modifiedlldb/source/Utility/Args.cpp
The file was modifiedlldb/unittests/Utility/ArgsTest.cpp
The file was modifiedlldb/source/Host/common/ProcessLaunchInfo.cpp
Commit 461605c418e9059aa50de65c60bbd49e8f270b4a by pifon
[mlir] Add MemRefReinterpretCastOp definition to Standard.

Reuse most code for printing/parsing/verification from SubViewOp.

https://llvm.discourse.group/t/rfc-standard-memref-cast-ops/1454/15

Differential Revision: https://https://reviews.llvm.org/D89720
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/Dialect/Standard/invalid.mlir
The file was modifiedmlir/test/Dialect/Standard/ops.mlir
Commit 088f3c83cc8fad7765a4dfd386519ffa6799be6c by eleviant
[llvm-mca] Add few ldm* instructions to cortex-a57 test case
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
Commit 794dc7ad26c21064a282046277bdb53c8d9690d5 by llvm-dev
[CodeGen] Split MVT::changeTypeToInteger() functionality from EVT::changeTypeToInteger().

Add the MVT equivalent handling for EVT changeTypeToInteger/changeVectorElementType/changeVectorElementTypeToInteger.

All the SimpleVT code already exists inside the EVT equivalents, but by splitting this out we can use these directly inside MVT types without converting to/from EVT.
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit e4b4543ff0c83b6f1d80064e2dcd22b2bb0bfab6 by paul
[Clang] [TableGen] Clean up !if(!eq(bool, 1) and related booleans

Differential Revision: https://reviews.llvm.org/D89893
The file was modifiedclang/include/clang/Basic/arm_mve_defs.td
The file was modifiedclang/include/clang/Basic/arm_mve.td
Commit 41185226f6d80663b4a1064c6f47581ee567d78d by Raphael Isemann
[lldb] Explicitly use the configuration architecture when building test executables

The Darwin builder currently assumes in `getArchCFlags` that the passed `arch`
value is an actual string it can string.join with vendor/os/version/env strings:

```
   triple = '-'.join([arch, vendor, os, version, env])
```

However this is not true for most tests as we just pass down the `arch=None`
default value from `TestBase.build`. This causes that if we actually end up in
this function we just error out when concatenating `None` with the other actual
strings of vendor/os/version/env. What we should do instead is check that if
there is no test-specific architecture that we fall back to the configuration's
architecture value.

It seems we already worked around this in `builder.getArchSpec` by explicitly
falling back to the architecture specified in the configuration.

This patch just moves this fallback logic to the top `build` function so that it
affects all functions called from `TestBase.build`.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D89056
The file was modifiedlldb/packages/Python/lldbsuite/test/builders/builder.py
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbtest.py
Commit f8fcff5a9d7ee948add3f28382d4ced5710edaaf by ezhulenev
[mlir] Convert from Async dialect to LLVM coroutines

Lower from Async dialect to LLVM by converting async regions attached to `async.execute` operations into LLVM coroutines (https://llvm.org/docs/Coroutines.html):
1. Outline all async regions to functions
2. Add LLVM coro intrinsics to mark coroutine begin/end
3. Use MLIR conversion framework to convert all remaining async types and ops to LLVM + Async runtime function calls

All `async.await` operations inside async regions converted to coroutine suspension points. Await operation outside of a coroutine converted to the blocking wait operations.

Implement simple runtime to support concurrent execution of coroutines.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D89292
The file was modifiedmlir/test/CMakeLists.txt
The file was addedmlir/include/mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h
The file was addedmlir/lib/ExecutionEngine/AsyncRuntime.cpp
The file was modifiedmlir/include/mlir/Dialect/Async/IR/AsyncOps.td
The file was modifiedmlir/lib/ExecutionEngine/CMakeLists.txt
The file was modifiedmlir/include/mlir/Conversion/Passes.h
The file was addedmlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt
The file was addedmlir/test/Conversion/AsyncToLLVM/convert-to-llvm.mlir
The file was addedmlir/test/mlir-cpu-runner/async.mlir
The file was addedmlir/include/mlir/ExecutionEngine/AsyncRuntime.h
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was addedmlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
The file was modifiedmlir/lib/Conversion/CMakeLists.txt
The file was modifiedmlir/lib/ExecutionEngine/OptUtils.cpp
Commit b2faf75568717397a7fced8fe93bbc013df77aaf by paul
[TableGen] Continue improving the comments for the data structures.

Differential Revision: https://reviews.llvm.org/D89901
The file was modifiedllvm/docs/TableGen/BackGuide.rst
The file was modifiedllvm/include/llvm/TableGen/Record.h
Commit 09bc755deaa69b1377a8c050131f67cd276a51f3 by jonchesterfield
[OpenMP] Emit calls to int64_t functions for amdgcn

[OpenMP] Emit calls to int64_t functions for amdgcn

Two functions, syncwarp and active_thread_mask, return lanemask_t. Currently
this is assumed to be int32, which is true for nvptx. Patch makes the type
target architecture dependent.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D89746
The file was modifiedllvm/test/Transforms/OpenMP/add_attributes.ll
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPKinds.def
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
The file was addedllvm/test/Transforms/OpenMP/add_attributes_amdgcn.ll
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Commit e3c6b0f1514c8e3fceb5f5451e672c9394aa9460 by jeremy.morse
Limit debug instr-referencing tests to X86

The instruction referencing work currently only works on X86, and all the
tests for it will be X86 based for the time being. Configure the whole
directory to be X86-only, seeing how I keep on landing tests that don't
have the correct REQUIRES lines.
The file was addedllvm/test/DebugInfo/MIR/InstrRef/lit.local.cfg
Commit 188df1742042610a4c9af1fff9943d3d2a2740c6 by Matthew.Arsenault
ScheduleDAGInstrs: Skip debug instructions at end of scheduling region

If the end instruction of the scheduling region was a DBG_VALUE, the
uses of the debug instruction were tracked as if they were real
uses. This would then hit the deadDefHasNoUse assertion in
addVRegDefDeps if the only use was the debug instruction.
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was addedllvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
Commit d3bcfe2a3602e14606417d8bb9d6bbaf636d9a02 by Matthew.Arsenault
AMDGPU: Implement getNoPreservedMask

We don't support funclets for exception handling and I hit this when
manually reducing MIR.
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
The file was addedllvm/test/CodeGen/AMDGPU/return-with-successors.mir
Commit d5c05616679894b3eb99194f1a3ffeef07c5cb19 by Matthew.Arsenault
AMDGPU: Fix not always reserving VGPRs used for SGPR spilling

The VGPRs used for SGPR spills need to be reserved, even if we aren't
speculatively reserving one.

This was broken by 117e5609e98b43f925c678b72f816ad3a1c3eee7.
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
Commit 30d5590d171c40e05b65585d1b531d8489e783e2 by Raphael Isemann
[lldb] Fix TestTargetAPI.py on Apple simulators

This test checks that the output of `SBTarget.GetDescription()` contains the
substrings `'a.out', 'Target', 'Module', 'Breakpoint'` in that order. This test
is currently failing on Apple simulators as apparently 'Module' can't be found
in the output after 'Target".

The reason for that is that the actual output of `SBTarget.GetDescription()` looks like this:
```
Target
  Module /build/path/lldb-test-build.noindex/python_api/target/TestTargetAPI.test_get_description_dwarf/a.out
0x7ff2b6d3f990:     ObjectFileMachO64, file = /build/path/lldb-test-build.noindex/python_api/target/TestTargetAPI.test_get_description
[...]
0x7ff307150000:   BreakpointList with 0 Breakpoints:
<LLDB module output repeats for each loaded module>
```

Clearly the string order should be `'Target', 'Module', 'a.out', 'Breakpoint'`.
However, LLDB is also a bunch of system shared libraries (libxpc.dylib,
libobjc.A.dylib, etc.) when *not* running against a simulator, we end up
unintentionally finding the `'Target', 'Module', 'Breakpoint'` substrings in the
trailing descriptions of the system modules. When running against a simulator we
however don't load shared system libraries.

This patch just moves the substrings in the correct order to make this test pass
without having any shared library modules in the description output.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D89698
The file was modifiedlldb/test/API/python_api/target/TestTargetAPI.py
Commit d6efc87518b554254d2f7203ba1e8c0be3adb88d by flo
[AArch64] Add min/max cost-model tests for v4i16.
The file was modifiedllvm/test/Analysis/CostModel/AArch64/min-max.ll
Commit 68ac02c0dd2b8fda52ac132a86f72f2ad6b139a5 by jeremy.morse
[DebugInstrRef] Pass DBG_INSTR_REFs through register allocation

Both FastRegAlloc and LiveDebugVariables/greedy need to cope with
DBG_INSTR_REFs. None of them actually need to take any action, other than
passing DBG_INSTR_REFs through: variable location information doesn't refer
to any registers at this stage.

LiveDebugVariables stashes the instruction information in a tuple, then
re-creates it later. This is only necessary as the register allocator
doesn't expect to see any debug instructions while it's working. No
equivalence classes or interval splitting is required at all!

No changes are needed for the fast register allocator, as it just ignores
debug instructions. The test added checks that both of them preserve
DBG_INSTR_REFs.

This also expands ScheduleDAGInstrs.cpp to treat DBG_INSTR_REFs the same as
DBG_VALUEs when rescheduling instructions around. The current movement of
DBG_VALUEs around is less than ideal, but it's not a regression to make
DBG_INSTR_REFs subject to the same movement.

Differential Revision: https://reviews.llvm.org/D85757
The file was modifiedllvm/lib/CodeGen/LiveDebugVariables.cpp
The file was addedllvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
Commit 091b18ba81fc1c9774f36df0d903d75aa72b64fb by llvm-dev
[X86] Return const& in IntelExprStateMachine::getIdentifierInfo(). NFCI.

Avoid unnecessary copy in X86AsmParser::ParseIntelOperand
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Commit 26929780506c3492dddd980da728a92f050fe069 by llvm-dev
[X86] X86AsmParser - make methods const where possible. NFCI.

Reported by cppcheck
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Commit ed6a91f4567ead72ffb34975863575348ecf0674 by eleviant
[ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D89939
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
Commit c1705e0ba481b3bf6a7f256ba8948d21ab78907e by flo
[AArch64] Add min/max cost-model tests for v2i32.
The file was modifiedllvm/test/Analysis/CostModel/AArch64/min-max.ll
Commit 7ae0033ca88126a14be65d09a11a6f9e0b72262e by Piotr Sobczak
[AMDGPU] Fix expansion of i16 MULH

This commit marks i16 MULH as expand in AMDGPU backend,
which is necessary after the refactoring in D80485.

Differential Revision: https://reviews.llvm.org/D89965
The file was modifiedllvm/test/CodeGen/AMDGPU/srem.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp