FailedChanges

Summary

  1. [CGSCC] Detect devirtualization in more cases (details)
  2. DebugInfo: Hash DIE referevences (DW_OP_convert) when computing Split DWARF signatures (details)
  3. [IR] Merge metadata manipulation code into Value (details)
  4. [lldb] Fix missing initialization in UtilityFunction ctor (NFC) (details)
  5. [runtimes] Do not set XXX_STANDALONE_BUILD for libc++/abi/unwind (details)
  6. [lldb] Fix bug instroduced by a00acbab45b0 (details)
  7. [SCEV][NFC] Cache symbolic max exit count (details)
  8. [JITLink][ELF] Add support for ELF::R_X86_64_REX_GOTPCRELX relocation. (details)
  9. Revert "[JITLink][ELF] Add support for ELF::R_X86_64_REX_GOTPCRELX relocation." (details)
  10. [llvm-objcopy][NFC] Extract arg parsing logic into a helper function (details)
  11. [DebugInfo] Clear subreg in setDebugValueUndef() (details)
  12. [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate (details)
  13. [llvm-mca] Add test for cortex-a57 NEON instructions (details)
  14. [SVE]Clarify TypeSize comparisons in llvm/lib/Transforms (details)
  15. [AMDGPU] Add simplification/combines for llvm.amdgcn.fmul.legacy (details)
  16. [lld][ELF][test] Add additional test coverage for LTO (details)
  17. [mem2reg] Remove dbg.values describing contents of dead allocas (details)
  18. [mlir] Fix exiting OpPatternRewriteDriver::simplifyLocally after first iteration that didn't change the op. (details)
  19. [MLIR] Added PromoteBuffersToStackPass to convert heap- to stack-based allocations. (details)
  20. [DebugInstrRef] NFC: Separate collection of machine/variable values (details)
  21. [lldb] Split out NetBSD/x86 watchpoint impl for unification (details)
  22. [AArch64] Implement getIntrinsicInstrCost, handle min/max intrinsics. (details)
  23. [ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC (details)
  24. [X86] lowerShuffleWithPERMV - use MVT::changeTypeToInteger helper. NFCI. (details)
  25. [InstCombine] Rename InstCombinerImpl::matchBSwap to matchBSwapOrBitReverse. NFCI. (details)
  26. [InstCombine] matchBSwapOrBitReverse - expose bswap/bitreverse matching flags. (details)
  27. [mlir] Expose affine expression to C API (details)
Commit 3024fe5b55ed72633915f613bd5e2826583c396f by aeubanks
[CGSCC] Detect devirtualization in more cases

The devirtualization wrapper misses cases where if it wraps a pass
manager, an individual pass may devirtualize an indirect call created by
a previous pass. For example, inlining may create a new indirect call
which is devirtualized by instcombine. Currently the devirtualization
wrapper will not see that because it only checks cgscc edges at the very
beginning and end of the pass (manager) it wraps.

This fixes some tests testing this exact behavior in the legacy PM.

This piggybacks off of updateCGAndAnalysisManagerForPass()'s detection
of promoted ref to call edges.

This supercedes one of the previous mechanisms to detect
devirtualization by keeping track of potentially promoted call
instructions via WeakTrackingVHs.

There is one more existing way of detecting devirtualization, by
checking if the number of indirect calls has decreased and the number of
direct calls has increased in a function. It handles cases where calls
to functions without definitions are promoted, and some tests rely on
that. LazyCallGraph doesn't track edges to functions without
definitions so this part can't be removed in this change.

check-llvm and check-clang with -abort-on-max-devirt-iterations-reached
on by default doesn't show any failures outside of tests specifically
testing it so it doesn't needlessly rerun passes more than necessary.
(The NPM -O2/3 pipeline run the inliner/function simplification pipeline
under a devirtualization repeater pass up to 4 times by default).

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D89587
The file was modifiedllvm/test/Transforms/Inline/devirtualize-3.ll
The file was modifiedllvm/test/Transforms/Inline/devirtualize.ll
The file was addedllvm/test/Transforms/Inline/devirtualize-5.ll
The file was modifiedllvm/include/llvm/Analysis/CGSCCPassManager.h
The file was modifiedllvm/lib/Analysis/CGSCCPassManager.cpp
Commit 4437df8eedfdaa11b445c34fc3b19a1b14cb3d93 by dblaikie
DebugInfo: Hash DIE referevences (DW_OP_convert) when computing Split DWARF signatures
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DIEHash.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DIEHash.cpp
The file was modifiedllvm/include/llvm/CodeGen/DIE.h
The file was modifiedllvm/test/DebugInfo/X86/convert-debugloc.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Commit 7975b8c38da2f46f8d88c14d24259af28805dbf3 by sepavloff
[IR] Merge metadata manipulation code into Value

Now there are two main classes in Value hierarchy, which support metadata,
these are Instruction and GlobalObject. They implement different APIs for
metadata manipulation, which however overlap. This change moves metadata
manipulation code into Value, so descendant classes can use this code for
their operations on metadata.

No functional changes intended.

Differential Revision: https://reviews.llvm.org/D67626
The file was modifiedllvm/include/llvm/IR/GlobalObject.h
The file was modifiedllvm/lib/IR/LLVMContextImpl.h
The file was modifiedllvm/include/llvm/IR/Value.h
The file was modifiedllvm/lib/IR/LLVMContextImpl.cpp
The file was modifiedllvm/lib/IR/Metadata.cpp
The file was modifiedllvm/include/llvm/IR/Instruction.h
The file was modifiedllvm/lib/IR/Value.cpp
The file was modifiedllvm/lib/IR/Core.cpp
The file was modifiedllvm/lib/IR/Instruction.cpp
Commit a00acbab45b0c407da05bf5c8152018e1857a1f0 by Jonas Devlieghere
[lldb] Fix missing initialization in UtilityFunction ctor (NFC)

The UtilityFunction ctor was dropping the text argument. Probably for
that reason ClangUtilityFunction was setting the parent's member
directly instead of deferring to the parent ctor. Also change the
signatures to take strings which are std::moved in place.
The file was modifiedlldb/source/Expression/UtilityFunction.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.h
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp
The file was modifiedlldb/include/lldb/Expression/UtilityFunction.h
Commit 2b9b7b5775a1d8fcd7aa5abaa8fc0bc303434f1a by Louis Dionne
[runtimes] Do not set XXX_STANDALONE_BUILD for libc++/abi/unwind

The runtimes build was lying to the various runtimes builds by setting
XXX_STANDALONE_BUILD=ON when they are really not being built standalone.
Only COMPILER_RT_STANDALONE_BUILD appears to be necessary, but setting it
for the other runtimes actually breaks everything.

Differential Revision: https://reviews.llvm.org/D90005
The file was modifiedllvm/runtimes/CMakeLists.txt
Commit 3590a8319a5fb491cba2349509910c2479f49a00 by Jonas Devlieghere
[lldb] Fix bug instroduced by a00acbab45b0

g_expression_prefix, as the name implies, must be perfixed, not
suffixed.
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp
Commit 6e574abf617c504f78f45534bcda65e95787899d by mkazantsev
[SCEV][NFC] Cache symbolic max exit count

We want to have a caching version of symbolic BE exit count
rather than recompute it every time we need it.

Differential Revision: https://reviews.llvm.org/D89954
Reviewed By: nikic, efriedma
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolution.h
Commit e2fceec2fd15b7b74617816ddd87f456c42bbc45 by Lang Hames
[JITLink][ELF] Add support for ELF::R_X86_64_REX_GOTPCRELX relocation.

No support for relaxation yet -- this will always use the GOT entry.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
The file was modifiedllvm/test/ExecutionEngine/JITLink/X86/ELF_x86-64_relocations.s
Commit 0f910387e610d6c3e0008da5f5305d42c546cb8c by Lang Hames
Revert "[JITLink][ELF] Add support for ELF::R_X86_64_REX_GOTPCRELX relocation."

This reverts commit e2fceec2fd15b7b74617816ddd87f456c42bbc45.

This commit broke one of the bots. Reverting while I investigate.
The file was modifiedllvm/test/ExecutionEngine/JITLink/X86/ELF_x86-64_relocations.s
The file was modifiedllvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
Commit 310a8e1d1284096fd42499c48a19899ff8b150ee by alexshap
[llvm-objcopy][NFC] Extract arg parsing logic into a helper function

This diff refactors the code which determines the tool type based on
how llvm-objcopy is invoked (objcopy vs strip vs bitcode-strip vs install-name-tool).
NFC.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D89713
The file was modifiedllvm/tools/llvm-objcopy/llvm-objcopy.cpp
Commit 13edfcc97d29574d1d38ded4fa9c2af6e6519472 by david.stenberg
[DebugInfo] Clear subreg in setDebugValueUndef()

When switching the register debug operands to $noreg in
setupDebugValueUndef() also clear the sub-register indices for virtual
registers. This is done when marking DBG_VALUEs undef in other cases,
e.g. in LiveDebugVariables. I have not found any cases where leaving the
sub-register index causes any issues, and the indices would eventually
get dropped when LiveDebugVariables reinserted the undef DBG_VALUEs
after register scheduling, but if nothing else it looked a bit weird in
printouts to have sub-register indices on $noreg, and I don't think the
sub-register index holds any meaningful information at that point.

I have not been able to find any source-level reproducer for this with
an upstream target, so I have just added an instrumented machine-sink
test.

Reviewed By: djtodoro, jmorse

Differential Revision: https://reviews.llvm.org/D89941
The file was modifiedllvm/include/llvm/CodeGen/MachineInstr.h
The file was addedllvm/test/DebugInfo/MIR/X86/machinesink-subreg.mir
Commit 7a78073be7649d9d2a83df50db9ec41b9a26d4f4 by eleviant
[ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate

Differential revision: https://reviews.llvm.org/D89957
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
Commit ffc0f577dac7097facc6b3e254c0ff73a723738f by eleviant
[llvm-mca] Add test for cortex-a57 NEON instructions
The file was addedllvm/test/tools/llvm-mca/ARM/cortex-a57-neon-instructions.s
Commit 241563647555e48cfa96146dd19d00e5aadbc518 by caroline.concatto
[SVE]Clarify TypeSize comparisons in llvm/lib/Transforms

Use isKnownXY comparators when one of the operands can be with
scalable vectors or getFixedSize() for all the other cases.

This patch also does bug fixes for getPrimitiveSizeInBits by using
getFixedSize() near the places with the TypeSize comparison.

Differential Revision: https://reviews.llvm.org/D89703
The file was modifiedllvm/lib/Transforms/Scalar/LoopPredication.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp
The file was modifiedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
The file was modifiedllvm/lib/Transforms/Scalar/NaryReassociate.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Commit 86a480e9ce786bc55c1c9632d9a42c08846e4695 by jay.foad
[AMDGPU] Add simplification/combines for llvm.amdgcn.fmul.legacy

Differential Revision: https://reviews.llvm.org/D88955
The file was addedllvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll
The file was modifiedllvm/include/llvm/IR/PatternMatch.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
Commit 342040bf00743cd401f01667dcf54315c64f09e9 by james.henderson
[lld][ELF][test] Add additional test coverage for LTO

These are all inspired by existing test coverage we have in an internal
testsuite.

Reviewed by: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D89775
The file was modifiedlld/test/ELF/lto/common.ll
The file was addedlld/test/ELF/lto/bitcode-wrapper.ll
The file was removedlld/test/ELF/lto/Inputs/resolution.s
The file was addedlld/test/ELF/lto/non-ascii-filenames.ll
The file was removedlld/test/ELF/lto/Inputs/common.s
The file was modifiedlld/test/ELF/lto/resolution.ll
Commit fea067bdfde430a74de077f1f61ef1f8a43d9c30 by orlando.hyams
[mem2reg] Remove dbg.values describing contents of dead allocas

This patch copies @vsk's fix to instcombine from D85555 over to mem2reg. The
motivation and rationale are exactly the same: When mem2reg removes an alloca,
it erases the dbg.{addr,declare} instructions which refer to the alloca. It
would be better to instead remove all debug intrinsics which describe the
contents of the dead alloca, namely all dbg.value(<dead alloca>, ...,
DW_OP_deref)'s.

As far as I can tell, prior to D80264 these `dbg.value+deref`s would have been
silently dropped instead of being made `undef`, so we're just returning to
previous behaviour with these patches.

Testing:
`llvm-lit llvm/test` and `ninja check-clang` gave no unexpected failures. Added
3 tests, each of which covers a dbg.value deletion path in mem2reg:
  mem2reg-promote-alloca-1.ll
  mem2reg-promote-alloca-2.ll
  mem2reg-promote-alloca-3.ll
The first is based on the dexter test inlining.c from D89543. This patch also
improves the debugging experience for loop.c from D89543, which suffers
similarly after arg promotion instead of inlining.
The file was addedllvm/test/DebugInfo/Generic/mem2reg-promote-alloca-1.ll
The file was modifiedllvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
The file was addedllvm/test/DebugInfo/Generic/mem2reg-promote-alloca-2.ll
The file was addedllvm/test/DebugInfo/Generic/mem2reg-promote-alloca-3.ll
Commit ff87c4d3e773ae89ae62af20941339f0f252dafd by csigg
[mlir] Fix exiting OpPatternRewriteDriver::simplifyLocally after first iteration that didn't change the op.

Before this change, we would run `maxIterations` if the first iteration changed the op.
After this change, we exit the loop as soon as an iteration hasn't changed the op.
Assuming that we have reached a fixed point when an iteration doesn't change the op, this doesn't affect correctness.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D89981
The file was modifiedmlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
Commit 0d1d363c51c93614783755426cb58c819c164fab by julian.gross
[MLIR] Added PromoteBuffersToStackPass to convert heap- to stack-based allocations.

Added optimization pass to convert heap-based allocs to stack-based allocas in
buffer placement. Added the corresponding test file.

Differential Revision: https://reviews.llvm.org/D89688
The file was addedmlir/test/Transforms/promote-buffers-to-stack.mlir
The file was modifiedmlir/include/mlir/Transforms/Passes.h
The file was modifiedmlir/include/mlir/Transforms/Passes.td
The file was modifiedmlir/lib/Transforms/BufferOptimizations.cpp
Commit ab93e710652f764bf2ab51710980e7828ebe4a8b by jeremy.morse
[DebugInstrRef] NFC: Separate collection of machine/variable values

This patch adjusts _when_ something happens in LiveDebugValues /
InstrRefBasedLDV, to make it more amenable to dealing with DBG_INSTR_REF
instructions. There's no functional change.

In the current InstrRefBasedLDV implementation, we collect the machine
value-number transfer function for blocks at the same time as the
variable-value transfer function. After solving machine value numbers, the
variable-value transfer function is updated so that DBG_VALUEs of live-in
registers have the correct value. The same would need to be done for
DBG_INSTR_REFs, to connect instruction-references with machine value
numbers.

Rather than writing more code for that, this patch separates the two: we
collect the (machine-value-number) transfer function and solve for
machine value numbers, then step through the MachineInstrs again collecting
the variable value transfer function. This simplifies things for the new
few patches.

Differential Revision: https://reviews.llvm.org/D85760
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
Commit dae7b10034a515a34aca593fee24d5b73dc0785f by mgorny
[lldb] Split out NetBSD/x86 watchpoint impl for unification

Split the current NetBSD watchpoint implementation for x86 into Utility,
and revamp it to improve readability.  This code is meant to be used
as a common class for all x86 watchpoint implementation, particularly
these on FreeBSD and Linux.

The code uses global watchpoint enable bits, as required by the NetBSD
kernel.  If it ever becomes necessary for any platform to use local
enable bits instead, this can be trivially abstracted out.

The code also postpones clearing DR6 until a new different watchpoint
is being set in place of the old one.  This is necessary since LLDB
repeatedly reenables watchpoints on all threads, by clearing
and restoring them.  When DR6 is cleared as a part of that, then pending
events on other threads can no longer be associated with watchpoints
correctly.

Differential Revision: https://reviews.llvm.org/D89874
The file was modifiedlldb/source/Host/common/NativeRegisterContext.cpp
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD.cpp
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
The file was addedlldb/source/Plugins/Process/Utility/NativeRegisterContextWatchpoint_x86.cpp
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.h
The file was addedlldb/source/Plugins/Process/Utility/NativeRegisterContextWatchpoint_x86.h
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD.h
The file was modifiedlldb/source/Plugins/Process/Utility/CMakeLists.txt
The file was modifiedlldb/include/lldb/Host/common/NativeRegisterContext.h
Commit 0fcc6f7a7607b3bf80e67b9f9a07b608724ee031 by flo
[AArch64] Implement getIntrinsicInstrCost, handle min/max intrinsics.

This patch adds a specialized implementation of getIntrinsicInstrCost
and add initial cost-modeling for min/max vector intrinsics.

AArch64 NEON support umin/smin/umax/smax for vectors
<8 x i8>, <16 x i8>, <4 x i16>, <8 x i16>, <2 x i32> and <4 x i32>.
Notably, it does not support vectors with i64 elements.

This change by itself should have very little impact on codegen, but in
follow-up patches I plan to teach the vectorizers to consider using
those intrinsics on platforms where it is profitable, e.g. because there
is no general 'select'-like instruction.

The current cost returned should be better for throughput, latency and size.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D89953
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/AArch64/min-max.ll
Commit cb86522c9450d909863d36cd73dae2586f82fcdb by eleviant
[ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC

Differential revision: https://reviews.llvm.org/D90017
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
Commit 936ef89ebe8646c483b993d8d8e50ee9509e005d by llvm-dev
[X86] lowerShuffleWithPERMV - use MVT::changeTypeToInteger helper. NFCI.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 19a13bf538b30fa67fc4a381fb25d150cc5a9989 by llvm-dev
[InstCombine] Rename InstCombinerImpl::matchBSwap to matchBSwapOrBitReverse. NFCI.

This matches bswap and bitreverse intrinsics, so we should make that clear in the function name.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
Commit 1cab3bf0046117759cc7891eec66affbbeb5965c by llvm-dev
[InstCombine] matchBSwapOrBitReverse - expose bswap/bitreverse matching flags.

matchBSwapOrBitReverse was hardcoded to just match bswaps - we're going to need to expose the ability to match bitreverse as well, so make this part of the function call.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 448f25c86b79aebae90718938b6a2cb4c782e57d by zhanghb97
[mlir] Expose affine expression to C API

This patch provides C API for MLIR affine expression.
- Implement C API for methods of AffineExpr class.
- Implement C API for methods of derived classes (AffineBinaryOpExpr, AffineDimExpr, AffineSymbolExpr, and AffineConstantExpr).

Differential Revision: https://reviews.llvm.org/D89856
The file was addedmlir/include/mlir-c/AffineExpr.h
The file was addedmlir/include/mlir/CAPI/AffineExpr.h
The file was addedmlir/lib/CAPI/IR/AffineExpr.cpp
The file was modifiedmlir/lib/CAPI/IR/CMakeLists.txt
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/include/mlir/IR/AffineExpr.h