AbortedChanges

Summary

  1. [NFC] Factor out common code into lambda for further improvement (details)
  2. [NFC] Remove unused funciton param (details)
  3. Fix broken build after previous commit (details)
  4. [VE] Support atomic fence (details)
  5. [Schedule] Add a MultiHazardRecognizer (details)
  6. [gn build] Port 61bc18de0b2 (details)
  7. [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate (details)
  8. [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate (details)
  9. [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred (details)
  10. [VE] Support atomic load (details)
  11. [PowerPC] Add test case for pr47830. NFC. (details)
  12. [ARM][SchedModels] Rename and generalize predicate. NFC (details)
  13. [AMDGPU] Emit new pal metadata by default (details)
  14. [AsmPrinter] Add per BB instruction mix remark. (details)
  15. [VE] Add integer arithmetic vector instructions (details)
  16. [VE] Add vector comparison and min/max (details)
  17. [Annotation] Allows annotation to carry some additional constant arguments. (details)
  18. [flang] Tighten rules to resolve procedure as intrinsic procedure (details)
  19. Try to fix buildbots after d3205bbca3e0002d76282878986993e7e7994779 (details)
  20. [lldb] [Process/FreeBSDRemote] Fix #include for i386 compat (details)
  21. [lldb] [test/Register] Use initial state for write tests (details)
  22. [lldb] [Process/NetBSD] Set xs_xstate_bv correctly when setting regs (details)
  23. [lldb] [Process/Linux] Reuse NativeRegisterContextWatchpoint_x86 (details)
  24. [lldb] Fix bitfield "frame var" for pointers (pr47743) (details)
  25. [lldb] Modernize PseudoTerminal::Fork (details)
  26. [NFC][InstrRefLDV] Fix a typo (details)
  27. [llvm-mca] Add few memory instructions to cortex-a57 test (details)
  28. tsan: add mips64 support in lib/tsan/go/buildgo.sh (details)
  29. [InstCombine] Add rotate tests where the shift amount is zero extended after masking (details)
  30. [InstCombine] Add support for zext(and(neg(amt),width-1)) rotate shift amount patterns (details)
  31. [clang] Suppress "follow-up" diagnostics on recovery call expressions. (details)
  32. [MLIR][mlir-spirv-cpu-runner] A pass to emulate a call to kernel in LLVM (details)
  33. [clang-fuzzer] CreateAndRunJITFunc - fix use after move static analyzer warning. (details)
  34. [llvm-ar][Object] Fix detection of need for 64-bit archive symbol tables (details)
  35. [DAGCombine] Add test case showing incorrect DAGCombine optimization (details)
Commit 4b5e848befdf786f5c905adf3b6c589216a24bff by mkazantsev
[NFC] Factor out common code into lambda for further improvement
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
Commit cdccc82f4825a1c9ac1bc0df2a222acdf5e820d4 by mkazantsev
[NFC] Remove unused funciton param
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
Commit bfabd7878b3240732d64b09eeadbc1eccc21910a by mkazantsev
Fix broken build after previous commit
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
Commit 52f03fe1151f65278c855651bb8f325cca8500ea by marukawa
[VE] Support atomic fence

Support atomic fence instruction and add a regression test.
Add MEMBARRIER pseudo insturction also to use it as a barrier
against to the compiler optimizations.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90112
The file was modifiedllvm/lib/Target/VE/VEISelLowering.h
The file was addedllvm/test/CodeGen/VE/atomic_fence.ll
The file was modifiedllvm/lib/Target/VE/VEISelLowering.cpp
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
Commit 61bc18de0b2edf8659053b06d73dfd2563143572 by david.green
[Schedule] Add a MultiHazardRecognizer

This adds a MultiHazardRecognizer and starts to make use of it in the
ARM backend. The idea of the class is to allow multiple independent
hazard recognizers to be added to a single base MultiHazardRecognizer,
allowing them to all work in parallel without requiring them to be
chained into subclasses. They can then be added or not based on cpu or
subtarget features, which will become useful in the ARM backend once
more hazard recognizers are being used for various things.

This also renames ARMHazardRecognizer to ARMHazardRecognizerFPMLx in the
process, to more clearly explain what that recognizer is designed for.

Differential Revision: https://reviews.llvm.org/D72939
The file was addedllvm/lib/CodeGen/MultiHazardRecognizer.cpp
The file was modifiedllvm/lib/Target/ARM/ARMHazardRecognizer.h
The file was addedllvm/include/llvm/CodeGen/MultiHazardRecognizer.h
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMHazardRecognizer.cpp
Commit 8000d277bafa15f52061961e1ff1020306487e38 by llvmgnsyncbot
[gn build] Port 61bc18de0b2
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Commit d613e39d52d263823324a695614c3c2981e94927 by eleviant
[ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90045
The file was modifiedllvm/include/llvm/Target/TargetInstrPredicate.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
Commit a4fc18e6410f1d88ef3171e4eb6afc33d750f69a by eleviant
[ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90029
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
Commit 99b2756517f23252d1bd60f2a15c5799df054ef3 by eleviant
[ARM][SchedModels] Get rid of IsLdrAm2ScaledPred

Differential revision: https://reviews.llvm.org/D90024
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
Commit f32992ad24470e0abfc310dcd62359f35378be7b by marukawa
[VE] Support atomic load

Support atomic load instruction and add a regression test.
VE uses release consitency, so need to insert fence around
atomic instructions.  This patch enable AtomicExpandPass
and use emitLeadingFence and emitTrailingFence mechanism
for such purpose.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90135
The file was modifiedllvm/lib/Target/VE/VEISelLowering.h
The file was addedllvm/test/CodeGen/VE/atomic_load.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was modifiedllvm/lib/Target/VE/VETargetMachine.cpp
The file was modifiedllvm/lib/Target/VE/VEISelLowering.cpp
Commit 82150dae8660c005823ed2da5c86cc1559a40c7b by lkail
[PowerPC] Add test case for pr47830. NFC.
The file was addedllvm/test/CodeGen/PowerPC/pr47830.ll
Commit a95ce5f65f13608f652d554ee37e61d9df7fa0d3 by eleviant
[ARM][SchedModels] Rename and generalize predicate. NFC
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
Commit a094b4fa4b7f00d3e389a55c401e4078534494b8 by sebastian.neubauer
[AMDGPU] Emit new pal metadata by default

If no pal metadata is given, default to the msgpack format instead of
the legacy metadata. This makes tests better readable.

Differential Revision: https://reviews.llvm.org/D90035
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-gs.ll
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/elf-notes.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-es.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-ls.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-cs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-hs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-vs.ll
Commit b2bec7cece9bb7d17799ac0af65a770cab4397ee by flo
[AsmPrinter] Add per BB instruction mix remark.

This patch adds a remarks that provides counts for each opcode per basic block.

An snippet of the generated information can be seen below.

The current implementation uses the target specific opcode for the counts. For example, on AArch64 this means we currently get 2 entries for `add` instructions if the block contains 32 and 64 bit adds. Similarly, immediate version are treated differently.

Unfortunately there seems to be no convenient way to get only the mnemonic part of the instruction as a string AFAIK. This could be improved in the future.

```
--- !Analysis
Pass:            asm-printer
Name:            InstructionMix
DebugLoc:        { File: arm64-instruction-mix-remarks.ll, Line: 30, Column: 30 }
Function:        foo
Args:
  - String:          'BasicBlock: '
  - BasicBlock:      else
  - String:          "\n"
  - String:          INST_MADDWrrr
  - String:          ': '
  - INST_MADDWrrr:   '2'
  - String:          "\n"
  - String:          INST_MOVZWi
  - String:          ': '
  - INST_MOVZWi:     '1'
```

Reviewed By: anemet, thegameg, paquette

Differential Revision: https://reviews.llvm.org/D89892
The file was addedllvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Commit 0acf7002433052c02487645759540431c3b94829 by marukawa
[VE] Add integer arithmetic vector instructions

Add VADD/VADS/VADX/VSUB/VSBS/VSBX/VMPY/VMPS/VMPX/VMPD/VDIV/VDVS/VDVX
instructions.  Also add regression tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89642
The file was addedllvm/test/MC/VE/VDVX.s
The file was addedllvm/test/MC/VE/VADS.s
The file was addedllvm/test/MC/VE/VDIV.s
The file was modifiedllvm/lib/Target/VE/VEInstrVec.td
The file was addedllvm/test/MC/VE/VDVS.s
The file was addedllvm/test/MC/VE/VSUB.s
The file was addedllvm/test/MC/VE/VSBX.s
The file was addedllvm/test/MC/VE/VMPX.s
The file was addedllvm/test/MC/VE/VMPS.s
The file was addedllvm/test/MC/VE/VSBS.s
The file was addedllvm/test/MC/VE/VADD.s
The file was addedllvm/test/MC/VE/VMPD.s
The file was addedllvm/test/MC/VE/VADX.s
The file was addedllvm/test/MC/VE/VMPY.s
Commit 8aa60f67dc8c67390680b7a3be0d31384300f09f by marukawa
[VE] Add vector comparison and min/max

Add VCMP/VCPS/VCPX/VCMS/VCMX vector instructions.  Also add regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89643
The file was addedllvm/test/MC/VE/VCPX.s
The file was modifiedllvm/lib/Target/VE/VEInstrVec.td
The file was addedllvm/test/MC/VE/VCMP.s
The file was addedllvm/test/MC/VE/VCMS.s
The file was addedllvm/test/MC/VE/VCMX.s
The file was addedllvm/test/MC/VE/VCPS.s
Commit d3205bbca3e0002d76282878986993e7e7994779 by tyker
[Annotation] Allows annotation to carry some additional constant arguments.

This allows using annotation in a much more contexts than it currently has.
especially when annotation with template or constexpr.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D88645
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedllvm/test/Analysis/CostModel/free-intrinsics-datalayout.ll
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
The file was modifiedclang/test/Misc/pragma-attribute-cxx.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedllvm/test/Transforms/InstCombine/assume_inevitable.ll
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/test/Sema/pragma-attribute.c
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/test/AST/ast-dump-attr.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.h
The file was modifiedllvm/test/Analysis/CostModel/free-intrinsics-no_info.ll
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/test/CodeGen/annotations-loc.c
The file was modifiedllvm/test/CodeGen/Generic/ptr-annotate.ll
The file was modifiedclang/include/clang/Sema/ParsedAttr.h
The file was modifiedclang/test/CodeGen/annotations-var.c
The file was addedclang/test/CodeGenCXX/attr-annotate.cpp
The file was modifiedclang/test/Parser/access-spec-attrs.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/free-intrinsics.ll
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
The file was modifiedclang/test/Parser/objc-implementation-attrs.m
The file was modifiedclang/test/Sema/annotate.c
The file was modifiedclang/test/Misc/pragma-attribute-objc.m
The file was addedclang/test/CodeGenCXX/attr-annotate2.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was addedclang/test/SemaCXX/attr-annotate.cpp
The file was modifiedclang/test/CodeGen/annotations-global.c
The file was modifiedclang/test/CodeGen/annotations-field.c
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
Commit 878b526409acb04b11f0a6b83c561bfee3521e57 by jperier
[flang] Tighten rules to resolve procedure as intrinsic procedure

2 Bug fixes:

- Do not resolve procedure as intrinsic if they appeared in an
  EXTERNAL attribute statement (one path was not considering this flag)

- Emit an error if a procedure resolved to be an intrinsic function
  (resp. subroutine) is used as a subroutine (resp. function).
  Lowering was attempted while the evaluate::Expression for the
  call was missing without any errors.

1 behavior change:

- Do not implicitly resolve subroutines (resp. functions) as intrinsics
  because their name is the name of an intrinsic function (resp.
  subroutine). Add justification in documentation.

Reviewed By: klausler, tskeith

Differential Revision: https://reviews.llvm.org/D90049
The file was modifiedflang/include/flang/Evaluate/intrinsics.h
The file was modifiedflang/lib/Semantics/resolve-names.cpp
The file was addedflang/test/Semantics/call16.f90
The file was addedflang/test/Semantics/symbol19.f90
The file was modifiedflang/lib/Evaluate/intrinsics.cpp
The file was modifiedflang/docs/Intrinsics.md
Commit 4afa077899b1e3def4cff475deae73681db04e21 by tyker
Try to fix buildbots after d3205bbca3e0002d76282878986993e7e7994779
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Commit 7acf2e2e1e8f7e2eac2dd5bbf7d752ba7ad4e79c by mgorny
[lldb] [Process/FreeBSDRemote] Fix #include for i386 compat

Include <x86/fpu.h> rather than <machine/fpu.h>, as the latter is not
present on i386.

Differential Revision: https://reviews.llvm.org/D90128
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
Commit 37d4d3bb4daf409102237132ae8e1db250da83be by mgorny
[lldb] [test/Register] Use initial state for write tests

Reset registers to their 'initial' state instead of a semi-random
pattern in write tests.  While the latter might have been helpful
while debugging failures (i.e. to distinguish unmodified registers
from mistakenly written zeroes), the former makes it possible to test
whether xstate_bv field is written correctly when using XSAVE.

With this change, the four relevant tests start failing on NetBSD
without D90105.

Differential Revision: https://reviews.llvm.org/D90114
The file was modifiedlldb/test/Shell/Register/Inputs/x86-mm-xmm-write.cpp
The file was modifiedlldb/test/Shell/Register/Inputs/x86-ymm-write.cpp
The file was modifiedlldb/test/Shell/Register/Inputs/x86-zmm-write.cpp
The file was modifiedlldb/test/Shell/Register/Inputs/x86-64-write.cpp
Commit a8902376651a7adbacd0c1934d9f70bdb9fad7f0 by mgorny
[lldb] [Process/NetBSD] Set xs_xstate_bv correctly when setting regs

Ensure that xs_xstate_bv is set correctly before calling
WriteRegisterSet().  The bit can be clear if the relevant registers
were at their initial state when they were read, and it needs to be set
in order to apply changes from the XState structure.

Differential Revision: https://reviews.llvm.org/D90105
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
Commit f5ca27569eacc398f0e4fc63a9b55cafac398c04 by mgorny
[lldb] [Process/Linux] Reuse NativeRegisterContextWatchpoint_x86

Differential Revision: https://reviews.llvm.org/D90119
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
Commit 97ca9ca180f0810adcc1637d1a6dd32a04f63cfe by pavel
[lldb] Fix bitfield "frame var" for pointers (pr47743)

Displaying large packed bitfields did not work if one was accessing them
through a pointer, and he used the "->" notation ("[0]." notation is
fine). The reason for that is that implicit dereference in -> is plumbed
all the way down to ValueObjectChild::UpdateValue, where the process of
fetching the child value was forked for this flag. The bitfield
"sliding" code was implemented only for the branch which did not require
dereferencing.

This patch restructures the function to avoid this mistake. Processing
now happens in two stages.
- first the parent is dereferenced (if needed)
- then the child value is computed (this step includes sliding and is
  common for both branches)

Differential Revision: https://reviews.llvm.org/D89236
The file was modifiedlldb/test/API/lang/c/bitfields/main.c
The file was modifiedlldb/test/API/lang/c/bitfields/TestBitfields.py
The file was modifiedlldb/source/Core/ValueObjectChild.cpp
Commit e4cc6e9bcdff5fe979ab72025cb803d723cd9c31 by pavel
[lldb] Modernize PseudoTerminal::Fork
The file was modifiedlldb/source/Plugins/Process/FreeBSD/ProcessMonitor.cpp
The file was modifiedlldb/include/lldb/Host/PseudoTerminal.h
The file was modifiedlldb/source/Host/common/PseudoTerminal.cpp
Commit a64b2c93662d8c9bbe49561980ed6c78892491d3 by djtodoro
[NFC][InstrRefLDV] Fix a typo
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
Commit 1876d06ea31f38411012841971a3ff69b4a864d4 by eleviant
[llvm-mca] Add few memory instructions to cortex-a57 test
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
Commit 5cad535ccfebf9b41a57cf2788d8de7a765f7f35 by dvyukov
tsan: add mips64 support in lib/tsan/go/buildgo.sh

Enable mips64 support in buildgo.sh.

Author: mzh (Meng Zhuo)
Reviewed-in: https://reviews.llvm.org/D90130
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform.h
The file was modifiedcompiler-rt/lib/tsan/go/buildgo.sh
Commit 821f3b763ae506b329144550028a4fd0cba0a361 by llvm-dev
[InstCombine] Add rotate tests where the shift amount is zero extended after masking
The file was modifiedllvm/test/Transforms/InstCombine/rotate.ll
Commit 6b2eb31e1e2db1f3ca7a5c4914ab08cb18698de7 by llvm-dev
[InstCombine] Add support for zext(and(neg(amt),width-1)) rotate shift amount patterns

Alive2: https://alive2.llvm.org/ce/z/bCvvHd
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/rotate.ll
Commit efa9aaad703e6b150980ed1a74b4e7c9da7d85a2 by hokein.wu
[clang] Suppress "follow-up" diagnostics on recovery call expressions.

Because of typo-correction, the AST can be transformed, and the transformed
AST is marginally useful for diagnostics purpose, the following
diagnostics usually do harm than good (easily cause confusions).

Given the following code:

```
void abcc();
void test() {
  if (abc());
  // diagnostic 1 (for the typo-correction): the typo is correct to `abcc()`, so the code is treate as `if (abcc())` in AST perspective;
  // diagnostic 2 (for mismatch type): we perform an type-analysis on `if`, discover the type is not match
}
```

The secondary diagnostic "convertable to bool" is likely bogus to users.

The idea is to use RecoveryExpr (clang's dependent mechanism) to preserve the
recovery behavior but suppress all follow-up diagnostics.

Differential Revision: https://reviews.llvm.org/D89946
The file was modifiedclang/test/SemaCXX/typo-correction-delayed.cpp
The file was modifiedclang/test/AST/ast-dump-recovery.cpp
The file was modifiedclang/lib/Sema/SemaOverload.cpp
Commit cae4067ec1cdf7846aa46dab13d3bc1f58b76016 by antiagainst
[MLIR][mlir-spirv-cpu-runner] A pass to emulate a call to kernel in LLVM

This patch introduces a pass for running
`mlir-spirv-cpu-runner` - LowerHostCodeToLLVMPass.

This pass emulates `gpu.launch_func` call in LLVM dialect and lowers
the host module code to LLVM. It removes the `gpu.module`, creates a
sequence of global variables that are later linked to the varables
in the kernel module, as well as a series of copies to/from
them to emulate the memory transfer to/from the host or to/from the
device sides. It also converts the remaining Standard dialect into
LLVM dialect, emitting C wrappers.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D86112
The file was modifiedmlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt
The file was addedmlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
The file was addedmlir/test/Conversion/SPIRVToLLVM/lower-host-to-llvm-calls.mlir
Commit e4991867fb5ace434640bfacfd28720ad031d33c by llvm-dev
[clang-fuzzer] CreateAndRunJITFunc - fix use after move static analyzer warning.

We were using the unique_ptr M to determine the triple after it had been moved in the EngineBuilder constructor.
The file was modifiedclang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp
Commit 2add7c5cf3ebbba629d2756b3e91728e55b40881 by andrew.ng
[llvm-ar][Object] Fix detection of need for 64-bit archive symbol tables

The code to detect the requirement for 64-bit offsets in the archive
symbol table was not correctly accounting for the archive file signature
and the size of all the contents of the symbol table itself, e.g. the
symbol table's header and string table. Also was not considering the
variation in symbol table formats. This could result in the creation of
large archives with a corrupt symbol table.

Change the testing environment variable SYM64_THRESHOLD to be an
absolute value rather than a power of 2 in order to enable precise
testing of this detection code.

Differential Revision: https://reviews.llvm.org/D89891
The file was modifiedllvm/test/Object/archive-symtab.test
The file was modifiedllvm/lib/Object/ArchiveWriter.cpp
Commit ffa6d2afa4a6f35e2e99172a17d489bcec7f0353 by fraser
[DAGCombine] Add test case showing incorrect DAGCombine optimization

This optmization produces incorrect results when the vector element type
is not byte-sized. Related to D78568.
The file was addedllvm/test/CodeGen/AMDGPU/extract-load-i1.ll