FailedChanges

Summary

  1. [zorg][PowerPC] Add tags for builders (details)
Commit 237d0b4da0c0df5ffec99ce30e62b3acc7d15c3c by Jinsong Ji
[zorg][PowerPC] Add tags for builders

Add the tag for all PowerPC builders so that we can identify them
easily.
eg: Check all with http://lab.llvm.org:8011/#/waterfall?tags=%20ppc

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D90263
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [yaml2obj][test] - Merge strtab-implicit-sections-*.yaml into strtab-implicit-sections.yaml and improve testing of .shstrtab (details)
  2. [ADT] Fix for ImmutableMapRef (details)
  3. [llvm-exegesis] Do not try to assign random registers twice. (details)
  4. [DebugInfo] [NFCI] Additional test for support of DW_TAG_generic_subrange (details)
  5. [llvm-readobj/elf] - Fix a crash when dumping a dynamic relocation that refer to a symbol past the EOF. (details)
  6. [lldb] Use reverse connection method for lldb-server tests (details)
  7. [libunwind] Fix linker flag handling in the tests. (details)
  8. [libcxx] Add targets to available features. (details)
  9. [libcxx] [docs] [NFC] Fix typo. (details)
  10. [flang][openacc] Enforce no modifier on enter data and exit data clauses (details)
  11. [mlir][openacc] Add if and device_type to update op (details)
  12. [VE] Support register aliases in llvm-mc (details)
  13. [VE] Add missing symbolic branch patterns (details)
  14. Revert "clang-format: Add a consumer to diagnostics engine" (details)
  15. [VE] Add missing BCR format (details)
  16. [SVE] Remove TypeSize comparison operators (details)
  17. [MLIR] Support walks over regions and blocks (details)
  18. [AMDGPU] Fix double space in disassembly of some DPP instructions (details)
  19. [AMDGPU] Fix double space in disassembly of s_set_gpr_idx_mode (details)
  20. [AMDGPU] Remove gds operand from ds_gws_* MachineInstrs (details)
  21. [libc++] Remove additional uses of std::rand() missed by 63aeadb4849d (details)
  22. [VE] Change to use integrated assembly by defualt (details)
  23. [ARM] Add IT block generation test (details)
  24. [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz (details)
  25. [mlir][Linalg] Make Linalg fusion a test pass (details)
  26. [InstCombine] visitShl - ensure inner shifts have inrange amounts (details)
  27. [NFC] Add more tests for DISubprogram verifier (details)
  28. [sanitizer] Print errno for report file open failure (details)
  29. [AMDGPU] Use pseudo instructions for readlane/writelane (details)
  30. [MC] Error for .globl/.local which change the symbol binding and warn for .weak (details)
  31. [x86] add test for umul intrinsic costs; NFC (details)
  32. [AMDGPU] Add __builtin_amdgcn_grid_size (details)
  33. [X86] Add PR46393 test case (details)
  34. [mlir][gpu] Allow gpu.launch_func to be async. (details)
  35. [ThinLTO] Fix empty .llvmcmd sections (details)
  36. [nfc] [lldb] Remove excessive parentheses in SymbolFileDWARF::GetUID (details)
  37. [MemProf] Augment test to debug avr bot failure (details)
  38. Revert "[mlir][gpu] Allow gpu.launch_func to be async." (details)
  39. [AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds (details)
Commit 18b4b0b80deaf4f9da4fbe8e6279e28514595b11 by grimar
[yaml2obj][test] - Merge strtab-implicit-sections-*.yaml into strtab-implicit-sections.yaml and improve testing of .shstrtab

This creates `strtab-implicit-sections.yaml` and merges 2 `strtab-implicit-sections*` tests into it.
I've also added a few tests for `.shstrtab` section related to section flags.

With that we have a single place where we can test implicit string table sections and
the `.shstrtab` section in particular.

Differential revision: https://reviews.llvm.org/D90372
The file was removedllvm/test/tools/yaml2obj/ELF/strtab-implicit-sections-flags.yaml
The file was addedllvm/test/tools/yaml2obj/ELF/strtab-implicit-sections.yaml
The file was removedllvm/test/tools/yaml2obj/ELF/strtab-implicit-sections-size-content.yaml
Commit 184eb4fa4f1cc871692fa390261df8c25ddcc7ec by adam.balogh
[ADT] Fix for ImmutableMapRef

The `Root` member of `ImmutableMapRef` was changed recently from a plain
pointer to `IntrusiveRefCntPtr`. However, the `Profile` member function
was not adjusted. This results in comilation error whenever the
`Profile` method is used on an `ImmutableMapRef`. This patch fixes this
issue and also adds unit tests for `ImmutableMapRef`.

Differential Revision: https://reviews.llvm.org/D89486
The file was modifiedllvm/unittests/ADT/ImmutableMapTest.cpp
The file was modifiedllvm/include/llvm/ADT/ImmutableMap.h
Commit 24bf8faabd625c213e6275c7cd77d4883f564489 by courbet
[llvm-exegesis] Do not try to assign random registers twice.

Doing a random assignment assigns both tested (forward) and back-to-back
(backward) instructions.

When none of the tested instruction and back-to-back instruction have
implicit aliasing, we're currently trying to do a random register
asignment twice.

Fix this (see PR26418).

Differential Revision: https://reviews.llvm.org/D90380
The file was modifiedllvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
The file was addedllvm/test/tools/llvm-exegesis/X86/latency-IN16rr.s
Commit aa71874f6b9bb9bddca54e9d89d5725dcc77090f by AlokKumar.Sharma
[DebugInfo] [NFCI] Additional test for support of DW_TAG_generic_subrange

As suggested by dstenb, additional test is added to check emission of DW_OP_consts.
Differential Revision: https://reviews.llvm.org/D89218
The file was addedllvm/test/DebugInfo/X86/dwarfdump-signed_const.ll
Commit d6d6fdb068afd043b9cfb9c7b5adbc29b1440aad by grimar
[llvm-readobj/elf] - Fix a crash when dumping a dynamic relocation that refer to a symbol past the EOF.

There is a possible scenario when we crash when dumping dynamic relocations.
For that we should have no section headers (to take the number of synamic symbols from)
and a dynamic relocation that refers to a symbol with an index that is too large to be in a file.

The patch fixes it.

Differential revision: https://reviews.llvm.org/D90214
The file was modifiedllvm/test/tools/llvm-readobj/ELF/broken-dynamic-reloc.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 8cc49bec2e067808e4b4d091a351fd66616d7b18 by pavel
[lldb] Use reverse connection method for lldb-server tests

This fixes an flakyness is all gdb-remote tests. These tests have been
(mildly) flaky since we started using "localhost" instead of 127.0.0.1
in the test suite. The reason is that lldb-server needs to create two
sockets (v4 and v6) to listen for localhost connections. The algorithm
it uses first tries to select a random port (bind(localhost:0)) for the
first address, and then bind the same port for the second one.

The creating of the second socket can fail as there's no guarantee that
port will be available -- it seems that the (linux) kernel tries to
choose an unused port for the first socket (I've had to create thousands
of sockets to reproduce this reliably), but this can apparantly fail
when the system is under load (and our test suite creates a _lot_ of
sockets).

The socket creationg operation is considered successful if it creates at
least one socket is created, but the test harness has no way of knowing
which one it is, so it can end up connecting to the wrong address.

I'm not aware of a way to atomically create two sockets bound to the
same port. One way to fix this would be to make lldb-server report the
address is it listening on instead of just the port. However, this would
be a breaking change and it's not clear to me that's worth it (the
algorithm works pretty well under normal circumstances).

Instead, this patch sidesteps that problem by using "reverse"
connections. This way, the test harness is responsible for creating the
listening socket so it can pass the address that it has managed to open.
It also results in much simpler code overall.

To preserve test coverage for the named pipe method, I've moved the
relevant code to a dedicated test. To avoid original problem, this test
passes raw addresses (as obtained by getaddrinfo(localhost)) instead of
"localhost".

Differential Revision: https://reviews.llvm.org/D90313
The file was addedlldb/test/API/tools/lldb-server/commandline/TestGdbRemoteConnection.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
The file was removedlldb/test/API/tools/lldb-server/commandline/TestStubReverseConnect.py
Commit 05598e3d3047cf028cc3e61f3268ff7d999e5f26 by daniel.kiss
[libunwind] Fix linker flag handling in the tests.

--export-dynamic is not always available on all targets.
-funwind-tables was a duplicate in the lit.site.cfg.in.

Reviewed By: ldionne

Differential Revision: https://reviews.llvm.org/D90202
The file was modifiedlibunwind/test/lit.site.cfg.in
The file was modifiedlibunwind/test/libunwind/test/config.py
Commit fd1c064845e598387b33ad4f548fde141f44728e by daniel.kiss
[libcxx] Add targets to available features.

This patch add the target-* (x86_64-*) as used elsewhere in llvm.

Reviewed By: #libc, #libc_abi, ldionne

Differential Revision: https://reviews.llvm.org/D88027
The file was modifiedlibcxx/utils/libcxx/test/config.py
Commit 6648414b2b7dd3802e6931be2f657926b97d0764 by marek
[libcxx] [docs] [NFC] Fix typo.
The file was modifiedlibcxx/docs/TestingLibcxx.rst
Commit 75ba29ac5654b622107653a0fd33f84846b4e39f by clementval
[flang][openacc] Enforce no modifier on enter data and exit data clauses

Enter data can have the copyin clause and exit data can have the copyout clause.
Both clauses support modifier with other directive but for these two directives no modifier
are supported. This semantic check enforce this rule.

Reviewed By: kiranktp

Differential Revision: https://reviews.llvm.org/D90280
The file was modifiedflang/lib/Semantics/check-acc-structure.h
The file was modifiedflang/test/Semantics/acc-clause-validity.f90
The file was modifiedflang/lib/Semantics/check-acc-structure.cpp
Commit 1ce5f8bbb6f3fb581fd4c5905e5574c8b9a09268 by clementval
[mlir][openacc] Add if and device_type to update op

Update op is modelling the update directive (2.14.4) from the OpenACC specs.
An if condition and a device_type list can be attached to the directive. This patch add
these two information to the current op.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D90310
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir
Commit 07d199660104b3e2e5e6e3f06412cfe66f9a6b61 by marukawa
[VE] Support register aliases in llvm-mc

Support register aliases in MC layer to compile existing assembly
files with clang and integrated assembler.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90383
The file was addedllvm/test/MC/VE/register.s
The file was modifiedllvm/lib/Target/VE/VERegisterInfo.td
Commit f52c1b53310a1715b85b358a5c3de0e1f7c2e227 by marukawa
[VE] Add missing symbolic branch patterns

Add missing symbolic branch patterns to a regression test.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90388
The file was modifiedllvm/test/MC/VE/sym-br.s
Commit 637c77fda64a9b4c021be9c2f89fe8995613c7ed by thakis
Revert "clang-format: Add a consumer to diagnostics engine"

This reverts commit df00267f1fdb0b098dc42f1caa8a59b29c8e0e5f.
clang-format should not depend on Frontend, see comment on
https://reviews.llvm.org/D90121.
The file was modifiedclang/tools/clang-format/ClangFormat.cpp
The file was modifiedclang/tools/clang-format/CMakeLists.txt
Commit 58a6b7bcdee24d72879d1c19331479ae94af6d41 by marukawa
[VE] Add missing BCR format

Add missing "BCR %sy, 0, target" format instruction and a regression
test for this format.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90387
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was modifiedllvm/test/MC/VE/BCR.s
Commit 8c058dd2d752f9ac26a085eb93e1b6e864583be0 by david.sherwood
[SVE] Remove TypeSize comparison operators

All known instances in the code where we relied upon the TypeSize
comparison operators have now been changed to either use scalar
interger comparisons or one of the TypeSize::isKnownXY functions.
It is now safe to remove the comparison operators.

Differential Revision: https://reviews.llvm.org/D90160
The file was modifiedllvm/include/llvm/Support/TypeSize.h
Commit dbae3d50f114a8ec0a7c3211e3b1b9fb6ef22dbd by frgossen
[MLIR] Support walks over regions and blocks

Add specializations for `walk` to allow traversal of regions and blocks.

Differential Revision: https://reviews.llvm.org/D90379
The file was modifiedmlir/include/mlir/IR/Visitors.h
The file was modifiedmlir/lib/IR/Visitors.cpp
The file was modifiedmlir/include/mlir/IR/Block.h
The file was modifiedmlir/include/mlir/IR/Operation.h
The file was modifiedmlir/lib/Analysis/Liveness.cpp
The file was modifiedmlir/include/mlir/Analysis/Liveness.h
Commit e9dd2c4fe2db5c2b242b0589bc407cb3040fbdd2 by jay.foad
[AMDGPU] Fix double space in disassembly of some DPP instructions

Differential Revision: https://reviews.llvm.org/D90373
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit a442fad911b3da4ba39a14539c5a100b5935341e by jay.foad
[AMDGPU] Fix double space in disassembly of s_set_gpr_idx_mode

Differential Revision: https://reviews.llvm.org/D90374
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
Commit 7a79921edd74e81a05f15491e5cdb093c653e06c by jay.foad
[AMDGPU] Remove gds operand from ds_gws_* MachineInstrs

The operand value was always 1 (except in some bad MIR tests) so it was
redundant.

Differential Revision: https://reviews.llvm.org/D90378
The file was modifiedllvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/gws-hazards.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-m0.mir
Commit bd8884f05e7586dd09aaab843c07361414343916 by Louis Dionne
[libc++] Remove additional uses of std::rand() missed by 63aeadb4849d
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/right_shift_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/count.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.operators/op_or.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/flip_all.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/op_eq_eq.pass.cpp
The file was addedlibcxx/test/std/utilities/template.bitset/bitset_test_cases.h
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/left_shift.pass.cpp
The file was removedlibcxx/test/std/utilities/template.bitset/bitset.members/bitset_test_cases.h
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/left_shift_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/index_const.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/index.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/op_xor_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/op_or_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/set_one.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.operators/op_and.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/op_and_eq.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/not_all.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/right_shift.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.operators/op_not.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/test.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/to_string.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/flip_one.pass.cpp
The file was modifiedlibcxx/test/std/utilities/template.bitset/bitset.members/reset_one.pass.cpp
Commit b5ac3721c8a497ebf33a9d0cc0d300564b0cefe1 by marukawa
[VE] Change to use integrated assembly by defualt

We've implemented integrated assembler.  Now, we change to use
integrated assembler by default.  Update a regression test also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90396
The file was modifiedclang/lib/Driver/ToolChains/VEToolchain.h
The file was modifiedclang/test/Driver/ve-toolchain.c
Commit 7b8de9fc6bce01daed49d3f6a8bd71a25e8c717f by nicholas.guy
[ARM] Add IT block generation test

D88496 introduces some new behaviour to IT block generation,
behaviour which is not covered by the current unit tests.
This adds one to cover it

Differential Revision: https://reviews.llvm.org/D90398
The file was addedllvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
Commit eb9fe24eaf2d602a5b5b59d253ad4946d850bd54 by nicholas.guy
[ARM] Fix IT block generation after Thumb2SizeReduce with -Oz

Fixes a regression caused by D82439, in which IT blocks were no longer being generated when -Oz is present.

Differential Revision: https://reviews.llvm.org/D88496
The file was modifiedllvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
The file was modifiedllvm/test/CodeGen/Thumb2/constant-hoisting.ll
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
Commit 9b17bf2e54c71b36bf28fbab05698fb73ea8dda9 by nicolas.vasilache
[mlir][Linalg] Make Linalg fusion a test pass

Linalg "tile-and-fuse" is currently exposed as a Linalg pass "-linalg-fusion" but only the mechanics of the transformation are currently relevant.
Instead turn it into a "-test-linalg-greedy-fusion" pass which performs canonicalizations to enable more fusions to compose.
This allows dropping the OperationFolder which is not meant to be used with the pattern rewrite infrastructure.

Differential Revision: https://reviews.llvm.org/D90394
The file was modifiedmlir/test/Dialect/Linalg/fusion-2-level.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/test/Dialect/Linalg/fusion-indexed-generic.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/test/Dialect/Linalg/fusion.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
The file was modifiedmlir/test/lib/Transforms/TestLinalgFusionTransforms.cpp
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.td
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.h
The file was modifiedmlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir
Commit dcb3dc101d80a5786f7f897f0090c081d2912443 by llvm-dev
[InstCombine] visitShl - ensure inner shifts have inrange amounts

Noticed when fixing OSS Fuzz #26716
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/shift.ll
Commit abf31f278cb629d8bc7f1683b7bfceb8d3f011c2 by scott.linder
[NFC] Add more tests for DISubprogram verifier

Minimum amount of tests to cover (most) of the DISubprogram verifier
checks.

Reviewed By: vsk

Differential Revision: https://reviews.llvm.org/D90340

Change-Id: Icd25dac64f87f6dcf67ff3443eb4f95af18d05a8
The file was addedllvm/test/DebugInfo/Generic/verifier-invalid-disubprogram.ll
Commit 81f7b96ed0a2295e0b82ca185019370ac8e1895e by tejohnson
[sanitizer] Print errno for report file open failure

To help debug failures, specifically the llvm-avr-linux bot failure from
5c20d7db9f2791367b9311130eb44afecb16829c:

http://lab.llvm.org:8011/#/builders/112/builds/407/steps/5/logs/FAIL__MemProfiler-x86_64-linux-dynamic__log_path_t

Also re-enable the failing test which I temporarily disabled, to
see if this change will help identify why that particular log file can't
be opened for write on that bot (when another log file in the same
directory could earlier in the test).

Differential Revision: https://reviews.llvm.org/D90120
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_file.cpp
The file was modifiedcompiler-rt/test/memprof/TestCases/log_path_test.cpp
Commit 58de4b205310d18614eabdcbaa1772e9fc090df3 by jay.foad
[AMDGPU] Use pseudo instructions for readlane/writelane

This reverts r227987 "R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2".

All the codegen changes are caused by the post-RA scheduler no longer
treating readlane/writelane as scheduling barriers due to having
unmodelled side effects. (The pseudos are hasSideEffects = 0, but the
real instructions are hasSideEffects = ? which TableGen conservatively
treats as 1.)

Differential Revision: https://reviews.llvm.org/D90401
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-realign.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/csr-gfx10.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill192.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sibling-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
Commit 8f8b5e5587c3e204f21db975a0a76d4462ce3c57 by i
[MC] Error for .globl/.local which change the symbol binding and warn for .weak

GNU as let .weak override .globl since binutils-gdb
5ca547dc2399a0a5d9f20626d4bf5547c3ccfddd (1996) while MC lets the last
directive win (PR38921).

This caused an issue to Linux's powerpc port which has been fixed by
http://git.kernel.org/linus/968339fad422a58312f67718691b717dac45c399

Binding overriding is error-prone. This patch disallows a changed binding.
(https://sourceware.org/pipermail/binutils/2020-March/000299.html )

Our behavior regarding `.globl x; .weak x` matches GNU as. Such usage is
still suspicious but we issue a warning for now. We may upgrade it to an
error in the future.

Reviewed By: jhenderson, nickdesaulniers

Differential Revision: https://reviews.llvm.org/D90108
The file was addedllvm/test/MC/ELF/symbol-binding-changed.s
The file was modifiedllvm/lib/MC/MCELFStreamer.cpp
Commit d5a75e7738d0ca2955b3b10a7d4631110f930b67 by spatel
[x86] add test for umul intrinsic costs; NFC
The file was modifiedllvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll
Commit dee7704829bd421ad3cce4b2132d28f4459b7319 by jonathanchesterfield
[AMDGPU] Add __builtin_amdgcn_grid_size

[AMDGPU] Add __builtin_amdgcn_grid_size

Similar to D76772, loads the data from the dispatch pointer. Marked invariant.

Patch also updates the openmp devicertl to use this builtin.

Reviewed By: yaxunl

Differential Revision: https://reviews.llvm.org/D90251
The file was modifiedclang/include/clang/Basic/BuiltinsAMDGPU.def
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/src/target_impl.hip
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn.cl
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
Commit 93ebefb9ee75143625d701250e69e701df4a7702 by llvm-dev
[X86] Add PR46393 test case
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
Commit ec7780ebdab480139596c3cb08ee77d7035457b3 by csigg
[mlir][gpu] Allow gpu.launch_func to be async.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D89324
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/test/Dialect/GPU/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
The file was modifiedmlir/test/Dialect/GPU/invalid.mlir
Commit 13aee94bc710bfa6277c1f07146c714ee65bf2de by mtrofin
[ThinLTO] Fix empty .llvmcmd sections

When passing -lto-embed-bitcode=post-merge-pre-opt, we were getting
empty .llvmcmd sections. It turns out that is because the
CodeGenOptions::CmdArgs field was only populated when clang saw
-fembed-bitcode={all|marker}.

This patch always populates the CodeGenOptions::CmdArgs. The overhead
of carrying through in memory in all cases is likely negligible in
the grand schema of things, and it keeps the using code simple.

Differential Revision: https://reviews.llvm.org/D90366
The file was modifiedclang/test/CodeGen/thinlto_embed_bitcode.ll
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
Commit 41f2bb232cc064c0289de877552cbd6a077a7ba5 by jan.kratochvil
[nfc] [lldb] Remove excessive parentheses in SymbolFileDWARF::GetUID
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
Commit 240b4217382d488cc3e3db823dfa362c9ad3e729 by tejohnson
[MemProf] Augment test to debug avr bot failure

After 81f7b96ed0a2295e0b82ca185019370ac8e1895e, I can see that the
reason this test is failing on llvm-avr-linux is that it doesn't think
the directory exists (error comes during file open for write command).
Not sure why since this is the main test Output directory and we created
a different file there earlier in the test from the same file open
invocation. Print directory contents in an attempt to debug.
The file was modifiedcompiler-rt/test/memprof/TestCases/log_path_test.cpp
Commit 834618a2ffbdaf3f2e94025b53f49f3764e5adb0 by joker.eph
Revert "[mlir][gpu] Allow gpu.launch_func to be async."

This reverts commit ec7780ebdab480139596c3cb08ee77d7035457b3.

One of the bot is crashing in a test related to this change.
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/test/Dialect/GPU/invalid.mlir
The file was modifiedmlir/test/Dialect/GPU/ops.mlir
Commit 9cee87d72a0bdf07f888f61c8988159a5fe6cd74 by jay.foad
[AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds

By setting up the AsmStrings correctly we can remove some special cases
from AMDGPUInstPrinter::printOffset.

Differential Revision: https://reviews.llvm.org/D90307
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Summary

  1. [zorg][PowerPC] Add tags for builders (details)
Commit 237d0b4da0c0df5ffec99ce30e62b3acc7d15c3c by Jinsong Ji
[zorg][PowerPC] Add tags for builders

Add the tag for all PowerPC builders so that we can identify them
easily.
eg: Check all with http://lab.llvm.org:8011/#/waterfall?tags=%20ppc

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D90263
The file was modifiedbuildbot/osuosl/master/config/builders.py