Started 1 mo 4 days ago
Took 4 hr 25 min

Success Build #2468 (Jan 22, 2021 3:12:44 PM)

  1. [SimplifyLibCalls] Skip unused calls in sincos transform (details)
  2. Remove obsolete TODOs (details)
  3. [mlir][OpFormatGen] Add support for anchoring optional groups with types (details)
  4. [CodeGen] Use getCharWidth() more consistently in CGRecordLowering. NFC (details)
  5. [CGExpr] Use getCharWidth() more consistently in CCGExprConstant. NFC (details)
  6. [libc++] Introduce __bits (details)
  7. [NewPM][AMDGPU] Skip adding CGSCCOptimizerLate callbacks at O0 (details)
  8. [Tests] Add willreturn to libcalls in some tests (details)
  9. [RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec. (details)
  10. [RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0.93 bitmanip spec. (details)
  11. [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec. (details)
  12. [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec. (details)
  13. [RISCV] Add Zba feature and move add.uw and slli.uw to it. (details)
  14. [RISCV] Add SH*ADD(.UW) instructions to Zba extension based on 0.93 bitmanip spec. (details)
  15. [RISCV] Move Shift Ones instructions from Zbb to Zbp to match 0.93 bitmanip spec. (details)
  16. [RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec. (details)
  17. [RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec. (details)
  18. [RISCV] Change zext.w to be an alias of add.uw rd, rs1, x0 instead of pack. (details)
  19. [RISCV] Move pack instructions to Zbp extension only. (details)
  20. [RISCV] Add zext.h instruction to Zbb. (details)
  21. [RISCV] Add support for rev8 and orc.b to Zbb. (details)
  22. [RISCV] Add xperm.* instructions to Zbp extension. (details)
  23. [RISCV] Update B extension version to 0.93. (details)
  24. [mlir][Linalg] Disable fusion of tensor_reshape op by expansion when unit-dims are involved (details)
  25. [InstSimplify] Add willreturn to more libcall tests (NFC) (details)
  26. [Analysis] Support AIX vec_malloc routines (details)
  27. [RISCV] Add isel patterns for SH*ADD(.UW) (details)
  28. [Inline] Precommit tests for dead calls and willreturn. (details)
  29. [gn build] Port 622eaa4a4cea (details)
  30. [lld-macho] Ignore -lto_library (details)
  31. [RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32. (details)
  32. [GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method (details)
  33. [VFS] Fix inconsistencies between relative paths and fallthrough. (details)
  34. [NFC][SimplifyCFG] PerformBranchToCommonDestFolding(): fix instruction name preservation (details)
  35. [NFC][SimplifyCFG] fold-branch-to-common-dest.ll: reduce complexity of @pr48450* test (details)
  36. [NFC][SimplifyCFG] PerformBranchToCommonDestFolding(): move instruction cloning to after CFG update (details)
  37. [SimplifyCFG] FoldBranchToCommonDest(): re-lift restrictions on liveout uses of bonus instructions (details)
  38. Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method" (details)
  39. Revert "[AArch64][GlobalISel] Implement widenScalar for signed overflow" (details)
  40. Revert "[AArch64][GlobalISel] Make G_USUBO legal and select it." (details)
  41. [Matrix] Propagate shape information through fneg (details)
  42. [mlir][Linalg] Make Fill operation work on tensors. (details)
  43. [RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate. (details)
  44. [RGT][ADT] Remove test assertion that will not be executed (details)
  45. [lldb] FixFileSystem::GetExternalPath for VFS API change (details)
  46. [RGT] Don't use EXPECT* macros in a subprocess that exits by signalling (details)
  47. [RGT][TextAPI] Remove a zero-trip loop and the assertions within it (details)
  48. [CodeComplete] Add ranged for loops code pattern. (details)
  49. PR47682: Merge the DeclContext of a merged FunctionDecl before we inherit (details)
  50. Change materializeFrameBaseRegister() to return register (details)
  51. [AMDGPU] Fix FP materialization/resolve with flat scratch (details)
  52. Change static buffer to be BSS instead of DATA in HandlePacket_qSpeedTest (details)
  53. [libomptarget] Build cuda plugin without cuda installed locally (details)
  54. ADT: Use 'using' to inherit assign and append in SmallString (details)
  55. [LoopDeletion] Handle inner loops w/untaken backedges (details)
  56. [RISCV] Implement vloxseg/vluxseg intrinsics. (details)
  57. [RISCV] Add RV32 test cases for vluxseg. (details)
  58. [RISCV] Add RV64 test cases for vluxseg. (details)
  59. [RISCV] Add RV32 test cases for vloxseg. (details)
  60. [RISCV] Add RV64 test cases for vloxseg. (details)
  61. [RISCV] Implement vsoxseg/vsuxseg intrinsics. (details)
  62. [RISCV] Add RV32 test cases for vsuxseg. (details)
  63. [RISCV] Add RV64 test cases for vsuxseg. (details)
  64. [RISCV] Add RV32 test cases for vsoxseg. (details)
  65. [RISCV] Add RV64 test cases for vsoxseg. (details)
  66. [OpenMP] Remove unnecessary pointer checks in a few locations (details)
  67. [InstCombine] remove incompatible attribute when simplifying some lib calls (details)
  68. Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it." (details)

Started by upstream project LLDB Incremental build number 27813
originally caused by:

  • Started by timer
  • Started by timer
  • Started by timer
  • Started by timer
  • Started by timer

This run spent:

  • 3 hr 24 min waiting;
  • 4 hr 25 min build duration;
  • 4 hr 26 min total from scheduled to completion.
Revision: f8837bec132947731bb9d2c87316e598d825396d
  • refs/remotes/origin/main
Revision: bd64ad3fe17506933ac2971dcc900271d6ae5969
  • refs/remotes/origin/master
Revision: fdb10180aeb7763add7215a1c068f505ede9cc17
  • refs/remotes/origin/master