Started 1 mo 3 days ago
Took 4 hr 42 min

Success Build #2478 (Jan 24, 2021 11:19:10 AM)

Changes
  1. [JITLink] Use edge kind names for fixups in EHFrameEdgeFixer. (details)
  2. [RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where the shift has guaranteed zeros. (details)
  3. [ValueTracking] Don't assume readonly function will return (details)
  4. [libomptarget][nvptx] Replace cuda atomic primitives with clang intrinsics (details)
  5. [examples] Fix "Target does not support MC emission!" in HowToUseJIT example. (details)
  6. [LoopUnroll] Use llvm.experimental.noalias.scope.decl for duplicating noalias metadata as needed (details)
  7. [LoopRotate] Use llvm.experimental.noalias.scope.decl for duplicating noalias metadata as needed (details)
  8. [InstCombine] Remove unused llvm.experimental.noalias.scope.decl (details)
  9. [AArch64] Saturating add cost tests. NFC (details)
  10. Fix x86 exegesis tests after c042aff8860df3cad2b274bf0a495e83ae36ddee (details)
  11. [SLP] fix fast-math requirements for fmin/fmax reductions (details)
  12. [LTO] Move DisableVerify setting to LTOCodeGenerator class (NFC). (details)
  13. [CostModel] Tests for showing the cost of intrinsics from the vectorizer. NFC (details)
  14. [Utils] Use NoAliasScopeDeclInst in a few more places (NFC) (details)
  15. [OpenMP] Fixed test environment of `check-libomptarget-nvptx` (details)
  16. [libomptarget][cuda] Fix build, change missed from D95274 (details)
  17. [RISCV] Use SRLIWPat in the PACKUW pattern. (details)
  18. [CodeGen] Forward-declare TargetMachine (NFC) (details)
  19. [Target] Use llvm::append_range (NFC) (details)
  20. [llvm] Use pop_back_val (NFC) (details)
  21. [lldb] Add -Wl,-rpath to make tests run with fresh built libc++ (details)
  22. Implement vAttachOrWait (details)
  23. [RISCV] Fix name of Zba extension (NFC) (details)
  24. [ARM] Extra MVE unaligned VLDn tests. NFC (details)
  25. [RISCV] Add test cases for missed opportunities to use fcvt.*.w(u) instructions on RV64 when input is known to be extended from i8/i16. (details)
  26. [RISCV] Add test cases for missed opportunities to use *W instructions for div/rem when inputs are sign/zero extended from i8/16 instead of i32. (details)
  27. [RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32. (details)
  28. [RISCV] Add support for Zvamo/Zvlsseg to driver (details)

Started by upstream project LLDB Incremental build number 27847
originally caused by:

  • Started by timer
  • Started by timer
  • Started by timer

This run spent:

  • 3 hr 36 min waiting;
  • 4 hr 42 min build duration;
  • 4 hr 42 min total from scheduled to completion.
Revision: f8837bec132947731bb9d2c87316e598d825396d
  • refs/remotes/origin/main
Revision: afd483e57d166418e94a65bd9716e7dc4c114eed
  • refs/remotes/origin/main
Revision: f8837bec132947731bb9d2c87316e598d825396d
  • refs/remotes/origin/main