SuccessChanges

Summary

  1. [clangd] Support multifile edits as output of Tweaks (details)
  2. Revert rL371198 from llvm/trunk: [DFAPacketizer] Track resources for (details)
  3. [clang-doc] sys::fs::F_None -> OF_None. NFC (details)
  4. [ARM][MVE] VCTP instruction selection (details)
  5. [clang-tidy] Fix bug in bugprone-use-after-move check (details)
  6. [Inliner][NFC] Make test less brittle. (details)
  7. [ELF] nmagic or omagic: don't allocate PT_PHDR or PF_R PT_LOAD for the (details)
  8. [DFAPacketizer] Reapply: Track resources for packetized instructions (details)
  9. compiler-rt: use fp_t instead of long double, for consistency (details)
  10. [NFC][InstCombine] Fixup test i added in rL371352. (details)
  11. [clangd] Add a new highlighting kind for typedefs (details)
  12. Merge note_ovl_builtin_candidate diagnostics; NFC (details)
  13. AMDGPU/GlobalISel: Remove dead patterns (details)
  14. [ARM] Remove some spurious MVE reduction instructions. (details)
  15. AMDGPU/GlobalISel: Try generated matcher before add/sub code (details)
  16. AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic (details)
  17. [clangd] Use pre-populated mappings for standard symbols (details)
  18. AMDGPU/GlobalISel: Use known bits for selection (details)
  19. [NFC] Add aacps bitfields access test (details)
  20. AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads (details)
  21. AMDGPU/GlobalISel: Select G_PTR_MASK (details)
  22. AMDGPU: Remove code address space predicates (details)
  23. AMDGPU/GlobalISel: Fix regbankselect for uniform extloads (details)
  24. Fix typo in comment noticed in D60295. NFCI. (details)
  25. AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant (details)
  26. LLDB - Simplify GetProgramFileSpec (details)
  27. AMDGPU/GlobalISel: Select atomic loads (details)
  28. [ARM] Fix loads and stores for predicate vectors (details)
  29. [yaml2obj] Simplify p_filesz/p_memsz computing (details)
  30. Revert "[MachineCopyPropagation] Remove redundant copies after TailDup (details)
  31. [clangd] Attempt to fix failing Windows buildbots. (details)
  32. AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC (details)
  33. AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE (details)
  34. [GlobalISel][AArch64] Handle tail calls with non-void return types (details)
  35. [SLP] add test for over-vectorization (PR33958); NFC (details)
Commit 5b270932cc6ee39d977d397bafc363e9c5df040f by kadircet
[clangd] Support multifile edits as output of Tweaks
Summary: First patch for propogating multifile changes from tweak
outputs to LSP WorkspaceEdits.
Uses SM to convert tooling::Replacements to TextEdits. Errors out if
there are any inconsistencies between the draft version and the version
generated the edits.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66637
llvm-svn: 371392
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ExtractVariable.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ExpandAutoType.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ExpandMacro.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ExtractFunction.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/SwapIfBranches.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TweakTests.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/RawStringLiteral.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Tweak.h
The file was modifiedclang-tools-extra/clangd/unittests/TweakTesting.cpp
The file was modifiedclang-tools-extra/clangd/SourceCode.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Tweak.cpp
The file was modifiedclang-tools-extra/clangd/SourceCode.h
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/AnnotateHighlightings.cpp
Commit 462e3d8050faf6442b678a9089933542b7c0e84c by llvm-dev
Revert rL371198 from llvm/trunk: [DFAPacketizer] Track resources for
packetized instructions
This patch allows the DFAPacketizer to be queried after a packet is
formed to work out which resources were allocated to the packetized
instructions.
This is particularly important for targets that do their own bundle
packing - it's not sufficient to know simply that instructions can share
a packet; which slots are used is also required for encoding.
This extends the emitter to emit a side-table containing resource usage
diffs for each state transition. The packetizer maintains a set of all
possible resource states in its current state. After packetization is
complete, all remaining resource states are possible packetization
strategies.
The sidetable is only ~500K for Hexagon, but the extra tracking is
disabled by default
(most uses of the packetizer like MachinePipeliner don't care and don't
need the extra maintained state).
Differential Revision: https://reviews.llvm.org/D66936
........ Reverted as this is causing "compiler out of heap space" errors
on MSVC 2017/19 NDEBUG builds
llvm-svn: 371393
The file was removedllvm/test/CodeGen/Hexagon/packetizer-resources.ll
The file was modifiedllvm/lib/CodeGen/DFAPacketizer.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
The file was modifiedllvm/include/llvm/CodeGen/DFAPacketizer.h
The file was modifiedllvm/utils/TableGen/DFAPacketizerEmitter.cpp
Commit ff354de2944e3082c5c2f1663c9b86c4ffabc3e3 by maskray
[clang-doc] sys::fs::F_None -> OF_None. NFC
F_None, F_Text and F_Append are kept for compatibility.
llvm-svn: 371394
The file was modifiedclang-tools-extra/clang-doc/tool/ClangDocMain.cpp
The file was modifiedclang-tools-extra/clang-doc/HTMLGenerator.cpp
Commit 1ad508e8e2d5036a6356a136ab0b02251091e2a6 by sam.parker
[ARM][MVE] VCTP instruction selection
Add codegen support for vctp{8,16,32}.
Differential Revision: https://reviews.llvm.org/D67344
llvm-svn: 371395
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was addedllvm/test/CodeGen/Thumb2/mve-vctp.ll
Commit f9ce864558ab4110233e86f6391ced320dd1e07b by yitzhakm
[clang-tidy] Fix bug in bugprone-use-after-move check
Summary: The bugprone-use-after-move check exhibits false positives for
certain uses of the C++17 if/switch init statements. These false
positives are caused by a bug in the ExprSequence calculations.
This revision adds tests for the false positives and fixes the
corresponding sequence calculation.
Reviewers: gribozavr
Subscribers: xazax.hun, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67292
llvm-svn: 371396
The file was modifiedclang-tools-extra/clang-tidy/utils/ExprSequence.cpp
The file was modifiedclang-tools-extra/test/clang-tidy/bugprone-use-after-move.cpp
Commit 388b9794b619141d4a3bba7d82b803a499d11540 by courbet
[Inliner][NFC] Make test less brittle.
Summary: This tests inlining size thresholds, but relies on the output
of running the full O2 pipeline, making it brittle against changes in
unrelated passes.
Only run the inlining pass and set thresholds on the test RUN line
instead.
Found while investigating D60318.
Reviewers: RKSimon, qcolombet
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67349
llvm-svn: 371397
The file was modifiedllvm/test/Transforms/Inline/inline_minisize.ll
Commit e8c0d933603a2ebfd535be454824219fb7b71001 by maskray
[ELF] nmagic or omagic: don't allocate PT_PHDR or PF_R PT_LOAD for the
!hasPhdrsCommands case
``` part.phdrs = script->hasPhdrsCommands() ? script->createPhdrs() :
createPhdrs(part);
```
createPhdrs() allocates a PT_PHDR and a PF_R PT_LOAD, which will be
deleted later in LinkerScript::allocateHeaders, but leave a gap between
the program headers and the first section. Don't allocate the segments
to avoid the gap. PT_INTERP is likely not needed as well.
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D67324
llvm-svn: 371398
The file was modifiedlld/test/ELF/magic-page-combo-warn.s
The file was modifiedlld/test/ELF/segments.s
The file was modifiedlld/test/ELF/relro-omagic.s
The file was modifiedlld/test/ELF/nmagic.s
The file was modifiedlld/ELF/Writer.cpp
Commit b6c7fce67add2769cb5f3e07d4a70ae09dc12836 by jmolloy
[DFAPacketizer] Reapply: Track resources for packetized instructions
Reapply with fix to reduce resources required by the compiler - use
unsigned[2] instead of std::pair. This causes clang and gcc to compile
the generated file multiple times faster, and hopefully will reduce the
resource requirements on Visual Studio also. This fix is a little ugly
but it's clearly the same issue the previous author of DFAPacketizer
faced (the previous tables use unsigned[2] rather uglily too).
This patch allows the DFAPacketizer to be queried after a packet is
formed to work out which resources were allocated to the packetized
instructions.
This is particularly important for targets that do their own bundle
packing - it's not sufficient to know simply that instructions can share
a packet; which slots are used is also required for encoding.
This extends the emitter to emit a side-table containing resource usage
diffs for each state transition. The packetizer maintains a set of all
possible resource states in its current state. After packetization is
complete, all remaining resource states are possible packetization
strategies.
The sidetable is only ~500K for Hexagon, but the extra tracking is
disabled by default
(most uses of the packetizer like MachinePipeliner don't care and don't
need the extra maintained state).
Differential Revision: https://reviews.llvm.org/D66936
llvm-svn: 371399
The file was modifiedllvm/lib/CodeGen/DFAPacketizer.cpp
The file was modifiedllvm/utils/TableGen/DFAPacketizerEmitter.cpp
The file was modifiedllvm/include/llvm/CodeGen/DFAPacketizer.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
The file was addedllvm/test/CodeGen/Hexagon/packetizer-resources.ll
Commit 1a3dd638c4a9173e53628b497a1aadc31c32eb50 by emaste
compiler-rt: use fp_t instead of long double, for consistency
Most builtins accepting or returning long double use the fp_t typedef.
Change the remaining few cases to do so.
Differential Revision: https://reviews.llvm.org/D35034
llvm-svn: 371400
The file was modifiedcompiler-rt/lib/builtins/addtf3.c
The file was modifiedcompiler-rt/lib/builtins/extendsftf2.c
The file was modifiedcompiler-rt/lib/builtins/extenddftf2.c
The file was modifiedcompiler-rt/lib/builtins/divtf3.c
Commit 59608c0049531758b9cbb3c400a68d597b797bf4 by lebedev.ri
[NFC][InstCombine] Fixup test i added in rL371352.
llvm-svn: 371401
The file was modifiedllvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
Commit e237520a8f5006692e25d7e5da7271f1c9832491 by ibiryukov
[clangd] Add a new highlighting kind for typedefs
Summary: We still attempt to highlight them as underlying types, but
fallback to the generic 'typedef' highlighting kind if the underlying
type is too complicated.
Reviewers: hokein
Reviewed By: hokein
Subscribers: nridge, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67290
llvm-svn: 371402
The file was modifiedclang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp
The file was modifiedclang-tools-extra/clangd/SemanticHighlighting.h
The file was modifiedclang-tools-extra/clangd/SemanticHighlighting.cpp
The file was modifiedclang-tools-extra/clangd/test/semantic-highlighting.test
Commit 783fc95f3eedfb44acbfc1f3f100a5eca83e7359 by sven.vanhaastregt
Merge note_ovl_builtin_candidate diagnostics; NFC
There is no difference between the unary and binary case, so merge them.
llvm-svn: 371403
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaOverload.cpp
Commit 508dff2ce15412a6b9a10a27f16d8c10b6e88c6b by Matthew.Arsenault
AMDGPU/GlobalISel: Remove dead patterns
llvm-svn: 371404
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
Commit 0e48bd24e2120e0a9fbf2bc4896266b43496df3d by simon.tatham
[ARM] Remove some spurious MVE reduction instructions.
The family of 'dual-accumulating' vector multiply-add instructions
(VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
unsigned integer types, and they all have an 'exchange' variant (with an
X in the name) that modifies which pairs of vector lanes in the two
inputs are multiplied together. But there's a clause in the spec that
says that the X variants //don't// operate on unsigned integer types,
only signed. You can have X, or unsigned, or neither, but not both.
We didn't notice that clause when we implemented the MC support for
these instructions, so LLVM believes that things like VMLADAVX.U8 do
exist, contradicting the spec. Here I fix that by conditioning them out
in Tablegen.
In order to do that, I've reversed the nesting order of the Tablegen
multiclasses for those instructions. Previously, the innermost
multiclass generated the X and not-X variants, and the one outside that
generated the A and not-A variants. Now X is done by the outer
multiclass, which allows me to bypass that one when I only want the two
not-X variants.
Changing the multiclass nesting order also changes the names of the
instruction ids unless I make a special effort not to. I decided that
while I was changing them anyway I'd make them look nicer; so now the
instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32, instead
of cumbersome _noacc_noexch suffixes.
The corresponding multiply-subtract instructions are unaffected. Those
don't accept unsigned types at all, either in the spec or in LLVM.
Reviewers: ostannard, dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67214
llvm-svn: 371405
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/test/MC/Disassembler/ARM/mve-reductions.txt
The file was modifiedllvm/test/MC/ARM/mve-reductions.s
Commit d50f937378c3cd0d763198c404687dea97e2734d by Matthew.Arsenault
AMDGPU/GlobalISel: Try generated matcher before add/sub code
This will allow optimization patterns which fold adds away to work.
llvm-svn: 371406
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 8e3bc9b572224023eb8536fe934167524ef68ecd by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic
llvm-svn: 371407
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
Commit 8b76709bac33f7edf0764416b4e5874c29f23e70 by ibiryukov
[clangd] Use pre-populated mappings for standard symbols
Summary: This takes ~5% of time when running clangd unit tests.
To achieve this, move mapping of system includes out of
CanonicalIncludes and into a separate class
Reviewers: sammccall, hokein
Reviewed By: sammccall
Subscribers: MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67172
llvm-svn: 371408
The file was modifiedclang-tools-extra/clangd/index/CanonicalIncludes.h
The file was modifiedclang-tools-extra/clangd/index/CanonicalIncludes.cpp
The file was modifiedclang-tools-extra/clangd/index/IndexAction.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CanonicalIncludesTests.cpp
The file was modifiedclang-tools-extra/clangd/ParsedAST.cpp
The file was modifiedclang-tools-extra/clangd/Preamble.cpp
Commit 2dd088ec7d8bf0804fc00e3583cb0bf10ae5c670 by Matthew.Arsenault
AMDGPU/GlobalISel: Use known bits for selection
llvm-svn: 371409
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
Commit 3c8644666c496e983d725859af61624299da67f1 by diogo.sampaio
[NFC] Add aacps bitfields access test
llvm-svn: 371410
The file was addedclang/test/CodeGen/aapcs-bitfield.c
Commit fdb70301172025ee77d3c77c28e18fd02ba5503f by Matthew.Arsenault
AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads
The pointer is always a VGPR. Also fix hardcoding the pointer size to
64.
llvm-svn: 371411
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit c34b4036ffe115c7cc03b9236922e98b78adb8b1 by Matthew.Arsenault
AMDGPU/GlobalISel: Select G_PTR_MASK
llvm-svn: 371412
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit ebbd6e49768271297d17bcecd22eae2128e24e26 by Matthew.Arsenault
AMDGPU: Remove code address space predicates
Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due to
not be reported as legal.
llvm-svn: 371413
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
Commit 02eb308387d73de035492c0ae56ce167eaa97a5f by Matthew.Arsenault
AMDGPU/GlobalISel: Fix regbankselect for uniform extloads
There are no scalar extloads.
llvm-svn: 371414
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Commit 9ede7c03956376105130421c786e1360e948b290 by llvm-dev
Fix typo in comment noticed in D60295. NFCI.
llvm-svn: 371415
The file was modifiedllvm/include/llvm/CodeGen/SwitchLoweringUtils.h
Commit d8409b178ed4b5af52eb82190b5d1c846ed8b63c by Matthew.Arsenault
AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant
loads
llvm-svn: 371416
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit f707dac742f39774aef446f275cc70f43586312a by David CARLIER
LLDB - Simplify GetProgramFileSpec
Reviewers: zturner, emaste
Reviewed By: emaste
Differential Revision: https://reviews.llvm.org/D46518
llvm-svn: 371417
The file was modifiedlldb/source/Host/freebsd/HostInfoFreeBSD.cpp
Commit 63e6d8db1cbfe75142669c55819c655c600f00a5 by Matthew.Arsenault
AMDGPU/GlobalISel: Select atomic loads
A new check for an explicitly atomic MMO is needed to avoid incorrectly
matching pattern for non-atomic loads
llvm-svn: 371418
The file was modifiedllvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
Commit 2b7089949eda508203eb23c835d6a295eb00b46b by david.green
[ARM] Fix loads and stores for predicate vectors
These predicate vectors can usually be loaded and stored with a single
instruction, a VSTR_P0. However this instruction will store the entire
P0 predicate, 16 bits, zeroextended to 32bits. Each lane of the the
v4i1/v8i1/v16i1 representing 4/2/1 bits.
As far as I understand, when llvm says "store this v4i1", it really does
need to store 4 bits (or 8, that being the size of a byte, with this
bottom 4 as the interesting bits). For example a bitcast from a v8i1 to
a i8 is defined as a store followed by a load, which is how the code is
expanded.
So this instead lowers the v4i1/v8i1 load/store through some shuffles to
get the bits into the correct positions. This, as you might imagine, is
not as efficient as a single instruction. But I believe it is needed for
correctness. v16i1 equally should not load/store 32bits, only storing
the 16bits of data. Stack loads/stores are still using the VSTR_P0 (as
can be seen by the test not changing). This is fine as they are
self-consistent, it is only "externally observable loads/stores" (from
our point of view) that need to be corrected.
Differential revision: https://reviews.llvm.org/D67085
llvm-svn: 371419
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-store.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-load.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
Commit c28f3e6e2c3ef1323ed18d4c485681bb4ff72ced by maskray
[yaml2obj] Simplify p_filesz/p_memsz computing
This fixes a bug as well. When "FileSize:" (p_filesz) is specified and
different from the actual value, the following code probably should not
use PHeader.p_filesz:
  if (SHeader->sh_offset == PHeader.p_offset + PHeader.p_filesz)
   PHeader.p_memsz += SHeader->sh_size;
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D67256
llvm-svn: 371420
The file was modifiedllvm/test/tools/yaml2obj/program-header-size-offset.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
Commit d9c4060bd5c9e6c24a96cd7e4501be30301dad9d by gribozavr
Revert "[MachineCopyPropagation] Remove redundant copies after TailDup
via machine-cp"
This reverts commit 371359. I'm suspecting a miscompile, I posted a
reproducer to https://reviews.llvm.org/D65267.
llvm-svn: 371421
The file was modifiedllvm/lib/CodeGen/MachineCopyPropagation.cpp
The file was modifiedllvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
The file was modifiedllvm/test/CodeGen/X86/mul-i512.ll
The file was modifiedllvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
Commit 6d7fba6aae28e313ba3e457ad9eff13b5e541204 by ibiryukov
[clangd] Attempt to fix failing Windows buildbots.
The assertion is failing on Windows, probably because path separator is
different.
For the failure see:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/28072/steps/test/logs/stdio
llvm-svn: 371422
The file was modifiedclang-tools-extra/clangd/index/CanonicalIncludes.cpp
Commit 182f9248e8f2c11e5aeeb08263c5b56dbf1ea9c6 by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC
Treat this as legal on gfx9 since it can use S_PACK_* instructions for
this.
This isn't used by anything yet. The same will probably apply to 16-bit
G_BUILD_VECTOR without the trunc.
llvm-svn: 371423
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector-trunc.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
Commit 64ecca90d4290f670b58111cc46e63b3aa9b72f5 by Matthew.Arsenault
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE
Handle the simple case that lowers to a constant.
llvm-svn: 371424
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-size.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
Commit bfb00e3d536e4a907f257684eba7836951677864 by Jessica Paquette
[GlobalISel][AArch64] Handle tail calls with non-void return types
Just return once you emit the call, which is exactly what SelectionDAG
does in this situation.
Update call-translator-tail-call.ll.
Also update dllimport.ll to show that we tail call here in GISel again.
Add
-verify-machineinstrs to the GISel line too, to defend against verifier
failures.
Differential revision: https://reviews.llvm.org/D67282
llvm-svn: 371425
The file was modifiedllvm/lib/Target/AArch64/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/dllimport.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
Commit c0728eac15b416206a715f4ee84e5956aa169c91 by spatel
[SLP] add test for over-vectorization (PR33958); NFC
llvm-svn: 371426
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll