SuccessChanges

Summary

  1. [LoopInterchange] Properly move condition, induction increment and ops (details)
  2. [LLDB] Do not try to canonicalize gethostname() result (details)
  3. [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' (details)
  4. Revert "clang-misexpect: Profile Guided Validation of Performance (details)
  5. [LLDB][ELF] Load both, .symtab and .dynsym sections (details)
  6. [LLDB][ELF] Fixup for comments in D67390 (details)
  7. [LoopInterchange] Drop unused splitInnerLoopHeader declaration. (details)
  8. [InstCombine] Fixed handling of isOpNewLike (PR11748) (details)
  9. [NFC] Fixed test (details)
  10. [NFC] Updated objsize-64.ll test (details)
  11. [Diagnostics] Add -Wsizeof-array-div (details)
  12. Fix -Wdocumentation warning - void function doesn't need a @returns. (details)
  13. [mips][msa] Fix infinite loop for mips.nori.b intrinsic (details)
  14. [Alignment] Use llvm::Align in MachineFunction and TargetLowering - (details)
  15. [InstCombine] fold sign-bit compares of srem (details)
  16. gn build: add include_dir that's necessary after r371564 (details)
  17. [LangRef] fix punctuation; NFC (details)
Commit e4961218fd5b9bb36810b8dc05481f29068dbbdd by flo
[LoopInterchange] Properly move condition, induction increment and ops
to latch.
Currently we only rely on the induction increment to come before the
condition to ensure the required instructions get moved to the new
latch.
This patch duplicates and moves the required instructions to the newly
created latch. We move the condition to the end of the new block, then
process its operands. We stop at operands that are defined outside the
loop, or are the induction PHI.
We duplicate the instructions and update the uses in the moved
instructions, to ensure other users remain intact. See the added test2
for such an example.
Reviewers: efriedma, mcrosier
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D67367
llvm-svn: 371595
The file was modifiedllvm/test/Transforms/LoopInterchange/phi-ordering.ll
The file was modifiedllvm/test/Transforms/LoopInterchange/interchangeable.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was modifiedllvm/test/Transforms/LoopInterchange/perserve-lcssa.ll
The file was addedllvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
The file was modifiedllvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
Commit b250d5ff5e7c5ebd9f3f5da6776ffc91cd01c614 by dave
[LLDB] Do not try to canonicalize gethostname() result
This code is trying too hard and failing. Either the result of
gethostname() is canonical or it is not. If it is not, then trying to
canonicalize it is – for various reasons – a lost cause. For example, a
given machine might have multiple network interfaces with multiple
addresses per interface, each with a different canonical name.
Separably, the result of HostInfoPosix::GetHostname() and latency
thereof shouldn't depend on whether networking is up or down or what
network the machine happened to be attached to at any given moment (like
a laptop that travels between work and home).
https://reviews.llvm.org/D67230
llvm-svn: 371596
The file was modifiedlldb/source/Host/posix/HostInfoPosix.cpp
Commit 73ec745793acdddc505610ae6a1087ada3140ef2 by diogo.sampaio
[ARM] Take into account -mcpu and -mfpu options while handling 'crypto'
feature
Submittin in behalf of krisb (Kristina Bessonova)
<ch.bessonova@gmail.com>
Summary:
'+crypto' means '+aes' and '+sha2' for arch >= ARMv8 when they were not
disabled explicitly. But this is correctly handled only in case of
'-march' option, though the feature may also be specified through the
'-mcpu' or '-mfpu' options. In the following example:
  $ clang -mcpu=cortex-a57 -mfpu=crypto-neon-fp-armv8
'aes' and 'sha2' are disabled that is quite unexpected:
  $ clang -cc1 -triple armv8--- -target-cpu cortex-a57
   <...> -target-feature -sha2 -target-feature -aes -target-feature
+crypto
This exposed by https://reviews.llvm.org/D63936 that makes the 'aes' and
'sha2' features disabled by default.
So, while handling the 'crypto' feature we need to take into account:
- a CPU name, as it provides the information about architecture
   (if no '-march' option specified),
- features, specified by the '-mcpu' and '-mfpu' options.
Reviewers: SjoerdMeijer, ostannard, labrinea, dnsampaio
Reviewed By: dnsampaio
Subscribers: ikudrin, javed.absar, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66018
Author: krisb llvm-svn: 371597
The file was modifiedclang/lib/Driver/ToolChains/Arch/ARM.cpp
The file was modifiedclang/test/Driver/arm-features.c
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
Commit 57256af307ab7bdf42c47da019a1a288b9f9451a by gribozavr
Revert "clang-misexpect: Profile Guided Validation of Performance
Annotations in LLVM"
This reverts commit r371584. It introduced a dependency from compiler-rt
to llvm/include/ADT, which is problematic for multiple reasons.
One is that it is a novel dependency edge, which needs cross-compliation
machinery for llvm/include/ADT (yes, it is true that right now
compiler-rt included only header-only libraries, however, if we allow
compiler-rt to depend on anything from ADT, other libraries will
eventually get used).
Secondly, depending on ADT from compiler-rt exposes ADT symbols from
compiler-rt, which would cause ODR violations when Clang is built with
the profile library.
llvm-svn: 371598
The file was removedclang/test/Profile/misexpect-switch-only-default-case.c
The file was removedclang/test/Profile/misexpect-switch.c
The file was removedllvm/test/Transforms/PGOProfile/Inputs/misexpect-branch.proftext
The file was removedllvm/lib/Transforms/Utils/MisExpect.cpp
The file was modifiedllvm/include/llvm/IR/DiagnosticInfo.h
The file was removedllvm/test/Transforms/PGOProfile/misexpect-branch-correct.ll
The file was modifiedllvm/lib/IR/MDBuilder.cpp
The file was removedllvm/test/Transforms/PGOProfile/misexpect-branch-unpredictable.ll
The file was modifiedclang/include/clang/Basic/DiagnosticGroups.td
The file was removedllvm/test/Transforms/PGOProfile/Inputs/misexpect-switch.proftext
The file was modifiedllvm/include/llvm/IR/MDBuilder.h
The file was modifiedllvm/lib/IR/DiagnosticInfo.cpp
The file was removedclang/test/Profile/misexpect-branch.c
The file was removedllvm/include/llvm/Transforms/Utils/MisExpect.h
The file was removedclang/test/Profile/misexpect-branch-cold.c
The file was removedllvm/test/Transforms/PGOProfile/misexpect-branch.ll
The file was removedclang/test/Profile/Inputs/misexpect-branch.proftext
The file was removedclang/test/Profile/Inputs/misexpect-switch.proftext
The file was removedclang/test/Profile/Inputs/misexpect-branch-nonconst-expect-arg.proftext
The file was removedllvm/test/Transforms/PGOProfile/misexpect-switch.ll
The file was removedllvm/test/Transforms/PGOProfile/misexpect-switch-default.ll
The file was modifiedllvm/include/llvm/IR/FixedMetadataKinds.def
The file was removedclang/test/Profile/Inputs/misexpect-switch-default-only.proftext
The file was modifiedllvm/test/ThinLTO/X86/lazyload_metadata.ll
The file was modifiedllvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
The file was removedcompiler-rt/lib/profile/xxhash.c
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedllvm/test/Transforms/LowerExpectIntrinsic/basic.ll
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
The file was removedclang/test/Profile/Inputs/misexpect-switch-default.proftext
The file was modifiedllvm/lib/Transforms/Scalar/LowerExpectIntrinsic.cpp
The file was removedclang/test/Profile/misexpect-switch-default.c
The file was removedclang/test/Profile/misexpect-switch-nonconst.c
The file was removedclang/test/Profile/misexpect-branch-unpredictable.c
The file was removedclang/test/Profile/Inputs/misexpect-switch-nonconst.proftext
The file was removedcompiler-rt/lib/profile/xxhash.h
The file was removedclang/test/Profile/misexpect-branch-nonconst-expected-val.c
The file was removedllvm/test/Transforms/PGOProfile/Inputs/misexpect-branch-correct.proftext
The file was removedllvm/test/Transforms/PGOProfile/Inputs/misexpect-switch-correct.proftext
The file was removedllvm/test/Transforms/PGOProfile/misexpect-branch-stripped.ll
The file was modifiedclang/include/clang/Basic/DiagnosticFrontendKinds.td
The file was modifiedllvm/lib/Transforms/Utils/CMakeLists.txt
Commit 3a4781bbf4f39a25562b4c61c9a9ab2483a96b41 by kkleine
[LLDB][ELF] Load both, .symtab and .dynsym sections
Summary: This change ensures that the .dynsym section will be parsed
even when there's already is a .symtab.
It is motivated because of minidebuginfo
(https://sourceware.org/gdb/current/onlinedocs/gdb/MiniDebugInfo.html#MiniDebugInfo).
There it says:
    Keep all the function symbols not already in the dynamic symbol
table.
That means the .symtab embedded inside the .gnu_debugdata does NOT
contain the symbols from .dynsym. But in order to put a breakpoint on
all symbols we need to load both. I hope this makes sense.
My other patch D66791 implements support for minidebuginfo, that's why I
need this change.
Reviewers: labath, espindola, alexshap
Subscribers: JDevlieghere, emaste, arichardson, MaskRay, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D67390
llvm-svn: 371599
The file was modifiedlldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
The file was addedlldb/lit/Modules/ELF/Inputs/load-from-dynsym-alone.c
The file was addedlldb/lit/Modules/ELF/Inputs/load-symtab-and-dynsym.c
The file was modifiedlldb/lit/helper/toolchain.py
The file was addedlldb/lit/Modules/ELF/load-symtab-and-dynsym.test
The file was addedlldb/lit/Modules/ELF/load-from-dynsym-alone.test
Commit 813f05915d29904878d926f9849ca3dbe78096af by kkleine
[LLDB][ELF] Fixup for comments in D67390
llvm-svn: 371600
The file was modifiedlldb/lit/Modules/ELF/load-symtab-and-dynsym.test
The file was modifiedlldb/lit/Modules/ELF/load-from-dynsym-alone.test
The file was modifiedlldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
Commit e79381c3f7a6da15dc632ecf02ab38805bf2761a by flo
[LoopInterchange] Drop unused splitInnerLoopHeader declaration.
llvm-svn: 371601
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
Commit 4dae283cd3e74f0ccacac14b3080a321cee740b3 by david.bolvansky
[InstCombine] Fixed handling of isOpNewLike (PR11748)
llvm-svn: 371602
The file was modifiedllvm/test/Transforms/InstCombine/deref-alloc-fns.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit 57ebb50a0ad4585976b55a81e76657cad5d27bef by david.bolvansky
[NFC] Fixed test
llvm-svn: 371603
The file was modifiedllvm/test/Transforms/InstCombine/malloc-free-delete.ll
Commit af5ba2873f5e9cd5c64d59fd3f13546815ab7fc1 by david.bolvansky
[NFC] Updated objsize-64.ll test
llvm-svn: 371604
The file was modifiedllvm/test/Transforms/InstCombine/objsize-64.ll
Commit 3240ad4ced0d3223149b72a4fc2a4d9b67589427 by david.bolvansky
[Diagnostics] Add -Wsizeof-array-div
Summary: Clang version of https://www.viva64.com/en/examples/v706/
Reviewers: rsmith
Differential Revision: https://reviews.llvm.org/D67287
llvm-svn: 371605
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was addedclang/test/Sema/div-sizeof-array.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit e0d9a0bd59d8ece9662c4ad618398ddcfec8d93f by llvm-dev
Fix -Wdocumentation warning - void function doesn't need a @returns.
NFCI.
llvm-svn: 371606
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceMetadata.cpp
Commit d811d9115b0b2d004a568e8ebdb37ba0ea6397d1 by simon
[mips][msa] Fix infinite loop for mips.nori.b intrinsic
When value of immediate in `mips.nori.b` is 255 (which has all ones in
binary form as 8bit integer) DAGCombiner and Legalizer would fall in an
infinite loop. DAGCombiner would try to simplify `or %value, -1` by
turning `%value` into UNDEF. Legalizer will turn it back into
`Constant<0>` which would then be again turned into UNDEF by
DAGCombiner. To avoid this loop we make UNDEF legal for MSA int types on
Mips.
Patch by Mirko Brkusanin.
Differential Revision: https://reviews.llvm.org/D67280
llvm-svn: 371607
The file was addedllvm/test/CodeGen/Mips/msa/nori.b.ll
The file was modifiedllvm/lib/Target/Mips/MipsSEISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
The file was modifiedllvm/test/CodeGen/Mips/cconv/vector.ll
Commit 48904e9452de81375bd55d830d08e51cc8f2ec7e by gchatelet
[Alignment] Use llvm::Align in MachineFunction and TargetLowering -
fixes mir parsing
Summary: This catches malformed mir files which specify alignment as
log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type. See
this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this
patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai,
jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook,
apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones,
atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei,
jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh6.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
The file was modifiedllvm/test/CodeGen/ARM/sched-it-debug-nodes.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir
The file was modifiedllvm/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir
The file was modifiedllvm/test/CodeGen/Mips/instverify/dextm-pos.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-sub.mir
The file was modifiedllvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir
The file was modifiedllvm/test/CodeGen/Mips/instverify/dext-pos.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/diexpr-win32.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir
The file was modifiedllvm/test/CodeGen/ARM/constant-islands-cfg.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir
The file was modifiedllvm/test/CodeGen/X86/late-remat-update.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir
The file was modifiedllvm/test/CodeGen/PowerPC/expand-isel-1.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fptosi.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
The file was modifiedllvm/lib/Target/ARM/ARMBasicBlockInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir
The file was modifiedllvm/test/CodeGen/PowerPC/expand-isel-7.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
The file was modifiedllvm/test/CodeGen/PowerPC/expand-isel-8.mir
The file was modifiedllvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
The file was modifiedllvm/test/CodeGen/PowerPC/expand-isel-3.mir
The file was modifiedllvm/test/CodeGen/Mips/instverify/dins-pos.mir
The file was modifiedllvm/test/CodeGen/Hexagon/early-if-predicator.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/legalize-add.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
The file was modifiedllvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir
The file was modifiedllvm/test/CodeGen/PowerPC/expand-isel-9.mir
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
The file was modifiedllvm/test/CodeGen/Mips/micromips-eva.mir
The file was modifiedllvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-br.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
The file was modifiedllvm/test/CodeGen/X86/conditional-tailcall-samedest.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame6.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
The file was modifiedllvm/test/CodeGen/AArch64/movimm-wzr.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
The file was modifiedllvm/test/CodeGen/SystemZ/misched-readadvances.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-block8.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-block5.mir
The file was modifiedllvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
The file was modifiedllvm/test/CodeGen/SystemZ/cond-move-05.mir
The file was modifiedllvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
The file was modifiedllvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
The file was modifiedllvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
The file was modifiedllvm/test/CodeGen/ARM/vldm-liveness.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
The file was modifiedllvm/test/CodeGen/ARM/prera-ldst-aliasing.mir
The file was modifiedllvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-cmp.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
The file was modifiedllvm/test/CodeGen/PowerPC/schedule-addi-load.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir
The file was modifiedllvm/test/DebugInfo/ARM/cfi-eof-prologue.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame2.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
The file was modifiedllvm/test/CodeGen/X86/pre-coalesce.mir
The file was modifiedllvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
The file was modifiedllvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh1.mir
The file was modifiedllvm/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir
The file was modifiedllvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
The file was modifiedllvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
The file was modifiedllvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir
The file was modifiedllvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir
The file was modifiedllvm/lib/CodeGen/MIRParser/MIRParser.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
The file was modifiedllvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir
The file was modifiedllvm/test/DebugInfo/X86/live-debug-vars-dse.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
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Commit 80bea345d11912c6473797fcea0866a7f0ca9cca by spatel
[InstCombine] fold sign-bit compares of srem
(srem X, pow2C) sgt/slt 0 can be reduced using bit hacks by masking off
the sign bit and the module (low) bits: https://rise4fun.com/Alive/jSO A
'2' divisor allows slightly more folding:
https://rise4fun.com/Alive/tDBM
Any chance to remove an 'srem' use is probably worthwhile, but this is
limited to the one-use improvement case because doing more may expose
other missing folds. That means it does nothing for PR21929 yet:
https://bugs.llvm.org/show_bug.cgi?id=21929
Differential Revision: https://reviews.llvm.org/D67334
llvm-svn: 371610
The file was modifiedllvm/test/Transforms/InstCombine/icmp-div-constant.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Commit f78474ba8aeb72fe30aced2077b0ef31bc0b8326 by nicolasweber
gn build: add include_dir that's necessary after r371564
llvm-svn: 371611
The file was modifiedllvm/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
Commit b3b2064c5180d0b9cec95e6933c04b54e74dbebc by spatel
[LangRef] fix punctuation; NFC
llvm-svn: 371612
The file was modifiedllvm/docs/LangRef.rst