Commit
1d2cd2c0b7d978e22a50e918af708ba67e87c2c1
by maskray[Driver] Fix OptionClass of -fconvergent-functions and -fms-volatile (Joined -> Flag)
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 | clang/include/clang/Driver/Options.td |
Commit
9b23407063ca41901e9e272bacf8b33eee8251c4
by saar[Concepts] Fix MarkUsedTemplateParameters for exprs D41910 introduced a recursive visitor to MarkUsedTemplateParameters, but disregarded the 'Depth' parameter, and had incorrect assertions. This fixes the visitor and removes the assertions.
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 | clang/lib/Sema/SemaTemplateDeduction.cpp |
Commit
de0a2247115729eade8249267a47f96f070a7666
by alexandre.ganeaRemove umask tests These tests were added in 18627115f4d2db5dc73207e0b5312f52536be7dd and e08b59f81d950bd5c8b8528fcb3ac4230c7b736c for validating a refactoring. Removing because they break on ACL-controlled folders on Ubuntu, and their added value is low. Differential Revision: https://reviews.llvm.org/D70854
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 | llvm/test/Other/umask.ll |
 | clang/test/Misc/permissions.cpp |
Commit
7c816492197aefbaa2ea3ba0e391f7c6905956bc
by Tom.Tan[COFF] Align ARM64 range extension thunks at instruction boundary RangeExtensionThunkARM64 is created for out-of-range branches on Windows ARM64 because branch instructions has limited bits to encode target address. Currently, RangeExtensionThunkARM64 is appended to its referencing COFF section from object file at link time without any alignment requirement, so if size of the preceding COFF section is not aligned to instruction boundary (4 bytes), RangeExtensionThunkARM64 will emit thunk instructions at unaligned address which is never a valid branch target on ARM64, and usually triggers invalid instruction exception when branching to it. This PR fixes it by requiring such thunks to align at 4 bytes. Differential revision: https://reviews.llvm.org/D72473
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 | lld/test/COFF/arm64-thunks.s |
 | lld/COFF/Chunks.h |
Commit
bb2553175ac3cc6223ff379b266ee1c23a468d66
by craig.topper[TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare from RunttimeLibcalls.def and all associated usages Summary: This always just used the same libcall as unordered, but the comparison predicate was different. This change appears to have been made when targets were given the ability to override the predicates. Before that they were hardcoded into the type legalizer. At that time we never inverted predicates and we handled ugt/ult/uge/ule compares by emitting an unordered check ORed with a ogt/olt/oge/ole checks. So only ordered needed an inverted predicate. Later ugt/ult/uge/ule were optimized to only call a single libcall and invert the compare. This patch removes the ordered entries and just uses the inverting logic that is now present. This removes some odd things in both the Mips and WebAssembly code. Reviewers: efriedma, ABataev, uweigand, cameron.mcinally, kpn Reviewed By: efriedma Subscribers: dschuff, sdardis, sbc100, arichardson, jgravelle-google, kristof.beyls, hiraditya, aheejin, sunfish, atanasyan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72536
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 | llvm/lib/Target/Mips/Mips16ISelLowering.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp |
 | llvm/lib/CodeGen/TargetLoweringBase.cpp |
 | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
 | llvm/lib/Target/ARM/ARMISelLowering.cpp |
 | llvm/include/llvm/IR/RuntimeLibcalls.def |
 | llvm/lib/Target/ARM/ARMLegalizerInfo.cpp |
Commit
a701be8f036accef9a3dab62fa4baa70ea330a80
by czhengsz[SCEV] [NFC] add more test cases for range of addrecexpr with nsw flag
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 | llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll |
Commit
4134d706d9bc48d1634e0d95a5c1698f5fcfd06e
by qiucofan[NFC] [PowerPC] Update mi-peephole-splat test Use script to re-generate the test case, for easier comparison with future patches.
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 | llvm/test/CodeGen/PowerPC/mi-peephole-splat.ll |
Commit
4a32cd11acd7c38f5e0b587d724935ab7a9938a6
by mjbedy[AMDGPU] Remove unnecessary v_mov from a register to itself in WQM lowering. Summary: - SI Whole Quad Mode phase is replacing WQM pseudo instructions with v_mov instructions. While this is necessary for the special handling of moving results out of WWM live ranges, it is not necessary for WQM live ranges. The result is a v_mov from a register to itself after every WQM operation. This change uses a COPY psuedo in these cases, which allows the register allocator to coalesce the moves away. Reviewers: tpr, dstuttard, foad, nhaehnle Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71386
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 | llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp |
 | llvm/test/CodeGen/AMDGPU/wqm.mir |
 | llvm/test/CodeGen/AMDGPU/wqm.ll |
Commit
695804508db048fe3403f2b8bc690633a471a40b
by Amara EmersonMark the test/Feature/load_extension.ll test as unsupported on Darwin. With plugins and examples enabled, this XPASSes. Mark it as unsupported until the owner investigates what's going on.
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 | llvm/test/Feature/load_extension.ll |
Commit
69806808b918adc9b24bee05654b1d6dad91ef74
by craig.topper[X86] Use ReplaceAllUsesWith instead of ReplaceAllUsesOfValueWith to simplify some code. NFCI
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 | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp |
Commit
fcad5b298c7859d7f10908fab7b82983e286bb8d
by maskray[X86][Disassembler] Simplify readPrefixes
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 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp |
Commit
5fe5c0a60f9a5f32da4316ba0d1732a1e439703b
by craig.topper[X86] Preserve fpexcept property when turning strict_fp_extend and strict_fp_round into stack operations. We use the stack for X87 fp_round and for moving from SSE f32/f64 to X87 f64/f80. Or from X87 f64/f80 to SSE f32/f64. Note for the SSE<->X87 conversions the conversion always happens in the X87 domain. The load/store ops in the X87 instructions are able to signal exceptions.
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 | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp |
 | llvm/lib/Target/X86/X86InstrFPStack.td |
Commit
c2ddfa876fa90008f1b4ff611256ad5dd4b36d96
by craig.topper[X86] Simplify code by removing an unreachable condition. NFCI For X87<->SSE conversions, the SSE type is always smaller than the X87 type. So we can always use the smallest type for the memory type.
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 | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp |
Commit
60346bdbd73da9c944d50ea5dcecad71a05105ac
by csiggAdd test for GDB pretty printers. Reviewers: dblaikie, aprantl, davide, JDevlieghere Reviewed By: aprantl Subscribers: jmorse, aprantl, merge_guards_bot, mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72321
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 | debuginfo-tests/llvm-prettyprinters/gdb/lit.local.cfg |
 | debuginfo-tests/llvm-prettyprinters/gdb/prettyprinters.cpp |
 | debuginfo-tests/CMakeLists.txt |
 | debuginfo-tests/lit.cfg.py |
 | debuginfo-tests/llvm-prettyprinters/gdb/prettyprinters.gdb |
Commit
81a3d987ced0905bef2e3055bf77ec174bb631c7
by craig.topper[X86] Remove dead code from X86DAGToDAGISel::Select that is no longer needed now that we don't mutate strict fp nodes. NFC
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 | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp |
Commit
0e322c8a1f20ab04ce4f6bc538846859707f2d69
by nikita.ppv[InstCombine] Preserve nuw on sub of geps (PR44419) Fix https://bugs.llvm.org/show_bug.cgi?id=44419 by preserving the nuw on sub of geps. We only do this if the offset has a multiplication as the final operation, as we can't be sure the operations is nuw in the other cases without more thorough analysis. Differential Revision: https://reviews.llvm.org/D72048
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 | llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp |
 | llvm/lib/Transforms/InstCombine/InstCombineInternal.h |
 | llvm/test/Transforms/InstCombine/sub-gep.ll |
Commit
ad36d29eaed62e33eabab8ffd2006b9ff5fbd719
by nikita.ppv[LoopSimplify] Regenerate test checks; NFC For D72519.
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 | llvm/test/Transforms/LoopSimplify/basictest.ll |
Commit
142ba7d76af4a66037fd180db371da19f35ef5f3
by nikita.ppv[LoopRotate] Add tests for rotate with switch; NFC For D72420.
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 | llvm/test/Transforms/LoopRotate/switch.ll |
Commit
87407fc03c82d880cc42330a8e230e7a48174e3c
by nunoplopesDSE: fix bug where we would only check libcalls for name rather than whole decl
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 | llvm/test/Transforms/DeadStoreElimination/libcalls.ll |
 | llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp |
 | llvm/test/Transforms/DeadStoreElimination/libcalls2.ll |
Commit
5d069f4314a0d8b124a563e61d161c3c3d3b0536
by flo[X86] Add more complex tests for vector masks used with AND/OR/XOR. Additional test cases for D72524.
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 | llvm/test/CodeGen/X86/v8i1-masks.ll |
Commit
ce35010d782cb5a69102ad7785eb747f6d747eb4
by llvm-dev[X86][AVX] Add lowerShuffleAsLanePermuteAndSHUFP lowering Add initial support for lowering v4f64 shuffles to SHUFPD(VPERM2F128(V1, V2), VPERM2F128(V1, V2)), eventually this could be used for v8f32 (and maybe v8f64/v16f32) but I'm being conservative for the initial implementation as only v4f64 can always succeed. This currently is only called from lowerShuffleAsLanePermuteAndShuffle so only gets used for unary shuffles, and we limit this to cases where we use upper elements as otherwise concating 2 xmm shuffles is probably the better case. Helps with poor shuffles mentioned in D66004.
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 | llvm/lib/Target/X86/X86ISelLowering.cpp |
 | llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll |
 | llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll |
Commit
08275a52d83e623f0347fd9396c18f4d21a15c90
by llvm-devFix copy+paste typo in shuffle test name
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 | llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll |
Commit
9c74fb402e1b7aad4a509a49ab4792154b8ba2c8
by koraq[Sema] Improve -Wrange-loop-analysis warnings. No longer generate a diagnostic when a small trivially copyable type is used without a reference. Before the test looked for a POD type and had no size restriction. Since the range-based for loop is only available in C++11 and POD types are trivially copyable in C++11 it's not required to test for a POD type. Since copying a large object will be expensive its size has been restricted. 64 bytes is a common size of a cache line and if the object is aligned the copy will be cheap. No performance impact testing has been done. Differential Revision: https://reviews.llvm.org/D72212
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 | clang/test/SemaCXX/warn-range-loop-analysis.cpp |
 | clang/lib/Sema/SemaStmt.cpp |
 | clang/test/SemaCXX/warn-range-loop-analysis-trivially-copyable.cpp |
Commit
24763734e7f45e3b60118b28987685d42e7a761f
by llvm-dev[X86] Fix outdated comment The generic saturated math opcodes are no longer widened inside X86TargetLowering
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 | llvm/lib/Target/X86/X86ISelLowering.cpp |
Commit
a8ed86b5c705cf1d2f3ca55b0640cf0f2fe01abc
by llvm-devmoveOperands - assert Src/Dst MachineOperands are non-null. Fixes static-analyzer warnings.
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 | llvm/lib/CodeGen/MachineInstr.cpp |
Commit
7c7ca515837305f5d14033aee1191c254b86063c
by benny.kraRemove copy ctors identical to the default one. NFC. Those do nothing but make the type no longer trivial to the compiler.
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 | mlir/include/mlir/IR/AffineExpr.h |
 | mlir/include/mlir/IR/AffineMap.h |
 | mlir/include/mlir/IR/IntegerSet.h |
Commit
2740b2d5d5f0f56c87024555bdcae4f91e595ddb
by llvm-devFix uninitialized value clang static analyzer warning. NFC.
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 | llvm/lib/Transforms/Utils/CodeExtractor.cpp |
Commit
ded237b58d56299f90ef44853ef79b039248b85e
by llvm-devFix "pointer is null" static analyzer warning. NFCI. Use castAs<> instead of getAs<> since the pointer is dereferenced immediately below and castAs will perform the null assertion for us.
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 | clang/lib/Sema/SemaDecl.cpp |
Commit
16c53ffcb9d040f0396bf1ab42ca366f7e1f1e4d
by llvm-devFix "pointer is null" static analyzer warnings. NFCI. Use castAs<> instead of getAs<> since the pointer is dereferenced immediately below and castAs will perform the null assertion for us.
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 | clang/lib/CodeGen/CGExprCXX.cpp |
 | clang/lib/CodeGen/CGExpr.cpp |
 | clang/lib/CodeGen/CGExprScalar.cpp |
Commit
d87a76c9dae38b2a1ef63584aee82e74490dc83b
by llvm-devFix "pointer is null" static analyzer warning. NFCI. Use castAs<> instead of getAs<> since the pointer is dereferenced immediately within mangleCallingConvention and castAs will perform the null assertion for us.
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 | clang/lib/AST/MicrosoftMangle.cpp |
Commit
93431f96a7b14ff03036bae77cc0197fdc98ad52
by llvm-devFix "pointer is null" static analyzer warning. NFCI. Use cast<> instead of dyn_cast<> since we know that the pointer should be valid (and is dereferenced immediately).
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 | clang/lib/CodeGen/CGStmtOpenMP.cpp |
Commit
bf03944d5d9a7e7c8105c69dfa0d7e0d345644df
by llvm-devFix "pointer is null" static analyzer warnings. NFCI. Use castAs<> instead of getAs<> since the pointers are dereferenced immediately and castAs will perform the null assertion for us.
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 | clang/lib/Sema/SemaCodeComplete.cpp |
Commit
fce887beb79780d0e0b19e8ab6176978a3dce9b8
by llvm-devGlobalModuleIndex - Fix use-after-move clang static analyzer warning. Shadow variable names meant we were referencing the Buffer input argument, not the GlobalModuleIndex member that its std::move()'d it.
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 | clang/lib/Serialization/GlobalModuleIndex.cpp |
Commit
6cb3957730e9085bb7c37d871c790f910efdd6a7
by listmail[X86AsmBackend] Be consistent about placing definitions out of line [NFC]
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 | llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp |
Commit
563d3e344452c8923db09b043b8db471fc413b1e
by listmail[X86AsmBackend] Move static function before sole use [NFC]
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 | llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp |
Commit
1d641daf260308815d014d1bf1b424a1ed1e7277
by listmail[X86] Adjust nop emission by compiler to consider target decode limitations The primary motivation of this change is to bring the code more closely in sync behavior wise with the assembler's version of nop emission. I'd like to eventually factor them into one, but that's hard to do when one has features the other doesn't. The longest encodeable nop on x86 is 15 bytes, but many processors - for instance all intel chips - can't decode the 15 byte form efficiently. On those processors, it's better to use either a 10 byte or 11 byte sequence depending.
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 | llvm/test/MC/X86/stackmap-nops.ll |
 | llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll |
 | llvm/lib/Target/X86/X86MCInstLower.cpp |
 | llvm/test/CodeGen/X86/stackmap-nops.ll |
Commit
2bdf33cc4c733342fc83081bc7410ac5e9a24f55
by riverriddle[mlir] NFC: Remove Value::operator* and Value::operator-> now that Value is properly value-typed. Summary: These were temporary methods used to simplify the transition. Reviewed By: antiagainst Differential Revision: https://reviews.llvm.org/D72548
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 | mlir/lib/IR/Builders.cpp |
 | mlir/include/mlir/Dialect/Linalg/EDSC/Builders.h |
 | mlir/include/mlir/Quantizer/Support/ConstraintAnalysisGraph.h |
 | mlir/examples/toy/Ch3/mlir/ToyCombine.td |
 | mlir/lib/IR/AsmPrinter.cpp |
 | mlir/lib/Transforms/Utils/Utils.cpp |
 | mlir/lib/Transforms/Utils/FoldUtils.cpp |
 | mlir/lib/Transforms/Utils/LoopFusionUtils.cpp |
 | mlir/docs/Tutorials/Toy/Ch-4.md |
 | mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td |
 | mlir/examples/toy/Ch6/mlir/ToyCombine.td |
 | mlir/lib/Analysis/Utils.cpp |
 | mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h |
 | mlir/include/mlir/Dialect/QuantOps/QuantOps.td |
 | mlir/include/mlir/Dialect/StandardOps/Ops.h |
 | mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp |
 | mlir/include/mlir/Dialect/Linalg/Utils/Utils.h |
 | mlir/lib/IR/Value.cpp |
 | mlir/include/mlir/IR/Matchers.h |
 | mlir/include/mlir/IR/OpDefinition.h |
 | mlir/lib/Parser/Parser.cpp |
 | mlir/include/mlir/Dialect/Linalg/Transforms/LinalgTransformPatterns.td |
 | mlir/include/mlir/EDSC/Intrinsics.h |
 | mlir/include/mlir/Analysis/Dominance.h |
 | mlir/include/mlir/Dialect/VectorOps/VectorTransformPatterns.td |
 | mlir/lib/Transforms/Utils/InliningUtils.cpp |
 | mlir/lib/Transforms/Vectorize.cpp |
 | mlir/examples/toy/Ch5/mlir/ToyCombine.cpp |
 | mlir/lib/Transforms/LoopInvariantCodeMotion.cpp |
 | mlir/examples/toy/Ch7/mlir/ToyCombine.cpp |
 | mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp |
 | mlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp |
 | mlir/lib/Transforms/LoopTiling.cpp |
 | mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp |
 | mlir/lib/Dialect/GPU/IR/GPUDialect.cpp |
 | mlir/lib/Analysis/LoopAnalysis.cpp |
 | mlir/include/mlir/Dialect/AffineOps/AffineOps.h |
 | mlir/test/lib/TestDialect/TestOps.td |
 | mlir/lib/Transforms/AffineLoopInvariantCodeMotion.cpp |
 | mlir/lib/Conversion/GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp |
 | mlir/docs/Tutorials/Toy/Ch-3.md |
 | mlir/examples/toy/Ch5/mlir/Dialect.cpp |
 | mlir/lib/Dialect/Linalg/Utils/Utils.cpp |
 | mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp |
 | mlir/lib/Transforms/LoopUnrollAndJam.cpp |
 | mlir/include/mlir/Dialect/AffineOps/AffineOps.td |
 | mlir/examples/toy/Ch4/mlir/Dialect.cpp |
 | mlir/lib/Dialect/VectorOps/VectorOps.cpp |
 | mlir/include/mlir/IR/Value.h |
 | mlir/tools/mlir-tblgen/RewriterGen.cpp |
 | mlir/examples/toy/Ch4/mlir/ToyCombine.cpp |
 | mlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp |
 | mlir/include/mlir/IR/OpImplementation.h |
 | mlir/examples/toy/Ch5/mlir/ToyCombine.td |
 | mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp |
 | mlir/lib/IR/PatternMatch.cpp |
 | mlir/lib/EDSC/Helpers.cpp |
 | mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp |
 | mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp |
 | mlir/lib/Analysis/SliceAnalysis.cpp |
 | mlir/examples/toy/Ch7/mlir/ToyCombine.td |
 | mlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp |
 | mlir/lib/IR/Block.cpp |
 | mlir/lib/Quantizer/Support/ConstraintAnalysisGraph.cpp |
 | mlir/lib/Target/LLVMIR/ModuleTranslation.cpp |
 | mlir/examples/toy/Ch4/mlir/ToyCombine.td |
 | mlir/lib/Transforms/Utils/RegionUtils.cpp |
 | mlir/lib/Analysis/VectorAnalysis.cpp |
 | mlir/lib/Analysis/AffineAnalysis.cpp |
 | mlir/lib/Dialect/QuantOps/IR/QuantOps.cpp |
 | mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td |
 | mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td |
 | mlir/lib/Analysis/AffineStructures.cpp |
 | mlir/lib/IR/Function.cpp |
 | mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp |
 | mlir/examples/toy/Ch6/mlir/ToyCombine.cpp |
 | mlir/lib/Dialect/QuantOps/Transforms/ConvertConst.cpp |
 | mlir/include/mlir/Dialect/VectorOps/VectorOps.td |
 | mlir/include/mlir/IR/OpBase.td |
 | mlir/lib/Dialect/StandardOps/Ops.cpp |
 | mlir/lib/Dialect/FxpMathOps/Transforms/UniformKernelUtils.h |
 | mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp |
 | mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp |
 | mlir/test/lib/Transforms/TestVectorizationUtils.cpp |
 | mlir/lib/Analysis/Liveness.cpp |
 | mlir/lib/Analysis/Verifier.cpp |
 | mlir/lib/Dialect/SPIRV/SPIRVOps.cpp |
 | mlir/lib/Dialect/Traits.cpp |
 | mlir/examples/toy/Ch2/mlir/Dialect.cpp |
 | mlir/lib/Quantizer/Transforms/AddDefaultStatsTestPass.cpp |
 | mlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp |
 | mlir/test/mlir-tblgen/op-result.td |
 | mlir/lib/Dialect/AffineOps/AffineOps.cpp |
 | mlir/test/lib/Transforms/TestInlining.cpp |
 | mlir/lib/IR/Operation.cpp |
 | mlir/lib/Analysis/Dominance.cpp |
 | mlir/docs/DeclarativeRewrites.md |
 | mlir/examples/toy/Ch3/mlir/ToyCombine.cpp |
 | mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp |
 | mlir/lib/Analysis/CallGraph.cpp |
 | mlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp |
 | mlir/examples/toy/Ch6/mlir/Dialect.cpp |
 | mlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h |
 | mlir/lib/Transforms/MemRefDataFlowOpt.cpp |
 | mlir/lib/Dialect/Linalg/EDSC/Builders.cpp |
 | mlir/lib/Quantizer/Configurations/FxpMathConfig.cpp |
 | mlir/lib/IR/TypeUtilities.cpp |
 | mlir/lib/Transforms/Utils/LoopUtils.cpp |
 | mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp |
 | mlir/include/mlir/EDSC/Builders.h |
 | mlir/docs/QuickstartRewrites.md |
 | mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp |
 | mlir/test/mlir-tblgen/predicate.td |
 | mlir/docs/OpDefinitions.md |
 | mlir/lib/EDSC/Builders.cpp |
 | mlir/lib/Transforms/DialectConversion.cpp |
 | mlir/include/mlir/Transforms/RegionUtils.h |
 | mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp |
 | mlir/test/lib/TestDialect/TestPatterns.cpp |
 | mlir/examples/toy/Ch7/mlir/Dialect.cpp |
 | mlir/lib/Dialect/SPIRV/Transforms/DecorateSPIRVCompositeTypeLayoutPass.cpp |
 | mlir/include/mlir/Dialect/StandardOps/Ops.td |
 | mlir/lib/IR/Region.cpp |
 | mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp |
 | mlir/examples/toy/Ch7/mlir/MLIRGen.cpp |
 | mlir/examples/toy/Ch3/mlir/Dialect.cpp |
 | mlir/include/mlir/IR/Operation.h |
 | mlir/lib/Dialect/VectorOps/VectorTransforms.cpp |
 | mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp |
 | mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp |
 | mlir/lib/Dialect/LoopOps/LoopOps.cpp |
 | mlir/test/lib/TestDialect/TestDialect.cpp |
 | mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp |
 | mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp |
 | mlir/lib/Dialect/Linalg/Transforms/LinalgTransforms.cpp |
 | mlir/lib/Transforms/LoopFusion.cpp |
 | mlir/lib/Transforms/PipelineDataTransfer.cpp |
 | mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp |
Commit
4c48ea68e491cb42f1b5d43ffba89f6a7f0dadc4
by development[ASTMatchers] extract public matchers from const-analysis into own patch Summary: The analysis for const-ness of local variables required a view generally useful matchers that are extracted into its own patch. They are `decompositionDecl` and `forEachArgumentWithParamType`, that works for calls through function pointers as well. Reviewers: aaron.ballman Reviewed By: aaron.ballman Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D72505
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 | clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp |
 | clang/lib/ASTMatchers/Dynamic/Registry.cpp |
 | clang/docs/LibASTMatchersReference.html |
 | clang/include/clang/ASTMatchers/ASTMatchers.h |
Commit
23a799adf0abbe9a7be1494d5efd1ab3215ee4fb
by developmentRevert "[ASTMatchers] extract public matchers from const-analysis into own patch" This reverts commit 4c48ea68e491cb42f1b5d43ffba89f6a7f0dadc4. The powerpc buildbots had an internal compiler error after this patch. This requires some inspection.
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 | clang/docs/LibASTMatchersReference.html |
 | clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp |
 | clang/include/clang/ASTMatchers/ASTMatchers.h |
 | clang/lib/ASTMatchers/Dynamic/Registry.cpp |
Commit
d2751f8fdf6c072045bab62f6035511e028f46ee
by Lang Hames[ExecutionEngine] Re-enable FastISel for non-iOS arm targets. Patch by Nicolas Capens. Thanks Nicolas! https://reviews.llvm.org/D65015
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 | llvm/lib/ExecutionEngine/TargetSelect.cpp |
Commit
dc422e968e73790178e500f506e8fb7cfa1e62ea
by koraqAdd -Wrange-loop-analysis changes to ReleaseNotes This reflects the recent changes done.
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 | clang/docs/ReleaseNotes.rst |
Commit
9cc9120969fd9f7f6a99321c7d94133a32927a3a
by craig.topper[X86] Turn FP_ROUND/STRICT_FP_ROUND into X86ISD::VFPROUND/STRICT_VFPROUND during PreprocessISelDAG to remove some duplicate isel patterns.
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 | llvm/lib/Target/X86/X86InstrAVX512.td |
 | llvm/lib/Target/X86/X86InstrSSE.td |
 | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp |
Commit
a5994c789a2982a770254ae1607b5b4cb641f73c
by maskray[X86][Disassembler] Simplify and optimize reader functions llvm-objdump -d on clang is decreased from 8.2s to 7.8s.
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 | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp |
 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp |
 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h |
Commit
9fe6f36c1a909e381275f897b780a9c878fab94a
by craig.topper[LegalizeVectorOps] Only pass SDNode* instead SDValue to all of the Expand* and Promote* methods. All the Expand* and Promote* function assume they are being called with result 0 anyway. Just hardcode result 0 into them.
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 | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp |
Commit
5a9954c02a7d6e60da26b2feec0837695846aeed
by craig.topper[LegalizeVectorOps] Remove some of the simpler Expand methods. Pass Results vector to a couple. NFCI Some of the simplest handlers just call TLI and if that fails, they fall back to unrolling. For those just inline the TLI call and share the unrolling call with the default case of Expand. For ExpandFSUB and ExpandBITREVERSE so that its obvious they don't return results sometimes and want to defer to LegalizeDAG.
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 | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp |
Commit
179abb091d8a1d67115d21b54001d10250756042
by maskray[X86][Disassembler] Replace custom logger with LLVM_DEBUG llvm-objdump -d on clang is decreased from 7.8s to 7.4s. The improvement is likely due to the elimination of logger setup and dbgprintf(), which has a large overhead.
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 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h |
 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp |
 | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp |
Commit
a1f16998f371870ca4da8b3c00a093c607a36ddd
by alexandre.ganea[Support] Optionally call signal handlers when a function wrapped by the the CrashRecoveryContext fails This patch allows for handling a failure inside a CrashRecoveryContext in the same way as the global exception/signal handler. A failure will have the same side-effect, such as cleanup of temporarty file, printing callstack, calling relevant signal handlers, and finally returning an exception code. This is an optional feature, disabled by default. This is a support patch for D69825. Differential Revision: https://reviews.llvm.org/D70568
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 | llvm/include/llvm/Support/Signals.h |
 | llvm/unittests/Support/CrashRecoveryTest.cpp |
 | llvm/lib/Support/CrashRecoveryContext.cpp |
 | llvm/include/llvm/Support/CrashRecoveryContext.h |
 | llvm/lib/Support/Windows/Signals.inc |
 | llvm/lib/Support/Unix/Signals.inc |
Commit
2cdb18afda841392002feafda21af31854c195b3
by Lang Hames[ORC] Fix argv handling in runAsMain / lli. This fixes an off-by-one error in the argc value computed by runAsMain, and switches lli back to using the input bitcode (rather than the string "lli") as the effective program name. Thanks to Stefan Graenitz for spotting the bug.
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 | llvm/test/ExecutionEngine/OrcLazy/printargv.ll |
 | llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp |
 | llvm/tools/lli/lli.cpp |
Commit
6fdd6a7b3f696972edc244488f59532d05136a27
by maskray[Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction() The argument is llvm::null() everywhere except llvm::errs() in llvm-objdump in -DLLVM_ENABLE_ASSERTIONS=On builds. It is used by no target but X86 in -DLLVM_ENABLE_ASSERTIONS=On builds. If we ever have the needs to add verbose log to disassemblers, we can record log with a member function, instead of passing it around as an argument.
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 | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h |
 | llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp |
 | llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h |
 | llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp |
 | llvm/tools/llvm-objdump/llvm-objdump.cpp |
 | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp |
 | llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h |
 | llvm/lib/MC/MCDisassembler/Disassembler.cpp |
 | llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp |
 | llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp |
 | llvm/tools/llvm-objdump/MachODump.cpp |
 | llvm/tools/llvm-exegesis/lib/Analysis.cpp |
 | llvm/lib/MC/MCDisassembler/MCDisassembler.cpp |
 | llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp |
 | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp |
 | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp |
 | lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp |
 | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp |
 | llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp |
 | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp |
 | lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp |
 | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h |
 | llvm/tools/sancov/sancov.cpp |
 | llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp |
 | lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp |
 | llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp |
 | llvm/tools/llvm-mc/Disassembler.cpp |
 | llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp |
 | llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp |
 | llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp |
 | llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp |
 | llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp |
 | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp |
Commit
1e8ce7492e91aa6db269334d12187c7ae854dccb
by maskray[X86][Disassembler] Optimize argument passing and immediate reading
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 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp |
 | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp |
 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h |
Commit
f719c540bb09cb5bfe37bc6283ea68e31949b3f4
by maskray[X86][Disassembler] Shrink X86GenDisassemblerTables.inc from 36M to 6.1M In x86Disassembler{OneByte,TwoByte,...}Codes, "/* EmptyTable */" is very common. Omitting it saves lots of space. Also, there is no need to display a table entry in multiple lines. It is also common that the whole OpcodeDecision is { MODRM_ONEENTRY, 0}. Make use of zero-initialization.
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 | llvm/utils/TableGen/X86DisassemblerTables.cpp |
Commit
ddfcd82bdc219dd2dc04d6826c417cea3da65d12
by craig.topper[LegalizeVectorOps] Expand vector MERGE_VALUES immediately. Custom legalization can produce MERGE_VALUES to return multiple results. We can expand them immediately instead of leaving them around for DAG combine to clean up.
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 | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp |
Commit
ed679804d5e34dcb1046c5087acaf5d1dbb9b582
by craig.topper[TargetLowering][X86] Connect the chain from STRICT_FSETCC in TargetLowering::expandFP_TO_UINT and X86TargetLowering::FP_TO_INTHelper.
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 | llvm/lib/Target/X86/X86ISelLowering.cpp |
 | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
Commit
efb674ac2f2b0f06adc3f00df3134dadf1c875df
by craig.topper[LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UINT_TO_FLOAT legalization. The lo and hi computation are independent. Give them the same input chain and TokenFactor the results together.
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 | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp |
Commit
569ccfc384a5434c35c09adba8c44c46014297e6
by czhengsz[SCEV] more accurate range for addrecexpr with nsw flag. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D72436
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 | llvm/lib/Analysis/ScalarEvolution.cpp |
 | llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll |
Commit
d692f0f6c8c12316d559b9a638a2cb9fbd0c263d
by craig.topper[X86] Don't call LowerSETCC from LowerSELECT for STRICT_FSETCC/STRICT_FSETCCS nodes. This causes the STRICT_FSETCC/STRICT_FSETCCS nodes to lowered early while lowering SELECT, but the output chain doesn't get connected. Then we visit the node again when it is its turn because we haven't replaced the use of the chain result. In the case of the fp128 libcall lowering, after D72341 this will cause the libcall to be emitted twice.
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 | llvm/lib/Target/X86/X86ISelLowering.cpp |
Commit
f33fd43a7c91f1774a9512bbdb78c367cd23d233
by qiucofan[NFC] Refactor memory ops cluster method Current implementation of BaseMemOpsClusterMutation is a little bit obscure. This patch directly uses a map from store chain ID to set of memory instrs to make it simpler, so that future improvements are easier to read, update and review. Reviewed By: evandro Differential Revision: https://reviews.llvm.org/D72070
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 | llvm/lib/CodeGen/MachineScheduler.cpp |
Commit
c5b94ea265133a4a28006929643155fc8fbeafe6
by maskray[profile] Support merge pool size >= 10 The executable acquires an advisory record lock (`fcntl(fd, F_SETLKW, *)`) on a profile file. Merge pool size >= 10 may be beneficial when the concurrency is large. Also fix a small problem about snprintf. It can cause the filename to be truncated after %m. Reviewed By: davidxl Differential Revision: https://reviews.llvm.org/D71970
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 | compiler-rt/test/profile/instrprof-basic.c |
 | compiler-rt/lib/profile/InstrProfilingFile.c |
Commit
51c1d7c4bec025f70679284060b82c05242759b2
by maskray[X86][Disassembler] Simplify
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 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h |
 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp |
 | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp |
Commit
60cc095ecc34d72a9ac6947f39c6e2a0cdf5449f
by maskray[X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X86Disassembler.cpp and refactor
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 | llvm/lib/Target/X86/Disassembler/CMakeLists.txt |
 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp |
 | llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h |
 | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp |
 | llvm/utils/gn/secondary/llvm/lib/Target/X86/Disassembler/BUILD.gn |
Commit
b375f28b0ec1129a4b94770a9c55ba49222ea1dd
by llvm-dev[X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the demanded elements of the lane mask. Fixes an cyclic dependency issue with an upcoming patch where getVectorShuffle canonicalizes masks with splat build vector sources.
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 | llvm/lib/Target/X86/X86ISelLowering.cpp |
Commit
66e39067edbfdb1469be001ebb053530a608b532
by llvm-dev[X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower binary v4f64 shuffles. Only perform this if we are shuffling lower and upper lane elements across the lanes (otherwise splitting to lower xmm shuffles would be better). This is a regression if we shuffle build_vectors due to getVectorShuffle canonicalizing 'blend of splat' build vectors, for now I've set this not to shuffle build_vector nodes at all to avoid this.
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 | llvm/test/CodeGen/X86/avx-unpack.ll |
 | llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll |
 | llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll |
 | llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll |
 | llvm/test/CodeGen/X86/subvector-broadcast.ll |
 | llvm/lib/Target/X86/X86ISelLowering.cpp |
Commit
065eefcfe969249a7df9d1ef4a0e468606b25359
by llvm-dev[AMDGPU] Regenerate shl shift tests
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 | llvm/test/CodeGen/AMDGPU/shl.ll |
Commit
a888277897f75b2952d96de229fff57519cfc363
by llvm-dev[MIPS] Regenerate shl/lshr shift tests
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 | llvm/test/CodeGen/Mips/llvm-ir/shl.ll |
 | llvm/test/CodeGen/Mips/llvm-ir/lshr.ll |
Commit
ad201691d5cc0f15f6f885f3847dcc6440ee3de5
by llvm-devFix "pointer is null" static analyzer warnings. NFCI. Use cast<> instead of dyn_cast<> and move into its users where its dereferenced immediately.
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 | clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp |
Commit
ebd26cc8c434f40fe8079ee823e7657b5138769f
by maskray[PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin Darwin support has been removed. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D72063
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 | llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h |
 | llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s |
 | llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp |
 | llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp |
 | llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp |
 | llvm/test/CodeGen/PowerPC/hello-reloc.s |
 | llvm/test/MC/MachO/PowerPC/lit.local.cfg |
 | llvm/test/MC/PowerPC/ppc-separator.s |
Commit
de797ccdd74f46d5f637ccf66c78da9905a46f42
by alexandre.ganea[NFC] Fix compilation of CrashRecoveryContext.cpp on mingw Patch by Markus Böck. Differential Revision: https://reviews.llvm.org/D72564
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 | llvm/lib/Support/CrashRecoveryContext.cpp |
Commit
7fa5290d5bd5632d7a36a4ea9f46e81e04fb819e
by maskray__patchable_function_entries: don't use linkage field 'unique' with -no-integrated-as .section name, "flags"G, @type, GroupName[, linkage] As of binutils 2.33, linkage cannot be 'unique'. For integrated assembler, we use both 'o' flag and 'unique' linkage to support --gc-sections and COMDAT with lld. https://sourceware.org/ml/binutils/2019-11/msg00266.html
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 | llvm/test/CodeGen/AArch64/patchable-function-entry.ll |
 | llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp |
Commit
241f330d6bab52ab4e3a01cbb9a3edd417d07c59
by jay.foad[AMDGPU] Add gfx8 assembler and disassembler test cases Summary: This adds assembler tests for cases that were previously only in the disassembler tests, and vice versa. Reviewers: rampitec, arsenm, nhaehnle Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72561
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 | llvm/test/MC/AMDGPU/gfx8_asm_all.s |
 | llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt |
Commit
2bfee35cb860859b436de0b780fbd00d68e198a4
by maskray[MC][ELF] Emit a relocation if target is defined in the same section and is non-local For a target symbol defined in the same section, currently we don't emit a relocation if VariantKind is VK_None (with few exceptions like RISC-V relaxation), while GNU as emits one. This causes program behavior differences with and without -ffunction-sections, and can break intended symbol interposition in a -shared link. ``` .globl foo foo: call foo # no relocation. On other targets, may be written as b foo, etc call bar # a relocation if bar is in another section (e.g. -ffunction-sections) call foo@plt # a relocation ``` Unify these cases by always emitting a relocation. If we ever want to optimize `call foo` in -shared links, we should emit a STB_LOCAL alias and call via the alias. ARM/thumb2-beq-fixup.s: we now emit a relocation to global_thumb_fn as GNU as does. X86/Inputs/align-branch-64-2.s: we now emit R_X86_64_PLT32 to foo as GNU does. ELF/relax.s: rewrite the test as target-in-same-section.s . We omitted relocations to `global` and now emit R_X86_64_PLT32. Note, GNU as does not emit a relocation for `jmp global` (maybe its own bug). Our new behavior is compatible except `jmp global`. Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D72197
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 | lld/test/ELF/global-offset-table-position-aarch64.s |
 | llvm/test/MC/ARM/thumb1-branch-reloc.s |
 | llvm/test/MC/X86/align-branch-64-2c.s |
 | llvm/lib/MC/ELFObjectWriter.cpp |
 | llvm/test/MC/ARM/thumb2-beq-fixup.s |
 | llvm/test/MC/X86/align-branch-64-2a.s |
 | llvm/test/MC/ELF/relax.s |
 | llvm/test/MC/X86/align-branch-64-2b.s |
 | llvm/test/MC/ELF/target-in-same-section.s |
Commit
ada22c804cd956f3ee7cc9dc82e6d54ead8a4ffe
by llvm-devFix "pointer is null" static analyzer warning. NFCI.
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 | clang/include/clang/Basic/SourceManager.h |
Commit
54b2914accb4f5c9b58305fd6da405d20a47c452
by llvm-devFix "pointer is null" static analyzer warnings. NFCI. Use castAs<> instead of getAs<> since the pointers are dereferenced immediately and castAs will perform the null assertion for us.
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 | clang/lib/AST/VTableBuilder.cpp |
Commit
0113cf193f0610bb1a5dfa0bcd29c41a8965938a
by jrtc27[RISCV] Check register class for AMO memory operands Summary: AMO memory operands use a custom parser in order to accept both (reg) and 0(reg). However, the validation predicate used for these operands was only checking that they were registers, and not the register class, so non-GPRs (such as FPRs) were also accepted. Thus, fix this by making the predicate check that they are GPRs. Reviewers: asb, lenary Reviewed By: asb, lenary Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72471
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 | llvm/test/MC/RISCV/rva-aliases-invalid.s |
 | llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp |
 | llvm/lib/Target/RISCV/RISCVInstrInfoA.td |
Commit
a6342c247a17fb270e0385bd1deb463b7309a43b
by czhengsz[SCEV] accurate range for addrecexpr with nuw flag If addrecexpr has nuw flag, the value should never be less than its start value and start value does not required to be SCEVConstant. Reviewed By: nikic, sanjoy Differential Revision: https://reviews.llvm.org/D71690
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 | llvm/lib/Analysis/ScalarEvolution.cpp |
 | llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll |
Commit
1ad1308b69b89cc87533c16957189a84e1dd9754
by zeratul976[clangd] Assert that the testcases in FindExplicitReferencesTest.All have no diagnostics Reviewers: kadircet Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D72355
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 | clang-tools-extra/clangd/unittests/FindTargetTests.cpp |
Commit
79a09d8bf4d508b0ae6a1e3c90907488092678c5
by zeratul976[clangd] Show template arguments in type hierarchy when possible Summary: Fixes https://github.com/clangd/clangd/issues/31 Reviewers: kadircet Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D71533
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 | clang-tools-extra/clangd/XRefs.cpp |
 | clang-tools-extra/clangd/unittests/TypeHierarchyTests.cpp |
Commit
a10527cd3731e2ef246c4797fb099385a948f62f
by arsenm2AMDGPU/GlobalISel: Copy type when inserting readfirstlane getDefIgnoringCopies will fail to find any def if no type is set if we try to use it on the use's operand, so propagate the type.
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 | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir |
Commit
555e7ee04cb5c44e0b11a2eda999e6910b4b27e1
by arsenm2AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir |
 | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir |
Commit
3c868cbbda7e2ff66b8ed92b632a609aaac324ba
by arsenm2AMDGPU: Split test function This avoids slightly different scheduling/regalloc behavior, and avoids a test diff between GlobalISel and SelectionDAG.
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 | llvm/test/CodeGen/AMDGPU/write_register.ll |
Commit
52aaf4a27576607dfc0833f5f88e5a15a30ceadb
by craig.topper[X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes. At least one of these is used without a Glue. This doesn't seem to change the X86GenDAGISel.inc output so maybe it doesn't matter?
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 | llvm/lib/Target/X86/X86InstrFPStack.td |
Commit
c958639098a8702b831952b1a1a677ae19190a55
by SourabhSingh.Tomar[DWARF5][DebugInfo]: Added support for DebugInfo generation for auto return type for C++ member functions. Summary: This patch will provide support for auto return type for the C++ member functions. Before this return type of the member function is deduced and stored in the DIE. This patch includes llvm side implementation of this feature. Patch by: Awanish Pandey <Awanish.Pandey@amd.com> Reviewers: dblaikie, aprantl, shafik, alok, SouraVX, jini.susan.george Reviewed by: dblaikie Differential Revision: https://reviews.llvm.org/D70524
|
 | llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp |
 | llvm/test/DebugInfo/X86/debug-info-auto-return.ll |
Commit
6d6a4590c5d4c7fc7445d72fe685f966b0a8cafb
by SourabhSingh.Tomar[DWARF5][clang]: Added support for DebugInfo generation for auto return type for C++ member functions. Summary: This patch will provide support for auto return type for the C++ member functions. This patch includes clang side implementation of this feature. Patch by: Awanish Pandey <Awanish.Pandey@amd.com> Reviewers: dblaikie, aprantl, shafik, alok, SouraVX, jini.susan.george Reviewed by: dblaikie Differential Revision: https://reviews.llvm.org/D70524
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 | clang/lib/CodeGen/CGDebugInfo.cpp |
 | clang/lib/CodeGen/CGDebugInfo.h |
 | clang/test/CodeGenCXX/debug-info-auto-return.cpp |
Commit
07028b5a87803a3a857d6dd6320a0f7de4db23ad
by sjoerd.meijer[SCEV] Follow up of D71563: addressing post commit comment. NFC.
|
 | llvm/lib/Analysis/ScalarEvolution.cpp |
Commit
9d3e78e704fa6201bceb48f45fb061f572c5aa2e
by sam.parker[NFC] Update loop.decrement.reg intrinsic comment Note that the intrinsic is now understood by SCEV and that other optimisations can treat it as a sub.
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 | llvm/include/llvm/IR/Intrinsics.td |
Commit
3cad8ada4947dc6793e5af56d6dd0e6eed9e570f
by zinenkoAdd zero_extendi and sign_extendi to intrinsic namespace Summary: - update zero_extendi and sign_extendi in edsc/intrinsic namespace - Builder API test for zero_extendi and sign_extendi Differential Revision: https://reviews.llvm.org/D72298
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 | mlir/include/mlir/EDSC/Intrinsics.h |
 | mlir/test/EDSC/builder-api-test.cpp |
Commit
ddf044290ede7d7fd47f4f673e3e628f551a8aac
by Raphael Isemann[lldb] Mark several tests as not dependent on debug info Summary: This just adds `NO_DEBUG_INFO_TESTCASE` to tests that don't really exercise anything debug information specific and therefore don't need to be rerun for all debug information variants. Reviewers: labath, jingham, aprantl, mib, jfb Reviewed By: aprantl Subscribers: dexonsmith, JDevlieghere, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D72447
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 | lldb/packages/Python/lldbsuite/test/commands/command/script_alias/TestCommandScriptAlias.py |
 | lldb/packages/Python/lldbsuite/test/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_events/TestWatchpointEvents.py |
 | lldb/packages/Python/lldbsuite/test/lang/c/offsetof/TestOffsetof.py |
 | lldb/packages/Python/lldbsuite/test/python_api/sbvalue_persist/TestSBValuePersist.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_set_command/TestWatchLocationWithWatchSet.py |
 | lldb/packages/Python/lldbsuite/test/commands/apropos/with-process/TestAproposWithProcess.py |
 | lldb/packages/Python/lldbsuite/test/python_api/findvalue_duplist/TestSBFrameFindValue.py |
 | lldb/packages/Python/lldbsuite/test/python_api/watchpoint/watchlocation/TestSetWatchlocation.py |
 | lldb/packages/Python/lldbsuite/test/commands/process/launch-with-shellexpand/TestLaunchWithShellExpand.py |
 | lldb/packages/Python/lldbsuite/test/commands/target/create-no-such-arch/TestNoSuchArch.py |
 | lldb/packages/Python/lldbsuite/test/python_api/process/TestProcessAPI.py |
 | lldb/packages/Python/lldbsuite/test/python_api/process/io/TestProcessIO.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/variable_out_of_scope/TestWatchedVarHitWhenInScope.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_commands/TestWatchpointCommands.py |
 | lldb/packages/Python/lldbsuite/test/commands/statistics/basic/TestStats.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/step_over_watchpoint/TestStepOverWatchpoint.py |
 | lldb/packages/Python/lldbsuite/test/python_api/debugger/TestDebuggerAPI.py |
 | lldb/packages/Python/lldbsuite/test/python_api/sbdata/TestSBData.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_commands/command/TestWatchpointCommandLLDB.py |
 | lldb/packages/Python/lldbsuite/test/python_api/rdar-12481949/Test-rdar-12481949.py |
 | lldb/packages/Python/lldbsuite/test/python_api/watchpoint/TestWatchpointIgnoreCount.py |
 | lldb/packages/Python/lldbsuite/test/python_api/watchpoint/TestWatchpointIter.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_commands/command/TestWatchpointCommandPython.py |
 | lldb/packages/Python/lldbsuite/test/python_api/watchpoint/TestSetWatchpoint.py |
 | lldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py |
 | lldb/packages/Python/lldbsuite/test/python_api/watchpoint/condition/TestWatchpointConditionAPI.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_disable/TestWatchpointDisable.py |
 | lldb/packages/Python/lldbsuite/test/commands/process/attach-resume/TestAttachResume.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_commands/condition/TestWatchpointConditionCmd.py |
 | lldb/packages/Python/lldbsuite/test/python_api/default-constructor/TestDefaultConstructorForAPIObjects.py |
 | lldb/packages/Python/lldbsuite/test/python_api/value/linked_list/TestValueAPILinkedList.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/hello_watchlocation/TestWatchLocation.py |
 | lldb/packages/Python/lldbsuite/test/lang/cpp/offsetof/TestOffsetofCpp.py |
 | lldb/packages/Python/lldbsuite/test/commands/command/nested_alias/TestNestedAlias.py |
 | lldb/packages/Python/lldbsuite/test/commands/expression/calculator_mode/TestCalculatorMode.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_on_vectors/TestValueOfVectorVariable.py |
 | lldb/packages/Python/lldbsuite/test/python_api/formatters/TestFormattersSBAPI.py |
 | lldb/packages/Python/lldbsuite/test/python_api/event/TestEvents.py |
 | lldb/packages/Python/lldbsuite/test/commands/watchpoints/hello_watchpoint/TestMyFirstWatchpoint.py |
Commit
c9babcbda77e69698825cfb9ce771352be93acee
by selliott[RISCV] Collect Statistics on Compressed Instructions Summary: It is useful to keep statistics on how many instructions we have compressed, so we can see if future changes are increasing or decreasing this number. Reviewers: asb, luismarques Reviewed By: asb, luismarques Subscribers: xbolva00, sameer.abuasal, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67495
|
 | llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp |
 | llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp |
Commit
734aa1d133f264746f721a244d2c66bc99648ee5
by usx[clangd] Publish xref for macros from Index and AST. Summary: With this patch the `findReferences` API will return Xref for macros. If the symbol under the cursor is a macro then we collect the references to it from: 1. Main file by looking at the ParsedAST. (These were added to the ParsedAST in https://reviews.llvm.org/D70008) 2. Files other than the mainfile by looking at the: * static index (Added in https://reviews.llvm.org/D70489) * file index (Added in https://reviews.llvm.org/D71406) This patch collects all the xref from the above places and outputs it in `findReferences` API. Reviewers: kadircet Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D72395
|
 | clang-tools-extra/clangd/XRefs.cpp |
 | clang-tools-extra/clangd/unittests/XRefsTests.cpp |
Commit
e45fcfc3aa57bb237fd4fd694d0c257be66d5482
by sam.mccallRevert "[DWARF5][clang]: Added support for DebugInfo generation for auto return type for C++ member functions." This reverts commit 6d6a4590c5d4c7fc7445d72fe685f966b0a8cafb, which introduces a crash. See https://reviews.llvm.org/D70524 for details.
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 | clang/lib/CodeGen/CGDebugInfo.cpp |
 | clang/lib/CodeGen/CGDebugInfo.h |
 | clang/test/CodeGenCXX/debug-info-auto-return.cpp |
Commit
96b8e1ac4674dd3035b6cc7b1b7ed8b946208ab1
by pavel[lldb] Fix eh-frame-small-fde test for changes in lld lld in 2bfee35 started emitting relocations for some intra-section jumps between global symbols. This shifted the code around a bit, invalidating text expectations. Change the symbols to local to keep the previous behavior.
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 | lldb/test/Shell/Unwind/Inputs/eh-frame-small-fde.s |
Commit
10c11e4e2d05cf0e8f8251f50d84ce77eb1e9b8d
by peter.smithThis option allows selecting the TLS size in the local exec TLS model, which is the default TLS model for non-PIC objects. This allows large/ many thread local variables or a compact/fast code in an executable. Specification is same as that of GCC. For example, the code model option precedes the TLS size option. TLS access models other than local-exec are not changed. It means supoort of the large code model is only in the local exec TLS model. Patch By KAWASHIMA Takahiro (kawashima-fj <t-kawashima@fujitsu.com>) Reviewers: dmgreen, mstorsjo, t.p.northover, peter.smith, ostannard Reviewd By: peter.smith Committed by: peter.smith Differential Revision: https://reviews.llvm.org/D71688
|
 | llvm/test/CodeGen/AArch64/arm64-tls-execs.ll |
 | clang/lib/Frontend/CompilerInvocation.cpp |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
 | clang/lib/CodeGen/BackendUtil.cpp |
 | llvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll |
 | clang/include/clang/Driver/Options.td |
 | llvm/include/llvm/Target/TargetOptions.h |
 | llvm/lib/Target/AArch64/AArch64TargetMachine.cpp |
 | clang/test/Driver/tls-size.c |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.h |
 | clang/lib/Driver/ToolChains/Clang.cpp |
 | clang/include/clang/Basic/CodeGenOptions.def |
 | llvm/include/llvm/CodeGen/CommandFlags.inc |
 | llvm/test/CodeGen/AArch64/arm64-tls-local-exec.ll |
Commit
add04b9653848de583c542e0596737f7d7c21553
by sjoerd.meijerARMLowOverheadLoops: return earlier to avoid printing irrelevant dbg msg. NFC
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 | llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp |
Commit
b6ffa2fe1250a8f506cc66044275b0bced56059e
by james.henderson[DebugInfo][Support] Replace DWARFDataExtractor size function This patch adds a new size function to the base DataExtractor class, which removes the need for the DWARFDataExtractor size function. It is unclear why DWARFDataExtractor's size function returned zero in some circumstances (i.e. when it is constructed without a section, and with a different data source instead), so that behaviour has changed. The old behaviour could cause an assertion in the debug line parser, as the size did not reflect the actual data available, and could be lower than the current offset being parsed. Reviewed by: dblaikie Differential Revision: https://reviews.llvm.org/D72337
|
 | llvm/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h |
 | llvm/include/llvm/Support/DataExtractor.h |
 | llvm/unittests/Support/DataExtractorTest.cpp |
Commit
af4adb07cd18b7081ec5818aee385654c8454356
by Raphael Isemann[lldb][NFC] Use range-based for loops in IRInterpreter
|
 | lldb/source/Expression/IRInterpreter.cpp |
Commit
bf7225888a99f49afac0b95a8996d0a942b6b0e3
by jan.kratochvil[lldb] Fix lookup of symbols with the same address range but different binding This fixes a failing testcase on Fedora 30 x86_64 (regression Fedora 29->30): PASS: ./bin/lldb ./lldb-test-build.noindex/functionalities/unwind/noreturn/TestNoreturnUnwind.test_dwarf/a.out -o 'settings set symbols.enable-external-lookup false' -o r -o bt -o quit * frame #0: 0x00007ffff7aa6e75 libc.so.6`__GI_raise + 325 frame #1: 0x00007ffff7a91895 libc.so.6`__GI_abort + 295 frame #2: 0x0000000000401140 a.out`func_c at main.c:12:2 frame #3: 0x000000000040113a a.out`func_b at main.c:18:2 frame #4: 0x0000000000401134 a.out`func_a at main.c:26:2 frame #5: 0x000000000040112e a.out`main(argc=<unavailable>, argv=<unavailable>) at main.c:32:2 frame #6: 0x00007ffff7a92f33 libc.so.6`__libc_start_main + 243 frame #7: 0x000000000040106e a.out`_start + 46 vs. FAIL - unrecognized abort() function: ./bin/lldb ./lldb-test-build.noindex/functionalities/unwind/noreturn/TestNoreturnUnwind.test_dwarf/a.out -o 'settings set symbols.enable-external-lookup false' -o r -o bt -o quit * frame #0: 0x00007ffff7aa6e75 libc.so.6`.annobin_raise.c + 325 frame #1: 0x00007ffff7a91895 libc.so.6`.annobin_loadmsgcat.c_end.unlikely + 295 frame #2: 0x0000000000401140 a.out`func_c at main.c:12:2 frame #3: 0x000000000040113a a.out`func_b at main.c:18:2 frame #4: 0x0000000000401134 a.out`func_a at main.c:26:2 frame #5: 0x000000000040112e a.out`main(argc=<unavailable>, argv=<unavailable>) at main.c:32:2 frame #6: 0x00007ffff7a92f33 libc.so.6`.annobin_libc_start.c + 243 frame #7: 0x000000000040106e a.out`.annobin_init.c.hot + 46 The extra ELF symbols are there due to Annobin (I did not investigate why this problem happened specifically since F-30 and not since F-28). It is due to: Symbol table '.dynsym' contains 2361 entries: Valu e Size Type Bind Vis Name 0000000000022769 5 FUNC LOCAL DEFAULT _nl_load_domain.cold 000000000002276e 0 NOTYPE LOCAL HIDDEN .annobin_abort.c.unlikely ... 000000000002276e 0 NOTYPE LOCAL HIDDEN .annobin_loadmsgcat.c_end.unlikely ... 000000000002276e 0 NOTYPE LOCAL HIDDEN .annobin_textdomain.c_end.unlikely 000000000002276e 548 FUNC GLOBAL DEFAULT abort 000000000002276e 548 FUNC GLOBAL DEFAULT abort@@GLIBC_2.2.5 000000000002276e 548 FUNC LOCAL DEFAULT __GI_abort 0000000000022992 0 NOTYPE LOCAL HIDDEN .annobin_abort.c_end.unlikely GDB has some more complicated preferences between overlapping and/or sharing address symbols, I have made here so far the most simple fix for this case. Differential revision: https://reviews.llvm.org/D63540
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 | lldb/include/lldb/Symbol/Symtab.h |
 | lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp |
 | lldb/test/Shell/SymbolFile/Inputs/symbol-binding.s |
 | lldb/test/Shell/SymbolFile/symbol-binding.test |
 | lldb/source/Symbol/Symtab.cpp |
Commit
7f1cf7d5f658b15abb8bd6840fc01e6d44487a23
by llvm-dev[X86] Fix MSVC "truncation from 'int' to 'bool'" warning. NFCI.
|
 | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp |
Commit
8f49204f26ea8856b870d4c2344b98f4b706bea0
by llvm-dev[SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526) As detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value. This patch adds support to SelectionDAG::ComputeKnownBits to use KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the minimum guaranteed leading/trailing known zero bits. Differential Revision: https://reviews.llvm.org/D72573
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
 | llvm/test/CodeGen/X86/vector-fshl-rot-128.ll |
 | llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll |
 | llvm/test/CodeGen/X86/vector-fshl-128.ll |
 | llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll |
 | llvm/test/CodeGen/Mips/llvm-ir/lshr.ll |
 | llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll |
 | llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll |
 | llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll |
 | llvm/test/CodeGen/AMDGPU/shl.ll |
 | llvm/test/CodeGen/X86/vector-fshr-128.ll |
 | llvm/test/CodeGen/X86/avx2-vector-shifts.ll |
 | llvm/test/CodeGen/X86/vector-fshr-rot-128.ll |
 | llvm/test/CodeGen/X86/vector-rotate-128.ll |
 | llvm/test/CodeGen/AMDGPU/shl.v2i16.ll |
 | llvm/test/CodeGen/X86/avx2-shift.ll |
 | llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll |
 | llvm/test/CodeGen/X86/vector-shift-lshr-128.ll |
 | llvm/test/CodeGen/BPF/shifts.ll |
 | llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll |
Commit
804dd6722762040e7ce7e04bf97b19d9596fee20
by Milos.Stojanovic[llvm-exegesis][mips] Expand loadImmediate() Add support for loading 32-bit immediates and enable the use of GPR64 registers. Differential Revision: https://reviews.llvm.org/D71873
|
 | llvm/tools/llvm-exegesis/lib/Mips/Target.cpp |
 | llvm/test/tools/llvm-exegesis/Mips/latency-GPR64.s |
 | llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp |
Commit
b96ec492d34ecf31fd2c8d2f0033f00e36cc2b9c
by oliver.stannard[clangd] Remove raw string literals in macros Older (but still supported) versions of GCC don't handle C++11 raw string literals in macro parameters correctly.
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 | clang-tools-extra/clangd/unittests/FormattedStringTests.cpp |
Commit
7efc7ca8edf6762dc64472417dabfbbdd838ceeb
by llvm-dev[X86][SSE] Add knownbits test showing missing getValidMinimumShiftAmountConstant() ISD::SHL support As mentioned on D72573
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 | llvm/test/CodeGen/X86/combine-shl.ll |
Commit
ef5debac4302cd479ddd9e784a5b5acc8c2b9804
by llvm-dev[SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ISD::SHL support As mentioned on D72573
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
 | llvm/test/CodeGen/X86/combine-shl.ll |
Commit
6c203149b60e92e802df0c7a431744c337830a09
by oliver.stannard[clang] Remove raw string literals in macros Older (but still supported) versions of GCC don't handle C++11 raw string literals in macro parameters correctly.
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 | clang/unittests/AST/ASTTraverserTest.cpp |
 | clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp |
Commit
c1fbede984ec1eb87b35218d3b8161d3a6e92318
by Raphael Isemann[lldb][NFC] Remove debug print statement from TestExprDiagnostics.py
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 | lldb/packages/Python/lldbsuite/test/commands/expression/diagnostics/TestExprDiagnostics.py |
Commit
a70b993239a829f30ff1e5991670a0b28bf51459
by Milos.Stojanovic[llvm-exegesis] Remove unneeded std::move() Caught by buildbot breakage: /home/docker/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp:89:12: error: moving a local object in a return statement prevents copy elision [-Werror,-Wpessimizing-move] return std::move(Instructions); ^ /home/docker/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp:89:12: note: remove std::move call here return std::move(Instructions); ^~~~~~~~~~ ~
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 | llvm/tools/llvm-exegesis/lib/Mips/Target.cpp |
Commit
d7d88b9d8b3efd8b4b07074aa64b5b4136a35b2c
by arsenm2GlobalISel: Fix assertion on wide G_ZEXT sources It's possible to have a type that needs a mask greater than 64-bits.
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 | llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir |
Commit
04a86966fbf46809d7a165b1f089e4d076f0f8a5
by ulrich.weigand[FPEnv] Fix chain handling for fpexcept.strict nodes We need to ensure that fpexcept.strict nodes are not optimized away even if the result is unused. To do that, we need to chain them into the block's terminator nodes, like already done for PendingExcepts. This patch adds two new lists of pending chains, PendingConstrainedFP and PendingConstrainedFPStrict to hold constrained FP intrinsic nodes without and with fpexcept.strict markers. This allows not only to solve the above problem, but also to relax chains a bit further by no longer flushing all FP nodes before a store or other memory access. (They are still flushed before nodes with other side effects.) Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D72341
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
 | llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll |
 | llvm/test/CodeGen/X86/fp-intrinsics.ll |
 | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h |
 | llvm/test/CodeGen/X86/fp128-libcalls-strict.ll |
 | llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll |
 | llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll |
 | llvm/test/CodeGen/X86/fp128-cast-strict.ll |
 | llvm/test/CodeGen/SystemZ/fp-strict-alias.ll |
 | llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll |
Commit
6a634a5dba847e1c1d81bf59f76dfa7d76ac3c4c
by oliver.stannardRevert "[libc++] Explicitly enumerate std::string external instantiations." This is causing failures for multiple buildbots and bootstrap builds, details at https://reviews.llvm.org/rG61bd1920. This reverts commit 61bd19206f61ace4b007838a2ff8884a13ec0374.
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 | libcxx/include/string |
 | libcxx/include/__string |
 | libcxx/include/__config |
 | libcxx/src/string.cpp |
Commit
89ba150240a45cac88216b6127efb523fb9506b0
by llvm-dev[X86] Add knownbits tests showing missing shift amount demanded elts handling.
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 | llvm/test/CodeGen/X86/known-bits-vector.ll |
 | llvm/test/CodeGen/X86/combine-shl.ll |
Commit
6d1a8fd447934387605ea11d35e1b62866b7d093
by llvm-dev[SelectionDAG] ComputeKnownBits - Add DemandedElts support to getValidShiftAmountConstant/getValidMinimumShiftAmountConstant()
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 | llvm/test/CodeGen/X86/combine-shl.ll |
 | llvm/test/CodeGen/X86/known-bits-vector.ll |
 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
Commit
376bc39c829fab7ad14424c5418c03ed6649d839
by llvm-dev[SelectionDAG] ComputeNumSignBits - Use getValidShiftAmountConstant for shift opcodes getValidShiftAmountConstant handles out of bounds shift amounts for us, allowing us to remove the local handling.
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
Commit
26d2ace9e2305266be888e15392be29e3145163d
by spatel[InstSimplify] move tests for select from InstCombine; NFC InstCombine has transforms that would enable these simplifications in an indirect way, but those transforms are unsafe and likely to be removed.
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 | llvm/test/Transforms/InstCombine/select.ll |
 | llvm/test/Transforms/InstSimplify/select.ll |
Commit
894f742acb977a09285dcab024e50c2cf6bce578
by Alexander.Richardson[MIPS][ELF] Use PC-relative relocations in .eh_frame when possible When compiling position-independent executables, we now use DW_EH_PE_pcrel | DW_EH_PE_sdata4. However, the MIPS ABI does not define a 64-bit PC-relative ELF relocation so we cannot use sdata8 for the large code model case. When using the large code model, we fall back to the previous behaviour of generating absolute relocations. With this change clang-generated .o files can be linked by LLD without having to pass -Wl,-z,notext (which creates text relocations). This is simpler than the approach used by ld.bfd, which rewrites the .eh_frame section to convert absolute relocations into relative references. I saw in D13104 that apparently ld.bfd did not accept pc-relative relocations for MIPS ouput at some point. However, I also checked that recent ld.bfd can process the clang-generated .o files so this no longer seems true. Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72228
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 | lld/test/ELF/mips-eh_frame-pic.s |
 | llvm/test/DebugInfo/Mips/eh_frame.ll |
 | llvm/test/MC/Mips/eh-frame.s |
 | llvm/lib/MC/MCObjectFileInfo.cpp |
 | llvm/lib/Object/RelocationResolver.cpp |
Commit
8e8ccf4712cf58562a91c197da3efd4f9963ce0d
by Alexander.Richardson[MIPS] Don't emit R_(MICRO)MIPS_JALR relocations against data symbols The R_(MICRO)MIPS_JALR optimization only works when used against functions. Using the relocation against a data symbol (e.g. function pointer) will cause some linkers that don't ignore the hint in this case (e.g. LLD prior to commit 5bab291b7b) to generate a relative branch to the data symbol which crashes at run time. Before this patch, LLVM was erroneously emitting these relocations against local-dynamic TLS function pointers and global function pointers with internal visibility. Reviewers: atanasyan, jrtc27, vstefanovic Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72571
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 | llvm/test/CodeGen/Mips/reloc-jalr.ll |
 | llvm/lib/Target/Mips/MipsISelLowering.cpp |
Commit
da33762de8531914d4d0dae16bfce2192f02bc79
by pablo.barrio[AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below Summary: The Pointer Authentication Extension (PAC) was added in Armv8.3-A. Some instructions are implemented in the HINT space to allow compiling code common to CPUs regardless of whether they feature PAC or not, and still benefit from PAC protection in the PAC-enabled CPUs. The 8.3-specific mnemonics were currently enabled in any architecture, and LLVM was emitting them in assembly files when PAC code generation was enabled. This was ok for compilations where both LLVM codegen and the integrated assembler were used. However, the LLVM codegen was not compatible with other assemblers (e.g. GAS). Given the fact that the approach from these assemblers (i.e. to disallow Armv8.3-A mnemonics if compiling for Armv8.2-A or lower) is entirely reasonable, this patch makes LLVM to emit HINT when building for Armv8.2-A and below, instead of PACIASP, AUTIASP and friends. Then, LLVM assembly should be compatible with other assemblers. Reviewers: samparker, chill, LukeCheeseman Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71658
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 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll |
 | llvm/lib/Target/AArch64/AArch64InstrInfo.td |
 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll |
 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll |
 | llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll |
 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll |
 | llvm/test/CodeGen/AArch64/sign-return-address.ll |
 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll |
 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll |
 | llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll |
 | llvm/test/MC/AArch64/armv8.3a-signed-pointer.s |
 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll |
 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll |
Commit
0b91e78a719065c67b33bf82b0cde3d4ecfe3b7d
by sam.mccallAdd missing triples to tests in 0c29d3ff2233696f663ae34a8aeda23c750ac68f so they target the right arch.
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 | llvm/test/CodeGen/X86/align-branch-boundary-default.ll |
 | llvm/test/CodeGen/X86/align-branch-boundary-default.s |
Commit
7af67259cdd66811941514a263dd0f81c491d8f1
by llvm-devSema::getOwningModule - take const Decl* type. Fixes static analyzer warning that const_cast was being used despite only const methods being called.
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 | clang/lib/Sema/SemaOverload.cpp |
 | clang/include/clang/Sema/Sema.h |
Commit
40311f9724953541ab7b755fb6a96b31c1e63f00
by llvm-devFix "pointer is null" static analyzer warnings. NFCI. Use castAs<> instead of getAs<> since the pointers are always dereferenced and castAs will perform the null assertion for us.
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 | clang/lib/AST/ASTContext.cpp |
Commit
025941785faf25a3d9ba2c1e7682ca6c2ad063af
by llvm-devFix some cppcheck shadow variable warnings. NFCI.
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 | clang/lib/AST/ASTContext.cpp |
Commit
4647aae72f33b8742eb42c1fb869ebd4fdbb3038
by llvm-devMerge isVectorType() and getAs<VectorType> calls to silence clang static analyzer warning. NFCI.
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 | clang/lib/AST/ASTDiagnostic.cpp |
Commit
b11027a08620dce2887377c830be239a4af478b6
by llvm-devFix cppcheck uninitialized variable in DiffTree() constructor warning. NFCI.
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 | clang/lib/AST/ASTDiagnostic.cpp |
Commit
043c5eafa8789d76b06b93d157c928830c4d0814
by luismarques[RISCV] Handle globals and block addresses in asm operands Summary: These seem to be the machine operand types currently needed by the RISC-V target. Reviewers: asb, lenary Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D72275
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 | llvm/test/CodeGen/RISCV/inline-asm.ll |
 | llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp |
Commit
b4a99a061f517e60985667e39519f60186cbb469
by alexandre.ganea[Clang][Driver] Re-use the calling process instead of creating a new process for the cc1 invocation With this patch, the clang tool will now call the -cc1 invocation directly inside the same process. Previously, the -cc1 invocation was creating, and waiting for, a new process. This patch therefore reduces the number of created processes during a build, thus it reduces build times on platforms where process creation can be costly (Windows) and/or impacted by a antivirus. It also makes debugging a bit easier, as there's no need to attach to the secondary -cc1 process anymore, breakpoints will be hit inside the same process. Crashes or signaling inside the -cc1 invocation will have the same side-effect as before, and will be reported through the same means. This behavior can be controlled at compile-time through the CLANG_SPAWN_CC1 cmake flag, which defaults to OFF. Setting it to ON will revert to the previous behavior, where any -cc1 invocation will create/fork a secondary process. At run-time, it is also possible to tweak the CLANG_SPAWN_CC1 environment variable. Setting it and will override the compile-time setting. A value of 0 calls -cc1 inside the calling process; a value of 1 will create a secondary process, as before. Differential Revision: https://reviews.llvm.org/D69825
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 | clang/lib/Driver/ToolChains/Clang.cpp |
 | clang/lib/Driver/Job.cpp |
 | clang/test/Driver/cc1-spawnprocess.c |
 | clang/test/Driver/fsanitize-blacklist.c |
 | clang/include/clang/Driver/Driver.h |
 | clang/test/Driver/warning-options_pedantic.cpp |
 | clang/include/clang/Driver/Job.h |
 | clang/tools/driver/driver.cpp |
 | clang/CMakeLists.txt |
 | clang/include/clang/Config/config.h.cmake |
 | clang/test/CMakeLists.txt |
 | clang/test/Driver/clang_f_opts.c |
 | clang/test/Driver/unknown-arg.c |
Commit
e653d306ce90e5612796d8adce9eb34b1c10e85a
by ntv[mlir][Linalg] Update ReshapeOp::build to be more idiomatic Summary: This diff makes it easier to create a `linalg.reshape` op and adds an EDSC builder api test to exercise the new builders. Reviewers: ftynse, jpienaar Subscribers: mehdi_amini, rriddle, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72580
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 | mlir/include/mlir/Dialect/Linalg/EDSC/Intrinsics.h |
 | mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td |
 | mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp |
 | mlir/test/EDSC/builder-api-test.cpp |
Commit
6b686703e63f0e992438ce445cbe4b3e78b94ea4
by kazu[Inlining] Add PreInlineThreshold for the new pass manager Summary: This patch makes it easy to try out different preinlining thresholds with a command-line switch just like -preinline-threshold for the legacy pass manager. Reviewers: davidxl Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72618
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 | llvm/lib/Passes/PassBuilder.cpp |
Commit
202ab273e6eca134b69882f100c666fcd3affbcf
by julian.gross[mlir] Added missing GPU lowering ops. Summary: This diff adds missing GPU lowering ops to MLIR. Reviewers: herhut, pifon2a, ftynse Tags: #pre-merge_beta_testing, #llvm Differential Revision: https://reviews.llvm.org/D72439
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 | mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp |
 | mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp |
 | mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir |
 | mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir |
Commit
81e7922e83cf9782a39f4072e20eab8ab1e99828
by zinenko[mlir] m_Constant() Summary: Introduce m_Constant() which allows matching a constant operation without forcing the user also to capture the attribute value. Differential Revision: https://reviews.llvm.org/D72397
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 | mlir/test/lib/IR/TestMatchers.cpp |
 | mlir/test/IR/test-matchers.mlir |
 | mlir/lib/IR/Builders.cpp |
 | mlir/include/mlir/IR/Matchers.h |
Commit
07804f75a6cc506fada40c474f1e60840ce737d8
by james.henderson[DebugInfo] Make debug line address size mismatch non-fatal to parsing Reasonable assumptions can be made when a parsed address length does not match the expected length, so there's no need for this to be fatal. Reviewed by: ikudrin Differential Revision: https://reviews.llvm.org/D72154
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 | llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp |
 | llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp |
Commit
2af97be8027a0823b88d4b6a07fc5eedb440bc1f
by tejohnson[ThinLTO] Add additional ThinLTO pipeline testing with new PM Summary: I've added some more extensive ThinLTO pipeline testing with the new PM, motivated by the bug fixed in D72386. I beefed up llvm/test/Other/new-pm-pgo.ll a little so that it tests ThinLTO pre and post link with PGO, similar to the testing for the default pipelines with PGO. Added new pre and post link PGO tests for both instrumentation and sample PGO that exhaustively test the pipelines at different optimization levels via opt. Added a clang test to exhaustively test the post link pipeline invoked for distributed builds. I am currently only testing O2 and O3 since these are the most important for performance. It would be nice to add similar exhaustive testing for full LTO, and for the old PM, but I don't have the bandwidth now and this is a start to cover some of the situations that are not currently default and were under tested. Reviewers: wmi Subscribers: mehdi_amini, inglorion, hiraditya, steven_wu, dexonsmith, jfb, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D72538
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 | llvm/test/Other/Inputs/new-pm-thinlto-prelink-pgo-defaults.proftext |
 | llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll |
 | llvm/test/Other/new-pm-pgo.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll |
 | clang/test/CodeGen/thinlto-distributed-newpm.ll |
 | llvm/test/Other/Inputs/new-pm-thinlto-samplepgo-defaults.prof |
 | llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll |
Commit
2d7e757a836abb54590daa25fce626283adafadf
by danilo.carvalho.grael[AArch64][SVE] Add patterns for some arith SVE instructions. Summary: Add patterns for the following instructions: - smax, smin, umax, umin Reviewers: sdesmalen, huntergr, rengolin, efriedma, c-rhodes, mgudim, kmclaughlin Subscribers: amehsan Differential Revision: https://reviews.llvm.org/D71779
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 | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp |
 | llvm/lib/Target/AArch64/SVEInstrFormats.td |
 | llvm/lib/Target/AArch64/AArch64InstrFormats.td |
 | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td |
 | llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
Commit
90555d9253437d53fe03c26db73faf9c0ca14c82
by david.green[Scheduler] Remove superfluous casts. NFC
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 | llvm/lib/CodeGen/TargetInstrInfo.cpp |
 | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp |
Commit
ee4aa1a228b31ec8b8bd3c4a793c7fa92fec88d6
by llvm-dev[X86] Add AVX2 known signbits codegen tests
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 | llvm/test/CodeGen/X86/known-signbits-vector.ll |
Commit
7afaa0099b907842b281c25c2a57937a2c307d3b
by llvm-dev[X86][SSE] Add sitofp(ashr(x,y)) test case with non-uniform shift value
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 | llvm/test/CodeGen/X86/known-signbits-vector.ll |
Commit
38e2c01221a9751c0b797417747200d2e9513b9f
by llvm-dev[SelectionDAG] ComputeNumSignBits add getValidMinimumShiftAmountConstant() ISD::SRA support Allows us to handle more non-uniform SRA sign bits cases
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
 | llvm/test/CodeGen/X86/known-signbits-vector.ll |
Commit
05366870eed154c7eb48c7cc3873ea5188f54cc9
by weiwei64[LegalizeTypes] Add SoftenFloatResult support for STRICT_SINT_TO_FP/STRICT_UINT_TO_FP Some target like arm/riscv with soft-float will have compiling crash when using -fno-unsafe-math-optimization option. This patch will add the missing strict FP support to SoftenFloatRes_XINT_TO_FP. Differential Revision: https://reviews.llvm.org/D72277
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 | llvm/test/CodeGen/ARM/fp-intrinsics.ll |
 | llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp |
Commit
f2bbe8ede057af13b56949f24bbfb436f8a55f97
by Jonas Devlieghere[lldb/Scripts] Remove SWIG bot This is no longer used or maintained. Differential revision: https://reviews.llvm.org/D72539
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 | lldb/scripts/swig_bot_lib/client.py |
 | lldb/scripts/swig_bot.py |
 | lldb/scripts/swig_bot_lib/remote.py |
 | lldb/scripts/swig_bot_lib/local.py |
 | lldb/scripts/swig_bot_lib/server.py |
Commit
bb2e5f5e454245c8e7e9e4c9bf7a463c64604292
by tejohnsonFix tests for builtbot failures Should fix most of the buildbot failures from 2af97be8027a0823b88d4b6a07fc5eedb440bc1f, by loosening up the matching on the AnalysisProxy output. Added in --dump-input=fail on the one test that appears to be something different, so I can hopefully debug it better.
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 | llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll |
 | clang/test/CodeGen/thinlto-distributed-newpm.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll |
Commit
9d30d769041b14c0ff29770d59027e679e6b7edc
by Jonas Devlieghere[lldb/Docs] Extend description section of the main page The current description is a bit terse. I've copy/pasted the introduction form the website.
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 | lldb/docs/man/lldb.rst |
Commit
ffc05d0dbc88b89756d553ff32abefe720d27742
by llvm-dev[X86][SSE] Add sitofp(shl(sext(x),y)) test case with non-uniform shift value Shows that for non-uniform SHL shifts we fail to determine the minimum number of sign bits remaining (based off the maximum shift amount value)
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 | llvm/test/CodeGen/X86/known-signbits-vector.ll |
Commit
7d9b0a61c32b95fdc73228266d3f14687a8ada95
by arsenm2AMDGPU/GlobalISel: Simplify assert
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 | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
Commit
ca19d7a3993c69633826ae388155c9ad176b11df
by arsenm2AMDGPU/GlobalISel: Fix branch targets when emitting SI_IF The branch target needs to be changed depending on whether there is an unconditional branch or not. Loops also need to be similarly fixed, but compiling a simple testcase end to end requires another set of patches that aren't upstream yet.
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 | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll |
Commit
2f090cc8f1a3144c81b024bdc52ec1ae49dc0def
by arsenm2AMDGPU/GlobalISel: Add some baseline tests for vector extract A future change will try to fold constant offsets into the loop which these will stress.
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir |
Commit
3d8f1b2d22be79aab3d246fa5bc9c24b911b0bd2
by arsenm2AMDGPU/GlobalISel: Set insert point after waterfall loop The current users of the waterfall loop utility functions do not make use of the restored original insert point. The insertion is either done, or they set the insert point somewhere else. A future change will want to insert instructions after the waterfall loop, but figuring out the point after the loop is more difficult than ensuring the insert point is there after the loop.
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 | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
Commit
c6fcd5d115b62280669719c5ead436904c93d6cb
by llvm-dev[SelectionDAG] ComputeNumSignBits add getValidMaximumShiftAmountConstant() for ISD::SHL support Allows us to handle non-uniform SHL shifts to determine the minimum number of sign bits remaining (based off the maximum shift amount value)
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
 | llvm/test/CodeGen/X86/known-signbits-vector.ll |
Commit
203801425d222555fa2617fff19ecd861525429f
by arsenm2AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap}
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.ordered.add.gfx10.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.ordered.swap.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.ordered.add.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
Commit
292562c0046c72ea1ed229dbe13a89dca73e5b89
by tejohnsonTry number 2 for fixing bot failures Additional fixes for bot failures from 2af97be8027a0823b88d4b6a07fc5eedb440bc1f. Remove more exact matching on AnalyisManagers, as they can vary. Also allow different orders between LoopAnalysis and BranchProbabilityAnalysis as that can vary due to both being accessed in the parameter list of a call.
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 | llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll |
 | clang/test/CodeGen/thinlto-distributed-newpm.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll |
Commit
a2cd4fe6bf2a4e37d5f69b0b19cb1134a14e2970
by benny.kraUnbreak the mlir build after 202ab273e6eca134b69882f100c666fcd3affbcf
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 | mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp |
 | mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp |
Commit
fb79ef524171c96a9f3df025ac7a8a3e00fdc0b4
by aaronFix readability-identifier-naming missing member variables Fixes PR41122 (missing fixes for member variables in a destructor) and PR29005 (does not rename class members in all locations).
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 | clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp |
 | clang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-member-decl-usage.cpp |
Commit
7aed43b60739653b13b8503f9df4c958c44feed8
by tejohnsonHopefully last fix for bot failures Hopefully final bot fix for last few failures from 2af97be8027a0823b88d4b6a07fc5eedb440bc1f. Looks like sometimes the "llvm::" preceeding objects get printed in the debug pass manager output and sometimes they don't. Replace with wildcard matching.
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 | llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll |
 | clang/test/CodeGen/thinlto-distributed-newpm.ll |
 | llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll |
Commit
484a7472f1aa6906f2b66dc33bcf69cc8d5b9f29
by puyan[llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands. This patch makes it so that cases where multiple instructions that differ only in their FrameIndex MachineOperand values no longer collide. For instance: %1:_(p0) = G_FRAME_INDEX %stack.0 %2:_(p0) = G_FRAME_INDEX %stack.1 Prior to this patch these instructions would collide together. Differential Revision: https://reviews.llvm.org/D71583
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 | llvm/lib/CodeGen/MIRVRegNamerUtils.cpp |
 | llvm/test/CodeGen/MIR/X86/mir-namer-hash-frameindex.mir |
Commit
64a93afc3c630c39e5c583e4f67aef5821d635b6
by maskray[X86][Disassembler] Fix a bug when disassembling an empty string readPrefixes() assumes insn->bytes is non-empty. The code path is not exercised in llvm-mc because llvm-mc does not feed empty input to MCDisassembler::getInstruction(). This bug is uncovered by a5994c789a2982a770254ae1607b5b4cb641f73c. An empty string did not crash before because the deleted regionReader() allowed UINT64_C(-1) as insn->readerCursor. Bytes.size() <= Address -> R->Base 0 <= UINT64_C(-1) - UINT32_C(-1)
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 | llvm/unittests/MC/Disassembler.cpp |
 | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp |
Commit
cb988a858abbaf1a1ae0fe03f2a1dae692131ea9
by tejohnsonAdd a couple of missed wildcards in debug-pass-manager output checking Along with the previous fix for bot failures from 2af97be8027a0823b88d4b6a07fc5eedb440bc1f, need to add a wildcard in a couple of places where my local output did not print "llvm::" but the bot is.
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 | clang/test/CodeGen/thinlto-distributed-newpm.ll |
 | llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll |