SuccessChanges

Summary

  1. [Driver] Fix OptionClass of -fconvergent-functions and -fms-volatile (details)
  2. [Concepts] Fix MarkUsedTemplateParameters for exprs (details)
  3. Remove umask tests (details)
  4. [COFF] Align ARM64 range extension thunks at instruction boundary (details)
  5. [TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare (details)
  6. [SCEV] [NFC] add more test cases for range of addrecexpr with nsw flag (details)
  7. [NFC] [PowerPC] Update mi-peephole-splat test (details)
  8. [AMDGPU] Remove unnecessary v_mov from a register to itself in WQM (details)
  9. Mark the test/Feature/load_extension.ll test as unsupported on Darwin. (details)
  10. [X86] Use ReplaceAllUsesWith instead of ReplaceAllUsesOfValueWith to (details)
  11. [X86][Disassembler] Simplify readPrefixes (details)
  12. [X86] Preserve fpexcept property when turning strict_fp_extend and (details)
  13. [X86] Simplify code by removing an unreachable condition. NFCI (details)
  14. Add test for GDB pretty printers. (details)
  15. [X86] Remove dead code from X86DAGToDAGISel::Select that is no longer (details)
  16. [InstCombine] Preserve nuw on sub of geps (PR44419) (details)
  17. [LoopSimplify] Regenerate test checks; NFC (details)
  18. [LoopRotate] Add tests for rotate with switch; NFC (details)
  19. DSE: fix bug where we would only check libcalls for name rather than (details)
  20. [X86] Add more complex tests for vector masks used with AND/OR/XOR. (details)
  21. [X86][AVX] Add lowerShuffleAsLanePermuteAndSHUFP lowering (details)
  22. Fix copy+paste typo in shuffle test name (details)
  23. [Sema] Improve -Wrange-loop-analysis warnings. (details)
  24. [X86] Fix outdated comment (details)
  25. moveOperands - assert Src/Dst MachineOperands are non-null. (details)
  26. Remove copy ctors identical to the default one. NFC. (details)
  27. Fix uninitialized value clang static analyzer warning. NFC. (details)
  28. Fix "pointer is null" static analyzer warning. NFCI. (details)
  29. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  30. Fix "pointer is null" static analyzer warning. NFCI. (details)
  31. Fix "pointer is null" static analyzer warning. NFCI. (details)
  32. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  33. GlobalModuleIndex - Fix use-after-move clang static analyzer warning. (details)
  34. [X86AsmBackend] Be consistent about placing definitions out of line (details)
  35. [X86AsmBackend] Move static function before sole use [NFC] (details)
  36. [X86] Adjust nop emission by compiler to consider target decode (details)
  37. [mlir] NFC: Remove Value::operator* and Value::operator-> now that Value (details)
  38. [ASTMatchers] extract public matchers from const-analysis into own patch (details)
  39. Revert "[ASTMatchers] extract public matchers from const-analysis into (details)
  40. [ExecutionEngine] Re-enable FastISel for non-iOS arm targets. (details)
  41. Add -Wrange-loop-analysis changes to ReleaseNotes (details)
  42. [X86] Turn FP_ROUND/STRICT_FP_ROUND into (details)
  43. [X86][Disassembler] Simplify and optimize reader functions (details)
  44. [LegalizeVectorOps] Only pass SDNode* instead SDValue to all of the (details)
  45. [LegalizeVectorOps] Remove some of the simpler Expand methods. Pass (details)
  46. [X86][Disassembler] Replace custom logger with LLVM_DEBUG (details)
  47. [Support] Optionally call signal handlers when a function wrapped by the (details)
  48. [ORC] Fix argv handling in runAsMain / lli. (details)
  49. [Disassembler] Delete the VStream parameter of (details)
  50. [X86][Disassembler] Optimize argument passing and immediate reading (details)
  51. [X86][Disassembler] Shrink X86GenDisassemblerTables.inc from 36M to 6.1M (details)
  52. [LegalizeVectorOps] Expand vector MERGE_VALUES immediately. (details)
  53. [TargetLowering][X86] Connect the chain from STRICT_FSETCC in (details)
  54. [LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UINT_TO_FLOAT (details)
  55. [SCEV] more accurate range for addrecexpr with nsw flag. (details)
  56. [X86] Don't call LowerSETCC from LowerSELECT for (details)
  57. [NFC] Refactor memory ops cluster method (details)
  58. [profile] Support merge pool size >= 10 (details)
  59. [X86][Disassembler] Simplify (details)
  60. [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into (details)
  61. [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the demanded (details)
  62. [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower binary v4f64 (details)
  63. [AMDGPU] Regenerate shl shift tests (details)
  64. [MIPS] Regenerate shl/lshr shift tests (details)
  65. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  66. [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin (details)
  67. [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw (details)
  68. __patchable_function_entries: don't use linkage field 'unique' with (details)
  69. [AMDGPU] Add gfx8 assembler and disassembler test cases (details)
  70. [MC][ELF] Emit a relocation if target is defined in the same section and (details)
  71. Fix "pointer is null" static analyzer warning. NFCI. (details)
  72. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  73. [RISCV] Check register class for AMO memory operands (details)
  74. [SCEV] accurate range for addrecexpr with nuw flag (details)
  75. [clangd] Assert that the testcases in FindExplicitReferencesTest.All (details)
  76. [clangd] Show template arguments in type hierarchy when possible (details)
  77. AMDGPU/GlobalISel: Copy type when inserting readfirstlane (details)
  78. AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs (details)
  79. AMDGPU: Split test function (details)
  80. [X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes. (details)
  81. [DWARF5][DebugInfo]: Added support for DebugInfo generation for auto (details)
  82. [DWARF5][clang]: Added support for DebugInfo generation for auto return (details)
  83. [SCEV] Follow up of D71563: addressing post commit comment. NFC. (details)
  84. [NFC] Update loop.decrement.reg intrinsic comment (details)
  85. Add zero_extendi and sign_extendi to intrinsic namespace (details)
  86. [lldb] Mark several tests as not dependent on debug info (details)
  87. [RISCV] Collect Statistics on Compressed Instructions (details)
  88. [clangd] Publish xref for macros from Index and AST. (details)
  89. Revert "[DWARF5][clang]: Added support for DebugInfo generation for auto (details)
  90. [lldb] Fix eh-frame-small-fde test for changes in lld (details)
  91. This option allows selecting the TLS size in the local exec TLS model, (details)
  92. ARMLowOverheadLoops: return earlier to avoid printing irrelevant dbg (details)
  93. [DebugInfo][Support] Replace DWARFDataExtractor size function (details)
  94. [lldb][NFC] Use range-based for loops in IRInterpreter (details)
  95. [lldb] Fix lookup of symbols with the same address range but different (details)
  96. [X86] Fix MSVC "truncation from 'int' to 'bool'" warning. NFCI. (details)
  97. [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in (details)
  98. [llvm-exegesis][mips] Expand loadImmediate() (details)
  99. [clangd] Remove raw string literals in macros (details)
  100. [X86][SSE] Add knownbits test showing missing (details)
  101. [SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() (details)
  102. [clang] Remove raw string literals in macros (details)
  103. [lldb][NFC] Remove debug print statement from TestExprDiagnostics.py (details)
  104. [llvm-exegesis] Remove unneeded std::move() (details)
  105. GlobalISel: Fix assertion on wide G_ZEXT sources (details)
  106. [FPEnv] Fix chain handling for fpexcept.strict nodes (details)
  107. Revert "[libc++] Explicitly enumerate std::string external (details)
  108. [X86] Add knownbits tests showing missing shift amount demanded elts (details)
  109. [SelectionDAG] ComputeKnownBits - Add DemandedElts support to (details)
  110. [SelectionDAG] ComputeNumSignBits - Use getValidShiftAmountConstant for (details)
  111. [InstSimplify] move tests for select from InstCombine; NFC (details)
  112. [MIPS][ELF] Use PC-relative relocations in .eh_frame when possible (details)
  113. [MIPS] Don't emit R_(MICRO)MIPS_JALR relocations against data symbols (details)
  114. [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below (details)
  115. Add missing triples to tests in 0c29d3ff2233696f663ae34a8aeda23c750ac68f (details)
  116. Sema::getOwningModule - take const Decl* type. (details)
  117. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  118. Fix some cppcheck shadow variable warnings. NFCI. (details)
  119. Merge isVectorType() and getAs<VectorType> calls to silence clang static (details)
  120. Fix cppcheck uninitialized variable in DiffTree() constructor warning. (details)
  121. [RISCV] Handle globals and block addresses in asm operands (details)
  122. [Clang][Driver] Re-use the calling process instead of creating a new (details)
  123. [mlir][Linalg] Update ReshapeOp::build to be more idiomatic (details)
  124. [Inlining] Add PreInlineThreshold for the new pass manager (details)
  125. [mlir] Added missing GPU lowering ops. (details)
  126. [mlir] m_Constant() (details)
  127. [DebugInfo] Make debug line address size mismatch non-fatal to parsing (details)
  128. [ThinLTO] Add additional ThinLTO pipeline testing with new PM (details)
  129. [AArch64][SVE] Add patterns for some arith SVE instructions. (details)
  130. [Scheduler] Remove superfluous casts. NFC (details)
  131. [X86] Add AVX2 known signbits codegen tests (details)
  132. [X86][SSE] Add sitofp(ashr(x,y)) test case with non-uniform shift value (details)
  133. [SelectionDAG] ComputeNumSignBits add (details)
  134. [LegalizeTypes] Add SoftenFloatResult support for (details)
  135. [lldb/Scripts] Remove SWIG bot (details)
  136. Fix tests for builtbot failures (details)
  137. [lldb/Docs] Extend description section of the main page (details)
  138. [X86][SSE] Add sitofp(shl(sext(x),y)) test case with non-uniform shift (details)
  139. AMDGPU/GlobalISel: Simplify assert (details)
  140. AMDGPU/GlobalISel: Fix branch targets when emitting SI_IF (details)
  141. AMDGPU/GlobalISel: Add some baseline tests for vector extract (details)
  142. AMDGPU/GlobalISel: Set insert point after waterfall loop (details)
  143. [SelectionDAG] ComputeNumSignBits add (details)
  144. AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap} (details)
  145. Try number 2 for fixing bot failures (details)
  146. Unbreak the mlir build after 202ab273e6eca134b69882f100c666fcd3affbcf (details)
  147. Fix readability-identifier-naming missing member variables (details)
  148. Hopefully last fix for bot failures (details)
  149. [llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands. (details)
  150. [X86][Disassembler] Fix a bug when disassembling an empty string (details)
  151. Add a couple of missed wildcards in debug-pass-manager output checking (details)
Commit 1d2cd2c0b7d978e22a50e918af708ba67e87c2c1 by maskray
[Driver] Fix OptionClass of -fconvergent-functions and -fms-volatile
(Joined -> Flag)
The file was modifiedclang/include/clang/Driver/Options.td
Commit 9b23407063ca41901e9e272bacf8b33eee8251c4 by saar
[Concepts] Fix MarkUsedTemplateParameters for exprs
D41910 introduced a recursive visitor to MarkUsedTemplateParameters, but
disregarded the 'Depth' parameter, and had incorrect assertions. This
fixes the visitor and removes the assertions.
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
Commit de0a2247115729eade8249267a47f96f070a7666 by alexandre.ganea
Remove umask tests
These tests were added in 18627115f4d2db5dc73207e0b5312f52536be7dd and
e08b59f81d950bd5c8b8528fcb3ac4230c7b736c for validating a refactoring.
Removing because they break on ACL-controlled folders on Ubuntu, and
their added value is low.
Differential Revision: https://reviews.llvm.org/D70854
The file was removedclang/test/Misc/permissions.cpp
The file was removedllvm/test/Other/umask.ll
Commit 7c816492197aefbaa2ea3ba0e391f7c6905956bc by Tom.Tan
[COFF] Align ARM64 range extension thunks at instruction boundary
RangeExtensionThunkARM64 is created for out-of-range branches on Windows
ARM64 because branch instructions has limited bits to encode target
address. Currently, RangeExtensionThunkARM64 is appended to its
referencing COFF section from object file at link time without any
alignment requirement, so if size of the preceding COFF section is not
aligned to instruction boundary (4 bytes), RangeExtensionThunkARM64 will
emit thunk instructions at unaligned address which is never a valid
branch target on ARM64, and usually triggers invalid instruction
exception when branching to it.
This PR fixes it by requiring such thunks to align at 4 bytes.
Differential revision: https://reviews.llvm.org/D72473
The file was modifiedlld/COFF/Chunks.h
The file was modifiedlld/test/COFF/arm64-thunks.s
Commit bb2553175ac3cc6223ff379b266ee1c23a468d66 by craig.topper
[TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare
from RunttimeLibcalls.def and all associated usages
Summary: This always just used the same libcall as unordered, but the
comparison predicate was different. This change appears to have been
made when targets were given the ability to override the predicates.
Before that they were hardcoded into the type legalizer. At that time we
never inverted predicates and we handled ugt/ult/uge/ule compares by
emitting an unordered check ORed with a ogt/olt/oge/ole checks. So only
ordered needed an inverted predicate. Later ugt/ult/uge/ule were
optimized to only call a single libcall and invert the compare.
This patch removes the ordered entries and just uses the inverting logic
that is now present. This removes some odd things in both the Mips and
WebAssembly code.
Reviewers: efriedma, ABataev, uweigand, cameron.mcinally, kpn
Reviewed By: efriedma
Subscribers: dschuff, sdardis, sbc100, arichardson, jgravelle-google,
kristof.beyls, hiraditya, aheejin, sunfish, atanasyan, Petar.Avramovic,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72536
The file was modifiedllvm/lib/Target/Mips/Mips16ISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMLegalizerInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
The file was modifiedllvm/include/llvm/IR/RuntimeLibcalls.def
Commit a701be8f036accef9a3dab62fa4baa70ea330a80 by czhengsz
[SCEV] [NFC] add more test cases for range of addrecexpr with nsw flag
The file was modifiedllvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
Commit 4134d706d9bc48d1634e0d95a5c1698f5fcfd06e by qiucofan
[NFC] [PowerPC] Update mi-peephole-splat test
Use script to re-generate the test case, for easier comparison with
future patches.
The file was modifiedllvm/test/CodeGen/PowerPC/mi-peephole-splat.ll
Commit 4a32cd11acd7c38f5e0b587d724935ab7a9938a6 by mjbedy
[AMDGPU] Remove unnecessary v_mov from a register to itself in WQM
lowering.
Summary:
- SI Whole Quad Mode phase is replacing WQM pseudo instructions with
v_mov instructions. While this is necessary for the special handling of
moving results out of WWM live ranges, it is not necessary for WQM live
ranges. The result is a v_mov from a register to itself after every WQM
operation. This change uses a COPY psuedo in these cases, which allows
the register allocator to coalesce the moves away.
Reviewers: tpr, dstuttard, foad, nhaehnle
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl,
dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71386
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
Commit 695804508db048fe3403f2b8bc690633a471a40b by Amara Emerson
Mark the test/Feature/load_extension.ll test as unsupported on Darwin.
With plugins and examples enabled, this XPASSes. Mark it as unsupported
until the owner investigates what's going on.
The file was modifiedllvm/test/Feature/load_extension.ll
Commit 69806808b918adc9b24bee05654b1d6dad91ef74 by craig.topper
[X86] Use ReplaceAllUsesWith instead of ReplaceAllUsesOfValueWith to
simplify some code. NFCI
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit fcad5b298c7859d7f10908fab7b82983e286bb8d by maskray
[X86][Disassembler] Simplify readPrefixes
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
Commit 5fe5c0a60f9a5f32da4316ba0d1732a1e439703b by craig.topper
[X86] Preserve fpexcept property when turning strict_fp_extend and
strict_fp_round into stack operations.
We use the stack for X87 fp_round and for moving from SSE f32/f64 to X87
f64/f80. Or from X87 f64/f80 to SSE f32/f64.
Note for the SSE<->X87 conversions the conversion always happens in the
X87 domain. The load/store ops in the X87 instructions are able to
signal exceptions.
The file was modifiedllvm/lib/Target/X86/X86InstrFPStack.td
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit c2ddfa876fa90008f1b4ff611256ad5dd4b36d96 by craig.topper
[X86] Simplify code by removing an unreachable condition. NFCI
For X87<->SSE conversions, the SSE type is always smaller than the X87
type. So we can always use the smallest type for the memory type.
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 60346bdbd73da9c944d50ea5dcecad71a05105ac by csigg
Add test for GDB pretty printers.
Reviewers: dblaikie, aprantl, davide, JDevlieghere
Reviewed By: aprantl
Subscribers: jmorse, aprantl, merge_guards_bot, mgorny, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72321
The file was addeddebuginfo-tests/llvm-prettyprinters/gdb/prettyprinters.gdb
The file was modifieddebuginfo-tests/CMakeLists.txt
The file was modifieddebuginfo-tests/lit.cfg.py
The file was addeddebuginfo-tests/llvm-prettyprinters/gdb/prettyprinters.cpp
The file was addeddebuginfo-tests/llvm-prettyprinters/gdb/lit.local.cfg
Commit 81a3d987ced0905bef2e3055bf77ec174bb631c7 by craig.topper
[X86] Remove dead code from X86DAGToDAGISel::Select that is no longer
needed now that we don't mutate strict fp nodes. NFC
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 0e322c8a1f20ab04ce4f6bc538846859707f2d69 by nikita.ppv
[InstCombine] Preserve nuw on sub of geps (PR44419)
Fix https://bugs.llvm.org/show_bug.cgi?id=44419 by preserving the nuw on
sub of geps. We only do this if the offset has a multiplication as the
final operation, as we can't be sure the operations is nuw in the other
cases without more thorough analysis.
Differential Revision: https://reviews.llvm.org/D72048
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/test/Transforms/InstCombine/sub-gep.ll
Commit ad36d29eaed62e33eabab8ffd2006b9ff5fbd719 by nikita.ppv
[LoopSimplify] Regenerate test checks; NFC
For D72519.
The file was modifiedllvm/test/Transforms/LoopSimplify/basictest.ll
Commit 142ba7d76af4a66037fd180db371da19f35ef5f3 by nikita.ppv
[LoopRotate] Add tests for rotate with switch; NFC
For D72420.
The file was addedllvm/test/Transforms/LoopRotate/switch.ll
Commit 87407fc03c82d880cc42330a8e230e7a48174e3c by nunoplopes
DSE: fix bug where we would only check libcalls for name rather than
whole decl
The file was modifiedllvm/test/Transforms/DeadStoreElimination/libcalls.ll
The file was addedllvm/test/Transforms/DeadStoreElimination/libcalls2.ll
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Commit 5d069f4314a0d8b124a563e61d161c3c3d3b0536 by flo
[X86] Add more complex tests for vector masks used with AND/OR/XOR.
Additional test cases for D72524.
The file was modifiedllvm/test/CodeGen/X86/v8i1-masks.ll
Commit ce35010d782cb5a69102ad7785eb747f6d747eb4 by llvm-dev
[X86][AVX] Add lowerShuffleAsLanePermuteAndSHUFP lowering
Add initial support for lowering v4f64 shuffles to SHUFPD(VPERM2F128(V1,
V2), VPERM2F128(V1, V2)), eventually this could be used for v8f32 (and
maybe v8f64/v16f32) but I'm being conservative for the initial
implementation as only v4f64 can always succeed.
This currently is only called from lowerShuffleAsLanePermuteAndShuffle
so only gets used for unary shuffles, and we limit this to cases where
we use upper elements as otherwise concating 2 xmm shuffles is probably
the better case.
Helps with poor shuffles mentioned in D66004.
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 08275a52d83e623f0347fd9396c18f4d21a15c90 by llvm-dev
Fix copy+paste typo in shuffle test name
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
Commit 9c74fb402e1b7aad4a509a49ab4792154b8ba2c8 by koraq
[Sema] Improve -Wrange-loop-analysis warnings.
No longer generate a diagnostic when a small trivially copyable type is
used without a reference. Before the test looked for a POD type and had
no size restriction. Since the range-based for loop is only available in
C++11 and POD types are trivially copyable in C++11 it's not required to
test for a POD type.
Since copying a large object will be expensive its size has been
restricted. 64 bytes is a common size of a cache line and if the object
is aligned the copy will be cheap. No performance impact testing has
been done.
Differential Revision: https://reviews.llvm.org/D72212
The file was modifiedclang/test/SemaCXX/warn-range-loop-analysis.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
The file was addedclang/test/SemaCXX/warn-range-loop-analysis-trivially-copyable.cpp
Commit 24763734e7f45e3b60118b28987685d42e7a761f by llvm-dev
[X86] Fix outdated comment
The generic saturated math opcodes are no longer widened inside
X86TargetLowering
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit a8ed86b5c705cf1d2f3ca55b0640cf0f2fe01abc by llvm-dev
moveOperands - assert Src/Dst MachineOperands are non-null.
Fixes static-analyzer warnings.
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
Commit 7c7ca515837305f5d14033aee1191c254b86063c by benny.kra
Remove copy ctors identical to the default one. NFC.
Those do nothing but make the type no longer trivial to the compiler.
The file was modifiedmlir/include/mlir/IR/AffineExpr.h
The file was modifiedmlir/include/mlir/IR/IntegerSet.h
The file was modifiedmlir/include/mlir/IR/AffineMap.h
Commit 2740b2d5d5f0f56c87024555bdcae4f91e595ddb by llvm-dev
Fix uninitialized value clang static analyzer warning. NFC.
The file was modifiedllvm/lib/Transforms/Utils/CodeExtractor.cpp
Commit ded237b58d56299f90ef44853ef79b039248b85e by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use castAs<> instead of getAs<> since the pointer is dereferenced
immediately below and castAs will perform the null assertion for us.
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit 16c53ffcb9d040f0396bf1ab42ca366f7e1f1e4d by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use castAs<> instead of getAs<> since the pointer is dereferenced
immediately below and castAs will perform the null assertion for us.
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/lib/CodeGen/CGExprCXX.cpp
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
Commit d87a76c9dae38b2a1ef63584aee82e74490dc83b by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use castAs<> instead of getAs<> since the pointer is dereferenced
immediately within mangleCallingConvention and castAs will perform the
null assertion for us.
The file was modifiedclang/lib/AST/MicrosoftMangle.cpp
Commit 93431f96a7b14ff03036bae77cc0197fdc98ad52 by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use cast<> instead of dyn_cast<> since we know that the pointer should
be valid (and is dereferenced immediately).
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
Commit bf03944d5d9a7e7c8105c69dfa0d7e0d345644df by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use castAs<> instead of getAs<> since the pointers are dereferenced
immediately and castAs will perform the null assertion for us.
The file was modifiedclang/lib/Sema/SemaCodeComplete.cpp
Commit fce887beb79780d0e0b19e8ab6176978a3dce9b8 by llvm-dev
GlobalModuleIndex - Fix use-after-move clang static analyzer warning.
Shadow variable names meant we were referencing the Buffer input
argument, not the GlobalModuleIndex member that its std::move()'d it.
The file was modifiedclang/lib/Serialization/GlobalModuleIndex.cpp
Commit 6cb3957730e9085bb7c37d871c790f910efdd6a7 by listmail
[X86AsmBackend] Be consistent about placing definitions out of line
[NFC]
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Commit 563d3e344452c8923db09b043b8db471fc413b1e by listmail
[X86AsmBackend] Move static function before sole use [NFC]
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Commit 1d641daf260308815d014d1bf1b424a1ed1e7277 by listmail
[X86] Adjust nop emission by compiler to consider target decode
limitations
The primary motivation of this change is to bring the code more closely
in sync behavior wise with the assembler's version of nop emission.  I'd
like to eventually factor them into one, but that's hard to do when one
has features the other doesn't.
The longest encodeable nop on x86 is 15 bytes, but many processors - for
instance all intel chips - can't decode the 15 byte form efficiently.
On those processors, it's better to use either a 10 byte or 11 byte
sequence depending.
The file was modifiedllvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll
The file was modifiedllvm/test/CodeGen/X86/stackmap-nops.ll
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
The file was modifiedllvm/test/MC/X86/stackmap-nops.ll
Commit 2bdf33cc4c733342fc83081bc7410ac5e9a24f55 by riverriddle
[mlir] NFC: Remove Value::operator* and Value::operator-> now that Value
is properly value-typed.
Summary: These were temporary methods used to simplify the transition.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D72548
The file was modifiedmlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/Ops.td
The file was modifiedmlir/lib/Transforms/LoopInvariantCodeMotion.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp
The file was modifiedmlir/lib/Dialect/Linalg/EDSC/Builders.cpp
The file was modifiedmlir/examples/toy/Ch5/mlir/ToyCombine.td
The file was modifiedmlir/lib/Transforms/MemRefDataFlowOpt.cpp
The file was modifiedmlir/examples/toy/Ch4/mlir/ToyCombine.td
The file was modifiedmlir/lib/Dialect/StandardOps/Ops.cpp
The file was modifiedmlir/lib/Analysis/CallGraph.cpp
The file was modifiedmlir/examples/toy/Ch3/mlir/ToyCombine.td
The file was modifiedmlir/examples/toy/Ch6/mlir/ToyCombine.td
The file was modifiedmlir/lib/EDSC/Helpers.cpp
The file was modifiedmlir/lib/Quantizer/Transforms/AddDefaultStatsTestPass.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/include/mlir/Dialect/VectorOps/VectorTransformPatterns.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/LinalgTransformPatterns.td
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/include/mlir/IR/Matchers.h
The file was modifiedmlir/examples/toy/Ch3/mlir/ToyCombine.cpp
The file was modifiedmlir/lib/Dialect/FxpMathOps/Transforms/UniformKernelUtils.h
The file was modifiedmlir/lib/Dialect/SPIRV/Transforms/DecorateSPIRVCompositeTypeLayoutPass.cpp
The file was modifiedmlir/lib/Dialect/LoopOps/LoopOps.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
The file was modifiedmlir/lib/Quantizer/Support/ConstraintAnalysisGraph.cpp
The file was modifiedmlir/test/mlir-tblgen/op-result.td
The file was modifiedmlir/lib/Dialect/VectorOps/VectorTransforms.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was modifiedmlir/include/mlir/EDSC/Intrinsics.h
The file was modifiedmlir/examples/toy/Ch3/mlir/Dialect.cpp
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/lib/Dialect/AffineOps/AffineOps.cpp
The file was modifiedmlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp
The file was modifiedmlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
The file was modifiedmlir/tools/mlir-tblgen/RewriterGen.cpp
The file was modifiedmlir/examples/toy/Ch5/mlir/ToyCombine.cpp
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/Ops.h
The file was modifiedmlir/examples/toy/Ch6/mlir/Dialect.cpp
The file was modifiedmlir/docs/DeclarativeRewrites.md
The file was modifiedmlir/lib/EDSC/Builders.cpp
The file was modifiedmlir/lib/Analysis/LoopAnalysis.cpp
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/examples/toy/Ch6/mlir/ToyCombine.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/LinalgTransforms.cpp
The file was modifiedmlir/examples/toy/Ch4/mlir/Dialect.cpp
The file was modifiedmlir/lib/Transforms/Utils/Utils.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/Dialect.cpp
The file was modifiedmlir/lib/Quantizer/Configurations/FxpMathConfig.cpp
The file was modifiedmlir/include/mlir/Transforms/RegionUtils.h
The file was modifiedmlir/test/lib/TestDialect/TestDialect.cpp
The file was modifiedmlir/include/mlir/Dialect/AffineOps/AffineOps.h
The file was modifiedmlir/lib/Transforms/LoopUnrollAndJam.cpp
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
The file was modifiedmlir/lib/Transforms/PipelineDataTransfer.cpp
The file was modifiedmlir/include/mlir/Analysis/Dominance.h
The file was modifiedmlir/lib/Analysis/VectorAnalysis.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/docs/QuickstartRewrites.md
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/lib/Analysis/Dominance.cpp
The file was modifiedmlir/test/lib/TestDialect/TestPatterns.cpp
The file was modifiedmlir/lib/Analysis/Verifier.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/test/lib/TestDialect/TestOps.td
The file was modifiedmlir/examples/toy/Ch4/mlir/ToyCombine.cpp
The file was modifiedmlir/include/mlir/EDSC/Builders.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/EDSC/Builders.h
The file was modifiedmlir/lib/Transforms/LoopTiling.cpp
The file was modifiedmlir/include/mlir/IR/Operation.h
The file was modifiedmlir/lib/Transforms/Vectorize.cpp
The file was modifiedmlir/lib/Analysis/SliceAnalysis.cpp
The file was modifiedmlir/docs/Tutorials/Toy/Ch-4.md
The file was modifiedmlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
The file was modifiedmlir/lib/IR/Region.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h
The file was modifiedmlir/lib/Dialect/QuantOps/Transforms/ConvertConst.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/ToyCombine.cpp
The file was modifiedmlir/lib/Conversion/GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp
The file was modifiedmlir/lib/Transforms/Utils/LoopFusionUtils.cpp
The file was modifiedmlir/examples/toy/Ch2/mlir/Dialect.cpp
The file was modifiedmlir/examples/toy/Ch5/mlir/Dialect.cpp
The file was modifiedmlir/lib/Transforms/AffineLoopInvariantCodeMotion.cpp
The file was modifiedmlir/lib/IR/Operation.cpp
The file was modifiedmlir/lib/Dialect/QuantOps/IR/QuantOps.cpp
The file was modifiedmlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
The file was modifiedmlir/include/mlir/IR/Value.h
The file was modifiedmlir/lib/IR/Value.cpp
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp
The file was modifiedmlir/test/mlir-tblgen/predicate.td
The file was modifiedmlir/lib/Transforms/Utils/RegionUtils.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/MLIRGen.cpp
The file was modifiedmlir/test/lib/Transforms/TestInlining.cpp
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
The file was modifiedmlir/lib/IR/TypeUtilities.cpp
The file was modifiedmlir/lib/IR/Function.cpp
The file was modifiedmlir/include/mlir/Quantizer/Support/ConstraintAnalysisGraph.h
The file was modifiedmlir/lib/IR/Block.cpp
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/ToyCombine.td
The file was modifiedmlir/lib/Analysis/AffineAnalysis.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp
The file was modifiedmlir/docs/Tutorials/Toy/Ch-3.md
The file was modifiedmlir/test/lib/Transforms/TestVectorizationUtils.cpp
The file was modifiedmlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp
The file was modifiedmlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
The file was modifiedmlir/lib/Dialect/Traits.cpp
The file was modifiedmlir/lib/Analysis/Liveness.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/lib/Analysis/Utils.cpp
The file was modifiedmlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp
The file was modifiedmlir/lib/Dialect/VectorOps/VectorOps.cpp
The file was modifiedmlir/include/mlir/Dialect/AffineOps/AffineOps.td
The file was modifiedmlir/include/mlir/Dialect/QuantOps/QuantOps.td
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/lib/IR/Builders.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
The file was modifiedmlir/include/mlir/Dialect/VectorOps/VectorOps.td
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/lib/IR/PatternMatch.cpp
The file was modifiedmlir/lib/Transforms/DialectConversion.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVDialect.cpp
The file was modifiedmlir/lib/Transforms/Utils/InliningUtils.cpp
The file was modifiedmlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp
The file was modifiedmlir/lib/Transforms/LoopFusion.cpp
The file was modifiedmlir/lib/Transforms/Utils/FoldUtils.cpp
The file was modifiedmlir/include/mlir/IR/OpDefinition.h
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
Commit 4c48ea68e491cb42f1b5d43ffba89f6a7f0dadc4 by development
[ASTMatchers] extract public matchers from const-analysis into own patch
Summary: The analysis for const-ness of local variables required a view
generally useful matchers that are extracted into its own patch.
They are `decompositionDecl` and `forEachArgumentWithParamType`, that
works for calls through function pointers as well.
Reviewers: aaron.ballman
Reviewed By: aaron.ballman
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72505
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
The file was modifiedclang/docs/LibASTMatchersReference.html
The file was modifiedclang/lib/ASTMatchers/Dynamic/Registry.cpp
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
Commit 23a799adf0abbe9a7be1494d5efd1ab3215ee4fb by development
Revert "[ASTMatchers] extract public matchers from const-analysis into
own patch"
This reverts commit 4c48ea68e491cb42f1b5d43ffba89f6a7f0dadc4. The
powerpc buildbots had an internal compiler error after this patch. This
requires some inspection.
The file was modifiedclang/docs/LibASTMatchersReference.html
The file was modifiedclang/lib/ASTMatchers/Dynamic/Registry.cpp
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Commit d2751f8fdf6c072045bab62f6035511e028f46ee by Lang Hames
[ExecutionEngine] Re-enable FastISel for non-iOS arm targets.
Patch by Nicolas Capens. Thanks Nicolas!
https://reviews.llvm.org/D65015
The file was modifiedllvm/lib/ExecutionEngine/TargetSelect.cpp
Commit dc422e968e73790178e500f506e8fb7cfa1e62ea by koraq
Add -Wrange-loop-analysis changes to ReleaseNotes
This reflects the recent changes done.
The file was modifiedclang/docs/ReleaseNotes.rst
Commit 9cc9120969fd9f7f6a99321c7d94133a32927a3a by craig.topper
[X86] Turn FP_ROUND/STRICT_FP_ROUND into
X86ISD::VFPROUND/STRICT_VFPROUND during PreprocessISelDAG to remove some
duplicate isel patterns.
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit a5994c789a2982a770254ae1607b5b4cb641f73c by maskray
[X86][Disassembler] Simplify and optimize reader functions
llvm-objdump -d on clang is decreased from 8.2s to 7.8s.
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
Commit 9fe6f36c1a909e381275f897b780a9c878fab94a by craig.topper
[LegalizeVectorOps] Only pass SDNode* instead SDValue to all of the
Expand* and Promote* methods.
All the Expand* and Promote* function assume they are being called with
result 0 anyway. Just hardcode result 0 into them.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit 5a9954c02a7d6e60da26b2feec0837695846aeed by craig.topper
[LegalizeVectorOps] Remove some of the simpler Expand methods. Pass
Results vector to a couple. NFCI
Some of the simplest handlers just call TLI and if that fails, they fall
back to unrolling. For those just inline the TLI call and share the
unrolling call with the default case of Expand.
For ExpandFSUB and ExpandBITREVERSE so that its obvious they don't
return results sometimes and want to defer to LegalizeDAG.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit 179abb091d8a1d67115d21b54001d10250756042 by maskray
[X86][Disassembler] Replace custom logger with LLVM_DEBUG
llvm-objdump -d on clang is decreased from 7.8s to 7.4s.
The improvement is likely due to the elimination of logger setup and
dbgprintf(), which has a large overhead.
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
Commit a1f16998f371870ca4da8b3c00a093c607a36ddd by alexandre.ganea
[Support] Optionally call signal handlers when a function wrapped by the
the CrashRecoveryContext fails
This patch allows for handling a failure inside a CrashRecoveryContext
in the same way as the global exception/signal handler. A failure will
have the same side-effect, such as cleanup of temporarty file, printing
callstack, calling relevant signal handlers, and finally returning an
exception code. This is an optional feature, disabled by default. This
is a support patch for D69825.
Differential Revision: https://reviews.llvm.org/D70568
The file was modifiedllvm/unittests/Support/CrashRecoveryTest.cpp
The file was modifiedllvm/include/llvm/Support/Signals.h
The file was modifiedllvm/lib/Support/Unix/Signals.inc
The file was modifiedllvm/lib/Support/CrashRecoveryContext.cpp
The file was modifiedllvm/lib/Support/Windows/Signals.inc
The file was modifiedllvm/include/llvm/Support/CrashRecoveryContext.h
Commit 2cdb18afda841392002feafda21af31854c195b3 by Lang Hames
[ORC] Fix argv handling in runAsMain / lli.
This fixes an off-by-one error in the argc value computed by runAsMain,
and switches lli back to using the input bitcode (rather than the string
"lli") as the effective program name.
Thanks to Stefan Graenitz for spotting the bug.
The file was modifiedllvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
The file was addedllvm/test/ExecutionEngine/OrcLazy/printargv.ll
The file was modifiedllvm/tools/lli/lli.cpp
Commit 6fdd6a7b3f696972edc244488f59532d05136a27 by maskray
[Disassembler] Delete the VStream parameter of
MCDisassembler::getInstruction()
The argument is llvm::null() everywhere except llvm::errs() in
llvm-objdump in -DLLVM_ENABLE_ASSERTIONS=On builds. It is used by no
target but X86 in -DLLVM_ENABLE_ASSERTIONS=On builds.
If we ever have the needs to add verbose log to disassemblers, we can
record log with a member function, instead of passing it around as an
argument.
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modifiedllvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
The file was modifiedllvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h
The file was modifiedllvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
The file was modifiedllvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h
The file was modifiedllvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/Analysis.cpp
The file was modifiedllvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
The file was modifiedllvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
The file was modifiedllvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
The file was modifiedllvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp
The file was modifiedllvm/tools/llvm-mc/Disassembler.cpp
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
The file was modifiedlldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
The file was modifiedllvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
The file was modifiedllvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
The file was modifiedllvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
The file was modifiedllvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
The file was modifiedlldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
The file was modifiedlldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
The file was modifiedllvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
The file was modifiedllvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
The file was modifiedllvm/tools/sancov/sancov.cpp
The file was modifiedllvm/lib/MC/MCDisassembler/Disassembler.cpp
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was modifiedllvm/lib/MC/MCDisassembler/MCDisassembler.cpp
The file was modifiedllvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
Commit 1e8ce7492e91aa6db269334d12187c7ae854dccb by maskray
[X86][Disassembler] Optimize argument passing and immediate reading
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
Commit f719c540bb09cb5bfe37bc6283ea68e31949b3f4 by maskray
[X86][Disassembler] Shrink X86GenDisassemblerTables.inc from 36M to 6.1M
In x86Disassembler{OneByte,TwoByte,...}Codes,
"/* EmptyTable */" is very common. Omitting it saves lots of space.
Also, there is no need to display a table entry in multiple lines.
It is also common that the whole OpcodeDecision is { MODRM_ONEENTRY, 0}.
Make use of zero-initialization.
The file was modifiedllvm/utils/TableGen/X86DisassemblerTables.cpp
Commit ddfcd82bdc219dd2dc04d6826c417cea3da65d12 by craig.topper
[LegalizeVectorOps] Expand vector MERGE_VALUES immediately.
Custom legalization can produce MERGE_VALUES to return multiple results.
We can expand them immediately instead of leaving them around for DAG
combine to clean up.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit ed679804d5e34dcb1046c5087acaf5d1dbb9b582 by craig.topper
[TargetLowering][X86] Connect the chain from STRICT_FSETCC in
TargetLowering::expandFP_TO_UINT and X86TargetLowering::FP_TO_INTHelper.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit efb674ac2f2b0f06adc3f00df3134dadf1c875df by craig.topper
[LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UINT_TO_FLOAT
legalization.
The lo and hi computation are independent. Give them the same input
chain and TokenFactor the results together.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit 569ccfc384a5434c35c09adba8c44c46014297e6 by czhengsz
[SCEV] more accurate range for addrecexpr with nsw flag.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D72436
The file was modifiedllvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit d692f0f6c8c12316d559b9a638a2cb9fbd0c263d by craig.topper
[X86] Don't call LowerSETCC from LowerSELECT for
STRICT_FSETCC/STRICT_FSETCCS nodes.
This causes the STRICT_FSETCC/STRICT_FSETCCS nodes to lowered early
while lowering SELECT, but the output chain doesn't get connected. Then
we visit the node again when it is its turn because we haven't replaced
the use of the chain result. In the case of the fp128 libcall lowering,
after D72341 this will cause the libcall to be emitted twice.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit f33fd43a7c91f1774a9512bbdb78c367cd23d233 by qiucofan
[NFC] Refactor memory ops cluster method
Current implementation of BaseMemOpsClusterMutation is a little bit
obscure. This patch directly uses a map from store chain ID to set of
memory instrs to make it simpler, so that future improvements are easier
to read, update and review.
Reviewed By: evandro
Differential Revision: https://reviews.llvm.org/D72070
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
Commit c5b94ea265133a4a28006929643155fc8fbeafe6 by maskray
[profile] Support merge pool size >= 10
The executable acquires an advisory record lock (`fcntl(fd, F_SETLKW,
*)`) on a profile file. Merge pool size >= 10 may be beneficial when the
concurrency is large.
Also fix a small problem about snprintf. It can cause the filename to be
truncated after %m.
Reviewed By: davidxl
Differential Revision: https://reviews.llvm.org/D71970
The file was modifiedcompiler-rt/test/profile/instrprof-basic.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingFile.c
Commit 51c1d7c4bec025f70679284060b82c05242759b2 by maskray
[X86][Disassembler] Simplify
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
Commit 60cc095ecc34d72a9ac6947f39c6e2a0cdf5449f by maskray
[X86][Disassembler] Merge X86DisassemblerDecoder.cpp into
X86Disassembler.cpp and refactor
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/CMakeLists.txt
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
The file was removedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/X86/Disassembler/BUILD.gn
Commit b375f28b0ec1129a4b94770a9c55ba49222ea1dd by llvm-dev
[X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the demanded
elements of the lane mask.
Fixes an cyclic dependency issue with an upcoming patch where
getVectorShuffle canonicalizes masks with splat build vector sources.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 66e39067edbfdb1469be001ebb053530a608b532 by llvm-dev
[X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower binary v4f64
shuffles.
Only perform this if we are shuffling lower and upper lane elements
across the lanes (otherwise splitting to lower xmm shuffles would be
better).
This is a regression if we shuffle build_vectors due to getVectorShuffle
canonicalizing 'blend of splat' build vectors, for now I've set this not
to shuffle build_vector nodes at all to avoid this.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/subvector-broadcast.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
The file was modifiedllvm/test/CodeGen/X86/avx-unpack.ll
Commit 065eefcfe969249a7df9d1ef4a0e468606b25359 by llvm-dev
[AMDGPU] Regenerate shl shift tests
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
Commit a888277897f75b2952d96de229fff57519cfc363 by llvm-dev
[MIPS] Regenerate shl/lshr shift tests
The file was modifiedllvm/test/CodeGen/Mips/llvm-ir/lshr.ll
The file was modifiedllvm/test/CodeGen/Mips/llvm-ir/shl.ll
Commit ad201691d5cc0f15f6f885f3847dcc6440ee3de5 by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use cast<> instead of dyn_cast<> and move into its users where its
dereferenced immediately.
The file was modifiedclang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
Commit ebd26cc8c434f40fe8079ee823e7657b5138769f by maskray
[PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin
Darwin support has been removed.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D72063
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
The file was removedllvm/test/MC/MachO/PowerPC/lit.local.cfg
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was removedllvm/test/MC/PowerPC/ppc-separator.s
The file was removedllvm/test/CodeGen/PowerPC/hello-reloc.s
The file was removedllvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s
Commit de797ccdd74f46d5f637ccf66c78da9905a46f42 by alexandre.ganea
[NFC] Fix compilation of CrashRecoveryContext.cpp on mingw
Patch by Markus Böck.
Differential Revision: https://reviews.llvm.org/D72564
The file was modifiedllvm/lib/Support/CrashRecoveryContext.cpp
Commit 7fa5290d5bd5632d7a36a4ea9f46e81e04fb819e by maskray
__patchable_function_entries: don't use linkage field 'unique' with
-no-integrated-as
.section name, "flags"G, @type, GroupName[, linkage]
As of binutils 2.33, linkage cannot be 'unique'.  For integrated
assembler, we use both 'o' flag and 'unique' linkage to support
--gc-sections and COMDAT with lld.
https://sourceware.org/ml/binutils/2019-11/msg00266.html
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/AArch64/patchable-function-entry.ll
Commit 241f330d6bab52ab4e3a01cbb9a3edd417d07c59 by jay.foad
[AMDGPU] Add gfx8 assembler and disassembler test cases
Summary: This adds assembler tests for cases that were previously only
in the disassembler tests, and vice versa.
Reviewers: rampitec, arsenm, nhaehnle
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye,
jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72561
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
The file was modifiedllvm/test/MC/AMDGPU/gfx8_asm_all.s
Commit 2bfee35cb860859b436de0b780fbd00d68e198a4 by maskray
[MC][ELF] Emit a relocation if target is defined in the same section and
is non-local
For a target symbol defined in the same section, currently we don't emit
a relocation if VariantKind is VK_None (with few exceptions like RISC-V
relaxation), while GNU as emits one. This causes program behavior
differences with and without -ffunction-sections, and can break intended
symbol interposition in a -shared link.
```
.globl foo foo:
call foo      # no relocation. On other targets, may be written as b
foo, etc
call bar      # a relocation if bar is in another section (e.g.
-ffunction-sections)
call foo@plt  # a relocation
```
Unify these cases by always emitting a relocation. If we ever want to
optimize `call foo` in -shared links, we should emit a STB_LOCAL alias
and call via the alias.
ARM/thumb2-beq-fixup.s: we now emit a relocation to global_thumb_fn as
GNU as does. X86/Inputs/align-branch-64-2.s: we now emit R_X86_64_PLT32
to foo as GNU does.
ELF/relax.s: rewrite the test as target-in-same-section.s . We omitted
relocations to `global` and now emit R_X86_64_PLT32. Note, GNU as does
not emit a relocation for `jmp global` (maybe its own bug). Our new
behavior is compatible except `jmp global`.
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D72197
The file was modifiedlld/test/ELF/global-offset-table-position-aarch64.s
The file was addedllvm/test/MC/ELF/target-in-same-section.s
The file was modifiedllvm/test/MC/ARM/thumb1-branch-reloc.s
The file was modifiedllvm/test/MC/X86/align-branch-64-2b.s
The file was removedllvm/test/MC/ELF/relax.s
The file was modifiedllvm/test/MC/X86/align-branch-64-2a.s
The file was modifiedllvm/test/MC/X86/align-branch-64-2c.s
The file was modifiedllvm/test/MC/ARM/thumb2-beq-fixup.s
The file was modifiedllvm/lib/MC/ELFObjectWriter.cpp
Commit ada22c804cd956f3ee7cc9dc82e6d54ead8a4ffe by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
The file was modifiedclang/include/clang/Basic/SourceManager.h
Commit 54b2914accb4f5c9b58305fd6da405d20a47c452 by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use castAs<> instead of getAs<> since the pointers are dereferenced
immediately and castAs will perform the null assertion for us.
The file was modifiedclang/lib/AST/VTableBuilder.cpp
Commit 0113cf193f0610bb1a5dfa0bcd29c41a8965938a by jrtc27
[RISCV] Check register class for AMO memory operands
Summary: AMO memory operands use a custom parser in order to accept both
(reg) and 0(reg). However, the validation predicate used for these
operands was only checking that they were registers, and not the
register class, so non-GPRs (such as FPRs) were also accepted. Thus, fix
this by making the predicate check that they are GPRs.
Reviewers: asb, lenary
Reviewed By: asb, lenary
Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD,
kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01,
MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna,
Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72471
The file was modifiedllvm/test/MC/RISCV/rva-aliases-invalid.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoA.td
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit a6342c247a17fb270e0385bd1deb463b7309a43b by czhengsz
[SCEV] accurate range for addrecexpr with nuw flag
If addrecexpr has nuw flag, the value should never be less than its
start value and start value does not required to be SCEVConstant.
Reviewed By: nikic, sanjoy
Differential Revision: https://reviews.llvm.org/D71690
The file was modifiedllvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 1ad1308b69b89cc87533c16957189a84e1dd9754 by zeratul976
[clangd] Assert that the testcases in FindExplicitReferencesTest.All
have no diagnostics
Reviewers: kadircet
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95,
cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72355
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
Commit 79a09d8bf4d508b0ae6a1e3c90907488092678c5 by zeratul976
[clangd] Show template arguments in type hierarchy when possible
Summary: Fixes https://github.com/clangd/clangd/issues/31
Reviewers: kadircet
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet,
usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D71533
The file was modifiedclang-tools-extra/clangd/unittests/TypeHierarchyTests.cpp
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
Commit a10527cd3731e2ef246c4797fb099385a948f62f by arsenm2
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
getDefIgnoringCopies will fail to find any def if no type is set if we
try to use it on the use's operand, so propagate the type.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 555e7ee04cb5c44e0b11a2eda999e6910b4b27e1 by arsenm2
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
We don't use the xexec register classes for arbitrary values anymore.
Avoids a test variance beween GlobalISel and SelectionDAG>
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
Commit 3c868cbbda7e2ff66b8ed92b632a609aaac324ba by arsenm2
AMDGPU: Split test function
This avoids slightly different scheduling/regalloc behavior, and avoids
a test diff between GlobalISel and SelectionDAG.
The file was modifiedllvm/test/CodeGen/AMDGPU/write_register.ll
Commit 52aaf4a27576607dfc0833f5f88e5a15a30ceadb by craig.topper
[X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes.
At least one of these is used without a Glue. This doesn't seem to
change the X86GenDAGISel.inc output so maybe it doesn't matter?
The file was modifiedllvm/lib/Target/X86/X86InstrFPStack.td
Commit c958639098a8702b831952b1a1a677ae19190a55 by SourabhSingh.Tomar
[DWARF5][DebugInfo]: Added support for DebugInfo generation for auto
return type for C++ member functions.
Summary: This patch will provide support for auto return type for the
C++ member functions. Before this return type of the member function is
deduced and stored in the DIE. This patch includes llvm side
implementation of this feature.
Patch by: Awanish Pandey <Awanish.Pandey@amd.com>
Reviewers: dblaikie, aprantl, shafik, alok, SouraVX, jini.susan.george
Reviewed by: dblaikie
Differential Revision: https://reviews.llvm.org/D70524
The file was addedllvm/test/DebugInfo/X86/debug-info-auto-return.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
Commit 6d6a4590c5d4c7fc7445d72fe685f966b0a8cafb by SourabhSingh.Tomar
[DWARF5][clang]: Added support for DebugInfo generation for auto return
type for C++ member functions.
Summary: This patch will provide support for auto return type for the
C++ member functions.
This patch includes clang side implementation of this feature.
Patch by: Awanish Pandey <Awanish.Pandey@amd.com>
Reviewers: dblaikie, aprantl, shafik, alok, SouraVX, jini.susan.george
Reviewed by: dblaikie
Differential Revision: https://reviews.llvm.org/D70524
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedclang/lib/CodeGen/CGDebugInfo.h
The file was addedclang/test/CodeGenCXX/debug-info-auto-return.cpp
Commit 07028b5a87803a3a857d6dd6320a0f7de4db23ad by sjoerd.meijer
[SCEV] Follow up of D71563: addressing post commit comment. NFC.
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 9d3e78e704fa6201bceb48f45fb061f572c5aa2e by sam.parker
[NFC] Update loop.decrement.reg intrinsic comment
Note that the intrinsic is now understood by SCEV and that other
optimisations can treat it as a sub.
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
Commit 3cad8ada4947dc6793e5af56d6dd0e6eed9e570f by zinenko
Add zero_extendi and sign_extendi to intrinsic namespace
Summary:
- update zero_extendi and sign_extendi in edsc/intrinsic namespace
- Builder API test for zero_extendi and sign_extendi
Differential Revision: https://reviews.llvm.org/D72298
The file was modifiedmlir/include/mlir/EDSC/Intrinsics.h
The file was modifiedmlir/test/EDSC/builder-api-test.cpp
Commit ddf044290ede7d7fd47f4f673e3e628f551a8aac by Raphael Isemann
[lldb] Mark several tests as not dependent on debug info
Summary: This just adds `NO_DEBUG_INFO_TESTCASE` to tests that don't
really exercise anything debug information specific and therefore don't
need to be rerun for all debug information variants.
Reviewers: labath, jingham, aprantl, mib, jfb
Reviewed By: aprantl
Subscribers: dexonsmith, JDevlieghere, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D72447
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/process/TestProcessAPI.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/hello_watchlocation/TestWatchLocation.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_commands/condition/TestWatchpointConditionCmd.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/hello_watchpoint/TestMyFirstWatchpoint.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/findvalue_duplist/TestSBFrameFindValue.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_commands/command/TestWatchpointCommandLLDB.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/formatters/TestFormattersSBAPI.py
The file was modifiedlldb/packages/Python/lldbsuite/test/lang/c/offsetof/TestOffsetof.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/process/io/TestProcessIO.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/sbvalue_persist/TestSBValuePersist.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/value/linked_list/TestValueAPILinkedList.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_disable/TestWatchpointDisable.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/target/create-no-such-arch/TestNoSuchArch.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/watchpoint/watchlocation/TestSetWatchlocation.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/step_over_watchpoint/TestStepOverWatchpoint.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_commands/TestWatchpointCommands.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_commands/command/TestWatchpointCommandPython.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/watchpoint/TestWatchpointIgnoreCount.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/event/TestEvents.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/apropos/with-process/TestAproposWithProcess.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/variable_out_of_scope/TestWatchedVarHitWhenInScope.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/default-constructor/TestDefaultConstructorForAPIObjects.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/command/script_alias/TestCommandScriptAlias.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/statistics/basic/TestStats.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/watchpoint/TestSetWatchpoint.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/debugger/TestDebuggerAPI.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_events/TestWatchpointEvents.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/sbdata/TestSBData.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/signals/TestSignalsAPI.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_on_vectors/TestValueOfVectorVariable.py
The file was modifiedlldb/packages/Python/lldbsuite/test/lang/cpp/offsetof/TestOffsetofCpp.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/rdar-12481949/Test-rdar-12481949.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/watchpoint/condition/TestWatchpointConditionAPI.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/watchpoints/watchpoint_set_command/TestWatchLocationWithWatchSet.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/command/nested_alias/TestNestedAlias.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/process/attach-resume/TestAttachResume.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/expression/calculator_mode/TestCalculatorMode.py
The file was modifiedlldb/packages/Python/lldbsuite/test/python_api/watchpoint/TestWatchpointIter.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/process/launch-with-shellexpand/TestLaunchWithShellExpand.py
Commit c9babcbda77e69698825cfb9ce771352be93acee by selliott
[RISCV] Collect Statistics on Compressed Instructions
Summary: It is useful to keep statistics on how many instructions we
have compressed, so we can see if future changes are increasing or
decreasing this number.
Reviewers: asb, luismarques
Reviewed By: asb, luismarques
Subscribers: xbolva00, sameer.abuasal, hiraditya, rbar, johnrusso,
simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27,
MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult,
the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67495
The file was modifiedllvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit 734aa1d133f264746f721a244d2c66bc99648ee5 by usx
[clangd] Publish xref for macros from Index and AST.
Summary: With this patch the `findReferences` API will return Xref for
macros. If the symbol under the cursor is a macro then we collect the
references to it from: 1. Main file by looking at the ParsedAST. (These
were added to the ParsedAST in https://reviews.llvm.org/D70008) 2. Files
other than the mainfile by looking at the:
* static index (Added in https://reviews.llvm.org/D70489)
* file index (Added in https://reviews.llvm.org/D71406) This patch
collects all the xref from the above places and outputs it in
`findReferences` API.
Reviewers: kadircet
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72395
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
The file was modifiedclang-tools-extra/clangd/unittests/XRefsTests.cpp
Commit e45fcfc3aa57bb237fd4fd694d0c257be66d5482 by sam.mccall
Revert "[DWARF5][clang]: Added support for DebugInfo generation for auto
return type for C++ member functions."
This reverts commit 6d6a4590c5d4c7fc7445d72fe685f966b0a8cafb, which
introduces a crash.
See https://reviews.llvm.org/D70524 for details.
The file was removedclang/test/CodeGenCXX/debug-info-auto-return.cpp
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedclang/lib/CodeGen/CGDebugInfo.h
Commit 96b8e1ac4674dd3035b6cc7b1b7ed8b946208ab1 by pavel
[lldb] Fix eh-frame-small-fde test for changes in lld
lld in 2bfee35 started emitting relocations for some intra-section jumps
between global symbols. This shifted the code around a bit, invalidating
text expectations.
Change the symbols to local to keep the previous behavior.
The file was modifiedlldb/test/Shell/Unwind/Inputs/eh-frame-small-fde.s
Commit 10c11e4e2d05cf0e8f8251f50d84ce77eb1e9b8d by peter.smith
This option allows selecting the TLS size in the local exec TLS model,
which is the default TLS model for non-PIC objects. This allows large/
many thread local variables or a compact/fast code in an executable.
Specification is same as that of GCC. For example, the code model option
precedes the TLS size option.
TLS access models other than local-exec are not changed. It means
supoort of the large code model is only in the local exec TLS model.
Patch By KAWASHIMA Takahiro (kawashima-fj <t-kawashima@fujitsu.com>)
Reviewers: dmgreen, mstorsjo, t.p.northover, peter.smith, ostannard
Reviewd By: peter.smith Committed by: peter.smith
Differential Revision: https://reviews.llvm.org/D71688
The file was removedllvm/test/CodeGen/AArch64/arm64-tls-execs.ll
The file was modifiedllvm/include/llvm/Target/TargetOptions.h
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
The file was addedllvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll
The file was modifiedllvm/include/llvm/CodeGen/CommandFlags.inc
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was addedllvm/test/CodeGen/AArch64/arm64-tls-local-exec.ll
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was addedclang/test/Driver/tls-size.c
Commit add04b9653848de583c542e0596737f7d7c21553 by sjoerd.meijer
ARMLowOverheadLoops: return earlier to avoid printing irrelevant dbg
msg. NFC
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Commit b6ffa2fe1250a8f506cc66044275b0bced56059e by james.henderson
[DebugInfo][Support] Replace DWARFDataExtractor size function
This patch adds a new size function to the base DataExtractor class,
which removes the need for the DWARFDataExtractor size function.
It is unclear why DWARFDataExtractor's size function returned zero in
some circumstances (i.e. when it is constructed without a section, and
with a different data source instead), so that behaviour has changed.
The old behaviour could cause an assertion in the debug line parser, as
the size did not reflect the actual data available, and could be lower
than the current offset being parsed.
Reviewed by: dblaikie
Differential Revision: https://reviews.llvm.org/D72337
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h
The file was modifiedllvm/unittests/Support/DataExtractorTest.cpp
The file was modifiedllvm/include/llvm/Support/DataExtractor.h
Commit af4adb07cd18b7081ec5818aee385654c8454356 by Raphael Isemann
[lldb][NFC] Use range-based for loops in IRInterpreter
The file was modifiedlldb/source/Expression/IRInterpreter.cpp
Commit bf7225888a99f49afac0b95a8996d0a942b6b0e3 by jan.kratochvil
[lldb] Fix lookup of symbols with the same address range but different
binding
This fixes a failing testcase on Fedora 30 x86_64 (regression Fedora
29->30):
PASS:
./bin/lldb
./lldb-test-build.noindex/functionalities/unwind/noreturn/TestNoreturnUnwind.test_dwarf/a.out
-o 'settings set symbols.enable-external-lookup false' -o r -o bt -o
quit
* frame #0: 0x00007ffff7aa6e75 libc.so.6`__GI_raise + 325
   frame #1: 0x00007ffff7a91895 libc.so.6`__GI_abort + 295
   frame #2: 0x0000000000401140 a.out`func_c at main.c:12:2
   frame #3: 0x000000000040113a a.out`func_b at main.c:18:2
   frame #4: 0x0000000000401134 a.out`func_a at main.c:26:2
   frame #5: 0x000000000040112e a.out`main(argc=<unavailable>,
argv=<unavailable>) at main.c:32:2
   frame #6: 0x00007ffff7a92f33 libc.so.6`__libc_start_main + 243
   frame #7: 0x000000000040106e a.out`_start + 46
vs.
FAIL - unrecognized abort() function:
./bin/lldb
./lldb-test-build.noindex/functionalities/unwind/noreturn/TestNoreturnUnwind.test_dwarf/a.out
-o 'settings set symbols.enable-external-lookup false' -o r -o bt -o
quit
* frame #0: 0x00007ffff7aa6e75 libc.so.6`.annobin_raise.c + 325
   frame #1: 0x00007ffff7a91895
libc.so.6`.annobin_loadmsgcat.c_end.unlikely + 295
   frame #2: 0x0000000000401140 a.out`func_c at main.c:12:2
   frame #3: 0x000000000040113a a.out`func_b at main.c:18:2
   frame #4: 0x0000000000401134 a.out`func_a at main.c:26:2
   frame #5: 0x000000000040112e a.out`main(argc=<unavailable>,
argv=<unavailable>) at main.c:32:2
   frame #6: 0x00007ffff7a92f33 libc.so.6`.annobin_libc_start.c + 243
   frame #7: 0x000000000040106e a.out`.annobin_init.c.hot + 46
The extra ELF symbols are there due to Annobin (I did not investigate
why this problem happened specifically since F-30 and not since F-28).
It is due to:
Symbol table '.dynsym' contains 2361 entries: Valu e          Size Type
Bind   Vis     Name 0000000000022769   5 FUNC   LOCAL  DEFAULT
_nl_load_domain.cold 000000000002276e   0 NOTYPE LOCAL  HIDDEN
.annobin_abort.c.unlikely
... 000000000002276e   0 NOTYPE LOCAL  HIDDEN
.annobin_loadmsgcat.c_end.unlikely
... 000000000002276e   0 NOTYPE LOCAL  HIDDEN
.annobin_textdomain.c_end.unlikely 000000000002276e 548 FUNC   GLOBAL
DEFAULT abort 000000000002276e 548 FUNC   GLOBAL DEFAULT
abort@@GLIBC_2.2.5 000000000002276e 548 FUNC   LOCAL  DEFAULT __GI_abort
0000000000022992   0 NOTYPE LOCAL  HIDDEN  .annobin_abort.c_end.unlikely
GDB has some more complicated preferences between overlapping and/or
sharing address symbols, I have made here so far the most simple fix for
this case.
Differential revision: https://reviews.llvm.org/D63540
The file was modifiedlldb/include/lldb/Symbol/Symtab.h
The file was modifiedlldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
The file was addedlldb/test/Shell/SymbolFile/Inputs/symbol-binding.s
The file was addedlldb/test/Shell/SymbolFile/symbol-binding.test
The file was modifiedlldb/source/Symbol/Symtab.cpp
Commit 7f1cf7d5f658b15abb8bd6840fc01e6d44487a23 by llvm-dev
[X86] Fix MSVC "truncation from 'int' to 'bool'" warning. NFCI.
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
Commit 8f49204f26ea8856b870d4c2344b98f4b706bea0 by llvm-dev
[SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in
LSHR/SHL (PR44526)
As detailed in https://blog.regehr.org/archives/1709 we don't make use
of the known leading/trailing zeros for shifted values in cases where we
don't know the shift amount value.
This patch adds support to SelectionDAG::ComputeKnownBits to use
KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the
minimum guaranteed leading/trailing known zero bits.
Differential Revision: https://reviews.llvm.org/D72573
The file was modifiedllvm/test/CodeGen/Mips/llvm-ir/lshr.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
The file was modifiedllvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-128.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/BPF/shifts.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-rotate-128.ll
The file was modifiedllvm/test/CodeGen/X86/avx2-vector-shifts.ll
The file was modifiedllvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/X86/avx2-shift.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.v2i16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
The file was modifiedllvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
Commit 804dd6722762040e7ce7e04bf97b19d9596fee20 by Milos.Stojanovic
[llvm-exegesis][mips] Expand loadImmediate()
Add support for loading 32-bit immediates and enable the use of GPR64
registers.
Differential Revision: https://reviews.llvm.org/D71873
The file was modifiedllvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/Mips/Target.cpp
The file was addedllvm/test/tools/llvm-exegesis/Mips/latency-GPR64.s
Commit b96ec492d34ecf31fd2c8d2f0033f00e36cc2b9c by oliver.stannard
[clangd] Remove raw string literals in macros
Older (but still supported) versions of GCC don't handle C++11 raw
string literals in macro parameters correctly.
The file was modifiedclang-tools-extra/clangd/unittests/FormattedStringTests.cpp
Commit 7efc7ca8edf6762dc64472417dabfbbdd838ceeb by llvm-dev
[X86][SSE] Add knownbits test showing missing
getValidMinimumShiftAmountConstant() ISD::SHL support
As mentioned on D72573
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
Commit ef5debac4302cd479ddd9e784a5b5acc8c2b9804 by llvm-dev
[SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant()
ISD::SHL support
As mentioned on D72573
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
Commit 6c203149b60e92e802df0c7a431744c337830a09 by oliver.stannard
[clang] Remove raw string literals in macros
Older (but still supported) versions of GCC don't handle C++11 raw
string literals in macro parameters correctly.
The file was modifiedclang/unittests/AST/ASTTraverserTest.cpp
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Commit c1fbede984ec1eb87b35218d3b8161d3a6e92318 by Raphael Isemann
[lldb][NFC] Remove debug print statement from TestExprDiagnostics.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/expression/diagnostics/TestExprDiagnostics.py
Commit a70b993239a829f30ff1e5991670a0b28bf51459 by Milos.Stojanovic
[llvm-exegesis] Remove unneeded std::move()
Caught by buildbot breakage:
/home/docker/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp:89:12:
error: moving a local object in a return statement prevents copy elision
[-Werror,-Wpessimizing-move]
   return std::move(Instructions);
          ^
/home/docker/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp:89:12:
note: remove std::move call here
   return std::move(Instructions);
          ^~~~~~~~~~            ~
The file was modifiedllvm/tools/llvm-exegesis/lib/Mips/Target.cpp
Commit d7d88b9d8b3efd8b4b07074aa64b5b4136a35b2c by arsenm2
GlobalISel: Fix assertion on wide G_ZEXT sources
It's possible to have a type that needs a mask greater than 64-bits.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
Commit 04a86966fbf46809d7a165b1f089e4d076f0f8a5 by ulrich.weigand
[FPEnv] Fix chain handling for fpexcept.strict nodes
We need to ensure that fpexcept.strict nodes are not optimized away even
if the result is unused. To do that, we need to chain them into the
block's terminator nodes, like already done for PendingExcepts.
This patch adds two new lists of pending chains, PendingConstrainedFP
and PendingConstrainedFPStrict to hold constrained FP intrinsic nodes
without and with fpexcept.strict markers. This allows not only to solve
the above problem, but also to relax chains a bit further by no longer
flushing all FP nodes before a store or other memory access. (They are
still flushed before nodes with other side effects.)
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D72341
The file was modifiedllvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
The file was modifiedllvm/test/CodeGen/X86/fp128-cast-strict.ll
The file was modifiedllvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll
The file was modifiedllvm/test/CodeGen/X86/fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/fp128-libcalls-strict.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/test/CodeGen/SystemZ/fp-strict-alias.ll
Commit 6a634a5dba847e1c1d81bf59f76dfa7d76ac3c4c by oliver.stannard
Revert "[libc++] Explicitly enumerate std::string external
instantiations."
This is causing failures for multiple buildbots and bootstrap builds,
details at https://reviews.llvm.org/rG61bd1920.
This reverts commit 61bd19206f61ace4b007838a2ff8884a13ec0374.
The file was modifiedlibcxx/src/string.cpp
The file was modifiedlibcxx/include/__config
The file was modifiedlibcxx/include/string
The file was modifiedlibcxx/include/__string
Commit 89ba150240a45cac88216b6127efb523fb9506b0 by llvm-dev
[X86] Add knownbits tests showing missing shift amount demanded elts
handling.
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
The file was modifiedllvm/test/CodeGen/X86/known-bits-vector.ll
Commit 6d1a8fd447934387605ea11d35e1b62866b7d093 by llvm-dev
[SelectionDAG] ComputeKnownBits - Add DemandedElts support to
getValidShiftAmountConstant/getValidMinimumShiftAmountConstant()
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
The file was modifiedllvm/test/CodeGen/X86/known-bits-vector.ll
Commit 376bc39c829fab7ad14424c5418c03ed6649d839 by llvm-dev
[SelectionDAG] ComputeNumSignBits - Use getValidShiftAmountConstant for
shift opcodes
getValidShiftAmountConstant handles out of bounds shift amounts for us,
allowing us to remove the local handling.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 26d2ace9e2305266be888e15392be29e3145163d by spatel
[InstSimplify] move tests for select from InstCombine; NFC
InstCombine has transforms that would enable these simplifications in an
indirect way, but those transforms are unsafe and likely to be removed.
The file was modifiedllvm/test/Transforms/InstCombine/select.ll
The file was modifiedllvm/test/Transforms/InstSimplify/select.ll
Commit 894f742acb977a09285dcab024e50c2cf6bce578 by Alexander.Richardson
[MIPS][ELF] Use PC-relative relocations in .eh_frame when possible
When compiling position-independent executables, we now use
DW_EH_PE_pcrel | DW_EH_PE_sdata4. However, the MIPS ABI does not define
a 64-bit PC-relative ELF relocation so we cannot use sdata8 for the
large code model case. When using the large code model, we fall back to
the previous behaviour of generating absolute relocations.
With this change clang-generated .o files can be linked by LLD without
having to pass -Wl,-z,notext (which creates text relocations). This is
simpler than the approach used by ld.bfd, which rewrites the
.eh_frame section to convert absolute relocations into relative
references.
I saw in D13104 that apparently ld.bfd did not accept pc-relative
relocations for MIPS ouput at some point. However, I also checked that
recent ld.bfd can process the clang-generated .o files so this no longer
seems true.
Reviewed By: atanasyan Differential Revision:
https://reviews.llvm.org/D72228
The file was addedlld/test/ELF/mips-eh_frame-pic.s
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp
The file was modifiedllvm/test/MC/Mips/eh-frame.s
The file was modifiedllvm/lib/Object/RelocationResolver.cpp
The file was modifiedllvm/test/DebugInfo/Mips/eh_frame.ll
Commit 8e8ccf4712cf58562a91c197da3efd4f9963ce0d by Alexander.Richardson
[MIPS] Don't emit R_(MICRO)MIPS_JALR relocations against data symbols
The R_(MICRO)MIPS_JALR optimization only works when used against
functions. Using the relocation against a data symbol (e.g. function
pointer) will cause some linkers that don't ignore the hint in this case
(e.g. LLD prior to commit 5bab291b7b) to generate a relative branch to
the data symbol which crashes at run time. Before this patch, LLVM was
erroneously emitting these relocations against local-dynamic TLS
function pointers and global function pointers with internal visibility.
Reviewers: atanasyan, jrtc27, vstefanovic Reviewed By: atanasyan
Differential Revision: https://reviews.llvm.org/D72571
The file was modifiedllvm/test/CodeGen/Mips/reloc-jalr.ll
The file was modifiedllvm/lib/Target/Mips/MipsISelLowering.cpp
Commit da33762de8531914d4d0dae16bfce2192f02bc79 by pablo.barrio
[AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below
Summary: The Pointer Authentication Extension (PAC) was added in
Armv8.3-A. Some instructions are implemented in the HINT space to allow
compiling code common to CPUs regardless of whether they feature PAC or
not, and still benefit from PAC protection in the PAC-enabled CPUs.
The 8.3-specific mnemonics were currently enabled in any architecture,
and LLVM was emitting them in assembly files when PAC code generation
was enabled. This was ok for compilations where both LLVM codegen and
the integrated assembler were used. However, the LLVM codegen was not
compatible with other assemblers (e.g. GAS). Given the fact that the
approach from these assemblers (i.e. to disallow Armv8.3-A mnemonics if
compiling for Armv8.2-A or lower) is entirely reasonable, this patch
makes LLVM to emit HINT when building for Armv8.2-A and below, instead
of PACIASP, AUTIASP and friends. Then, LLVM assembly should be
compatible with other assemblers.
Reviewers: samparker, chill, LukeCheeseman
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71658
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll
The file was modifiedllvm/test/CodeGen/AArch64/sign-return-address.ll
The file was modifiedllvm/test/MC/AArch64/armv8.3a-signed-pointer.s
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll
The file was modifiedllvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
The file was modifiedllvm/test/CodeGen/AArch64/speculation-hardening-loads.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
Commit 0b91e78a719065c67b33bf82b0cde3d4ecfe3b7d by sam.mccall
Add missing triples to tests in 0c29d3ff2233696f663ae34a8aeda23c750ac68f
so they target the right arch.
The file was modifiedllvm/test/CodeGen/X86/align-branch-boundary-default.s
The file was modifiedllvm/test/CodeGen/X86/align-branch-boundary-default.ll
Commit 7af67259cdd66811941514a263dd0f81c491d8f1 by llvm-dev
Sema::getOwningModule - take const Decl* type.
Fixes static analyzer warning that const_cast was being used despite
only const methods being called.
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
Commit 40311f9724953541ab7b755fb6a96b31c1e63f00 by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use castAs<> instead of getAs<> since the pointers are always
dereferenced and castAs will perform the null assertion for us.
The file was modifiedclang/lib/AST/ASTContext.cpp
Commit 025941785faf25a3d9ba2c1e7682ca6c2ad063af by llvm-dev
Fix some cppcheck shadow variable warnings. NFCI.
The file was modifiedclang/lib/AST/ASTContext.cpp
Commit 4647aae72f33b8742eb42c1fb869ebd4fdbb3038 by llvm-dev
Merge isVectorType() and getAs<VectorType> calls to silence clang static
analyzer warning. NFCI.
The file was modifiedclang/lib/AST/ASTDiagnostic.cpp
Commit b11027a08620dce2887377c830be239a4af478b6 by llvm-dev
Fix cppcheck uninitialized variable in DiffTree() constructor warning.
NFCI.
The file was modifiedclang/lib/AST/ASTDiagnostic.cpp
Commit 043c5eafa8789d76b06b93d157c928830c4d0814 by luismarques
[RISCV] Handle globals and block addresses in asm operands
Summary: These seem to be the machine operand types currently needed by
the RISC-V target.
Reviewers: asb, lenary Reviewed By: lenary Tags: #llvm Differential
Revision: https://reviews.llvm.org/D72275
The file was modifiedllvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm.ll
Commit b4a99a061f517e60985667e39519f60186cbb469 by alexandre.ganea
[Clang][Driver] Re-use the calling process instead of creating a new
process for the cc1 invocation
With this patch, the clang tool will now call the -cc1 invocation
directly inside the same process. Previously, the -cc1 invocation was
creating, and waiting for, a new process. This patch therefore reduces
the number of created processes during a build, thus it reduces build
times on platforms where process creation can be costly (Windows) and/or
impacted by a antivirus. It also makes debugging a bit easier, as
there's no need to attach to the secondary -cc1 process anymore,
breakpoints will be hit inside the same process.
Crashes or signaling inside the -cc1 invocation will have the same
side-effect as before, and will be reported through the same means.
This behavior can be controlled at compile-time through the
CLANG_SPAWN_CC1 cmake flag, which defaults to OFF. Setting it to ON will
revert to the previous behavior, where any -cc1 invocation will
create/fork a secondary process. At run-time, it is also possible to
tweak the CLANG_SPAWN_CC1 environment variable. Setting it and will
override the compile-time setting. A value of 0 calls -cc1 inside the
calling process; a value of 1 will create a secondary process, as
before.
Differential Revision: https://reviews.llvm.org/D69825
The file was modifiedclang/test/Driver/fsanitize-blacklist.c
The file was modifiedclang/test/Driver/unknown-arg.c
The file was modifiedclang/lib/Driver/Job.cpp
The file was modifiedclang/test/Driver/warning-options_pedantic.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/include/clang/Config/config.h.cmake
The file was modifiedclang/include/clang/Driver/Job.h
The file was modifiedclang/test/CMakeLists.txt
The file was addedclang/test/Driver/cc1-spawnprocess.c
The file was modifiedclang/CMakeLists.txt
The file was modifiedclang/include/clang/Driver/Driver.h
The file was modifiedclang/test/Driver/clang_f_opts.c
The file was modifiedclang/tools/driver/driver.cpp
Commit e653d306ce90e5612796d8adce9eb34b1c10e85a by ntv
[mlir][Linalg] Update ReshapeOp::build to be more idiomatic
Summary: This diff makes it easier to create a `linalg.reshape` op and
adds an EDSC builder api test to exercise the new builders.
Reviewers: ftynse, jpienaar
Subscribers: mehdi_amini, rriddle, burmako, shauheen, antiagainst,
arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72580
The file was modifiedmlir/include/mlir/Dialect/Linalg/EDSC/Intrinsics.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/test/EDSC/builder-api-test.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Commit 6b686703e63f0e992438ce445cbe4b3e78b94ea4 by kazu
[Inlining] Add PreInlineThreshold for the new pass manager
Summary: This patch makes it easy to try out different preinlining
thresholds with a command-line switch just like -preinline-threshold for
the legacy pass manager.
Reviewers: davidxl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72618
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit 202ab273e6eca134b69882f100c666fcd3affbcf by julian.gross
[mlir] Added missing GPU lowering ops.
Summary: This diff adds missing GPU lowering ops to MLIR.
Reviewers: herhut, pifon2a, ftynse
Tags: #pre-merge_beta_testing, #llvm
Differential Revision: https://reviews.llvm.org/D72439
The file was modifiedmlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
The file was modifiedmlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
The file was modifiedmlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
Commit 81e7922e83cf9782a39f4072e20eab8ab1e99828 by zinenko
[mlir] m_Constant()
Summary: Introduce m_Constant() which allows matching a constant
operation without forcing the user also to capture the attribute value.
Differential Revision: https://reviews.llvm.org/D72397
The file was modifiedmlir/test/IR/test-matchers.mlir
The file was modifiedmlir/test/lib/IR/TestMatchers.cpp
The file was modifiedmlir/include/mlir/IR/Matchers.h
The file was modifiedmlir/lib/IR/Builders.cpp
Commit 07804f75a6cc506fada40c474f1e60840ce737d8 by james.henderson
[DebugInfo] Make debug line address size mismatch non-fatal to parsing
Reasonable assumptions can be made when a parsed address length does not
match the expected length, so there's no need for this to be fatal.
Reviewed by: ikudrin
Differential Revision: https://reviews.llvm.org/D72154
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
Commit 2af97be8027a0823b88d4b6a07fc5eedb440bc1f by tejohnson
[ThinLTO] Add additional ThinLTO pipeline testing with new PM
Summary: I've added some more extensive ThinLTO pipeline testing with
the new PM, motivated by the bug fixed in D72386.
I beefed up llvm/test/Other/new-pm-pgo.ll a little so that it tests
ThinLTO pre and post link with PGO, similar to the testing for the
default pipelines with PGO.
Added new pre and post link PGO tests for both instrumentation and
sample PGO that exhaustively test the pipelines at different
optimization levels via opt.
Added a clang test to exhaustively test the post link pipeline invoked
for distributed builds. I am currently only testing O2 and O3 since
these are the most important for performance.
It would be nice to add similar exhaustive testing for full LTO, and for
the old PM, but I don't have the bandwidth now and this is a start to
cover some of the situations that are not currently default and were
under tested.
Reviewers: wmi
Subscribers: mehdi_amini, inglorion, hiraditya, steven_wu, dexonsmith,
jfb, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72538
The file was addedllvm/test/Other/Inputs/new-pm-thinlto-prelink-pgo-defaults.proftext
The file was addedclang/test/CodeGen/thinlto-distributed-newpm.ll
The file was addedllvm/test/Other/Inputs/new-pm-thinlto-samplepgo-defaults.prof
The file was modifiedllvm/test/Other/new-pm-pgo.ll
The file was addedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was addedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was addedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
The file was addedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
Commit 2d7e757a836abb54590daa25fce626283adafadf by danilo.carvalho.grael
[AArch64][SVE] Add patterns for some arith SVE instructions.
Summary: Add patterns for the following instructions:
- smax, smin, umax, umin
Reviewers: sdesmalen, huntergr, rengolin, efriedma, c-rhodes, mgudim,
kmclaughlin
Subscribers: amehsan
Differential Revision: https://reviews.llvm.org/D71779
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 90555d9253437d53fe03c26db73faf9c0ca14c82 by david.green
[Scheduler] Remove superfluous casts. NFC
The file was modifiedllvm/lib/CodeGen/TargetInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
Commit ee4aa1a228b31ec8b8bd3c4a793c7fa92fec88d6 by llvm-dev
[X86] Add AVX2 known signbits codegen tests
The file was modifiedllvm/test/CodeGen/X86/known-signbits-vector.ll
Commit 7afaa0099b907842b281c25c2a57937a2c307d3b by llvm-dev
[X86][SSE] Add sitofp(ashr(x,y)) test case with non-uniform shift value
The file was modifiedllvm/test/CodeGen/X86/known-signbits-vector.ll
Commit 38e2c01221a9751c0b797417747200d2e9513b9f by llvm-dev
[SelectionDAG] ComputeNumSignBits add
getValidMinimumShiftAmountConstant() ISD::SRA support
Allows us to handle more non-uniform SRA sign bits cases
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/known-signbits-vector.ll
Commit 05366870eed154c7eb48c7cc3873ea5188f54cc9 by weiwei64
[LegalizeTypes] Add SoftenFloatResult support for
STRICT_SINT_TO_FP/STRICT_UINT_TO_FP
Some target like arm/riscv with soft-float will have compiling crash
when using -fno-unsafe-math-optimization option. This patch will add the
missing strict FP support to SoftenFloatRes_XINT_TO_FP.
Differential Revision: https://reviews.llvm.org/D72277
The file was modifiedllvm/test/CodeGen/ARM/fp-intrinsics.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
Commit f2bbe8ede057af13b56949f24bbfb436f8a55f97 by Jonas Devlieghere
[lldb/Scripts] Remove SWIG bot
This is no longer used or maintained.
Differential revision: https://reviews.llvm.org/D72539
The file was removedlldb/scripts/swig_bot_lib/client.py
The file was removedlldb/scripts/swig_bot.py
The file was removedlldb/scripts/swig_bot_lib/local.py
The file was removedlldb/scripts/swig_bot_lib/remote.py
The file was removedlldb/scripts/swig_bot_lib/server.py
Commit bb2e5f5e454245c8e7e9e4c9bf7a463c64604292 by tejohnson
Fix tests for builtbot failures
Should fix most of the buildbot failures from
2af97be8027a0823b88d4b6a07fc5eedb440bc1f, by loosening up the matching
on the AnalysisProxy output.
Added in --dump-input=fail on the one test that appears to be something
different, so I can hopefully debug it better.
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedclang/test/CodeGen/thinlto-distributed-newpm.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
Commit 9d30d769041b14c0ff29770d59027e679e6b7edc by Jonas Devlieghere
[lldb/Docs] Extend description section of the main page
The current description is a bit terse. I've copy/pasted the
introduction form the website.
The file was modifiedlldb/docs/man/lldb.rst
Commit ffc05d0dbc88b89756d553ff32abefe720d27742 by llvm-dev
[X86][SSE] Add sitofp(shl(sext(x),y)) test case with non-uniform shift
value
Shows that for non-uniform SHL shifts we fail to determine the minimum
number of sign bits remaining (based off the maximum shift amount value)
The file was modifiedllvm/test/CodeGen/X86/known-signbits-vector.ll
Commit 7d9b0a61c32b95fdc73228266d3f14687a8ada95 by arsenm2
AMDGPU/GlobalISel: Simplify assert
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit ca19d7a3993c69633826ae388155c9ad176b11df by arsenm2
AMDGPU/GlobalISel: Fix branch targets when emitting SI_IF
The branch target needs to be changed depending on whether there is an
unconditional branch or not.
Loops also need to be similarly fixed, but compiling a simple testcase
end to end requires another set of patches that aren't upstream yet.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
Commit 2f090cc8f1a3144c81b024bdc52ec1ae49dc0def by arsenm2
AMDGPU/GlobalISel: Add some baseline tests for vector extract
A future change will try to fold constant offsets into the loop which
these will stress.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
Commit 3d8f1b2d22be79aab3d246fa5bc9c24b911b0bd2 by arsenm2
AMDGPU/GlobalISel: Set insert point after waterfall loop
The current users of the waterfall loop utility functions do not make
use of the restored original insert point. The insertion is either done,
or they set the insert point somewhere else. A future change will want
to insert instructions after the waterfall loop, but figuring out the
point after the loop is more difficult than ensuring the insert point is
there after the loop.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit c6fcd5d115b62280669719c5ead436904c93d6cb by llvm-dev
[SelectionDAG] ComputeNumSignBits add
getValidMaximumShiftAmountConstant() for ISD::SHL support
Allows us to handle non-uniform SHL shifts to determine the minimum
number of sign bits remaining (based off the maximum shift amount value)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/known-signbits-vector.ll
Commit 203801425d222555fa2617fff19ecd861525429f by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap}
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.ordered.add.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.ordered.add.gfx10.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.ordered.swap.ll
Commit 292562c0046c72ea1ed229dbe13a89dca73e5b89 by tejohnson
Try number 2 for fixing bot failures
Additional fixes for bot failures from
2af97be8027a0823b88d4b6a07fc5eedb440bc1f. Remove more exact matching on
AnalyisManagers, as they can vary. Also allow different orders between
LoopAnalysis and BranchProbabilityAnalysis as that can vary due to both
being accessed in the parameter list of a call.
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedclang/test/CodeGen/thinlto-distributed-newpm.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
Commit a2cd4fe6bf2a4e37d5f69b0b19cb1134a14e2970 by benny.kra
Unbreak the mlir build after 202ab273e6eca134b69882f100c666fcd3affbcf
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
Commit fb79ef524171c96a9f3df025ac7a8a3e00fdc0b4 by aaron
Fix readability-identifier-naming missing member variables
Fixes PR41122 (missing fixes for member variables in a destructor) and
PR29005 (does not rename class members in all locations).
The file was addedclang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-member-decl-usage.cpp
The file was modifiedclang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
Commit 7aed43b60739653b13b8503f9df4c958c44feed8 by tejohnson
Hopefully last fix for bot failures
Hopefully final bot fix for last few failures from
2af97be8027a0823b88d4b6a07fc5eedb440bc1f.
Looks like sometimes the "llvm::" preceeding objects get printed in the
debug pass manager output and sometimes they don't. Replace with
wildcard matching.
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedclang/test/CodeGen/thinlto-distributed-newpm.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
Commit 484a7472f1aa6906f2b66dc33bcf69cc8d5b9f29 by puyan
[llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands.
This patch makes it so that cases where multiple instructions that
differ only in their FrameIndex MachineOperand values no longer collide.
For instance:
%1:_(p0) = G_FRAME_INDEX %stack.0
%2:_(p0) = G_FRAME_INDEX %stack.1
Prior to this patch these instructions would collide together.
Differential Revision: https://reviews.llvm.org/D71583
The file was addedllvm/test/CodeGen/MIR/X86/mir-namer-hash-frameindex.mir
The file was modifiedllvm/lib/CodeGen/MIRVRegNamerUtils.cpp
Commit 64a93afc3c630c39e5c583e4f67aef5821d635b6 by maskray
[X86][Disassembler] Fix a bug when disassembling an empty string
readPrefixes() assumes insn->bytes is non-empty. The code path is not
exercised in llvm-mc because llvm-mc does not feed empty input to
MCDisassembler::getInstruction().
This bug is uncovered by a5994c789a2982a770254ae1607b5b4cb641f73c. An
empty string did not crash before because the deleted regionReader()
allowed UINT64_C(-1) as insn->readerCursor.
  Bytes.size() <= Address -> R->Base
0 <= UINT64_C(-1) - UINT32_C(-1)
The file was modifiedllvm/unittests/MC/Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
Commit cb988a858abbaf1a1ae0fe03f2a1dae692131ea9 by tejohnson
Add a couple of missed wildcards in debug-pass-manager output checking
Along with the previous fix for bot failures from
2af97be8027a0823b88d4b6a07fc5eedb440bc1f, need to add a wildcard in a
couple of places where my local output did not print "llvm::" but the
bot is.
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedclang/test/CodeGen/thinlto-distributed-newpm.ll