SuccessChanges

Summary

  1. [ARM] Remove some spurious MVE reduction instructions. (details)
  2. AMDGPU/GlobalISel: Try generated matcher before add/sub code (details)
  3. AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic (details)
  4. [clangd] Use pre-populated mappings for standard symbols (details)
  5. AMDGPU/GlobalISel: Use known bits for selection (details)
  6. [NFC] Add aacps bitfields access test (details)
Commit 0e48bd24e2120e0a9fbf2bc4896266b43496df3d by simon.tatham
[ARM] Remove some spurious MVE reduction instructions.
The family of 'dual-accumulating' vector multiply-add instructions
(VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
unsigned integer types, and they all have an 'exchange' variant (with an
X in the name) that modifies which pairs of vector lanes in the two
inputs are multiplied together. But there's a clause in the spec that
says that the X variants //don't// operate on unsigned integer types,
only signed. You can have X, or unsigned, or neither, but not both.
We didn't notice that clause when we implemented the MC support for
these instructions, so LLVM believes that things like VMLADAVX.U8 do
exist, contradicting the spec. Here I fix that by conditioning them out
in Tablegen.
In order to do that, I've reversed the nesting order of the Tablegen
multiclasses for those instructions. Previously, the innermost
multiclass generated the X and not-X variants, and the one outside that
generated the A and not-A variants. Now X is done by the outer
multiclass, which allows me to bypass that one when I only want the two
not-X variants.
Changing the multiclass nesting order also changes the names of the
instruction ids unless I make a special effort not to. I decided that
while I was changing them anyway I'd make them look nicer; so now the
instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32, instead
of cumbersome _noacc_noexch suffixes.
The corresponding multiply-subtract instructions are unaffected. Those
don't accept unsigned types at all, either in the spec or in LLVM.
Reviewers: ostannard, dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67214
llvm-svn: 371405
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/test/MC/ARM/mve-reductions.s
The file was modifiedllvm/test/MC/Disassembler/ARM/mve-reductions.txt
Commit d50f937378c3cd0d763198c404687dea97e2734d by Matthew.Arsenault
AMDGPU/GlobalISel: Try generated matcher before add/sub code
This will allow optimization patterns which fold adds away to work.
llvm-svn: 371406
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 8e3bc9b572224023eb8536fe934167524ef68ecd by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic
llvm-svn: 371407
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 8b76709bac33f7edf0764416b4e5874c29f23e70 by ibiryukov
[clangd] Use pre-populated mappings for standard symbols
Summary: This takes ~5% of time when running clangd unit tests.
To achieve this, move mapping of system includes out of
CanonicalIncludes and into a separate class
Reviewers: sammccall, hokein
Reviewed By: sammccall
Subscribers: MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67172
llvm-svn: 371408
The file was modifiedclang-tools-extra/clangd/index/CanonicalIncludes.cpp
The file was modifiedclang-tools-extra/clangd/Preamble.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CanonicalIncludesTests.cpp
The file was modifiedclang-tools-extra/clangd/index/CanonicalIncludes.h
The file was modifiedclang-tools-extra/clangd/ParsedAST.cpp
The file was modifiedclang-tools-extra/clangd/index/IndexAction.cpp
Commit 2dd088ec7d8bf0804fc00e3583cb0bf10ae5c670 by Matthew.Arsenault
AMDGPU/GlobalISel: Use known bits for selection
llvm-svn: 371409
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 3c8644666c496e983d725859af61624299da67f1 by diogo.sampaio
[NFC] Add aacps bitfields access test
llvm-svn: 371410
The file was addedclang/test/CodeGen/aapcs-bitfield.c