Started 1 mo 6 days ago
Took 44 min

Success Build #22145 (Jul 2, 2020 9:46:52 AM)

Changes
  1. [ELF][test] Add some additional .eh_frame/.eh_frame_hdr testing (details)
  2. [InstCombine] Add some (vXi1 trunc(lshr(x,c))) -> icmp_eq(and(x,c')) tests for vectors with undef elements (details)
  3. [InstCombine] Add (vXi1 trunc(lshr(x,c))) -> icmp_eq(and(x,c')) support for non-uniform vectors (details)
  4. [AArch64][SVE] NFC: Rename isOrig -> isReverseInstr (details)
  5. [lldb] Fix type conversion in the Scalar getters (details)
  6. [InstCombine] Add some sext/trunc tests to show missing support for non-uniform vectors (details)
  7. [MLIR][SPIRVToLLVM] Implementation of spv.BitFieldInsert pattern (details)
  8. [MLIR][SPIRVToLLVM] SPIR-V function call conversion pattern (details)

Started by timer (12 times)

This run spent:

  • 1 hr 52 min waiting;
  • 44 min build duration;
  • 2 hr 37 min total from scheduled to completion.
Revision: ac4c27ddd9bf6b75f4430476a1f63a3377b38f2c
  • refs/remotes/origin/master
Revision: 8119a374bc3aa7ee7f135038a7c772762711d135
  • refs/remotes/origin/master
Revision: ac4c27ddd9bf6b75f4430476a1f63a3377b38f2c
  • refs/remotes/origin/master
Test Result (no failures)