Started 1 mo 25 days ago
Took 2 hr 0 min

Success Build #23156 (Jul 30, 2020 5:38:35 PM)

  1. [clang codegen][AArch64] Use llvm.aarch64.neon.fcvtzs/u where it's necessary (details)
  2. [libc] Add a tool called WrapperGen. (details)
  3. [doc] Describe the header guard style (details)
  4. [AArch64][GlobalISel] Add legalization & selection support for G_INTRINSIC_LRINT. (details)
  5. [LegalizeTypes][SVE] Support widen/split legalization for SPLAT_VECTOR (details)
  6. [debugserver/Apple Silicon] Handoff connections when attaching to translated processes (details)
  7. [profile] Remove dependence on getpagesize from InstrProfilingBuffer.c.o (details)
  8. [ValueTracking] Add basic computeKnownBits support for llvm.abs intrinsic (details)
  9. [Attributor] Add time trace support. (details)
  10. [X86] Separate CPU Feature lists in between architecture features and tuning features (details)

Started by timer (15 times)

This run spent:

  • 2 hr 26 min waiting;
  • 2 hr 0 min build duration;
  • 4 hr 24 min total from scheduled to completion.
Revision: 48a02487ae940446bb7c2ee3d4c93ba7cdc6b9cf
  • refs/remotes/origin/master
Revision: 3ad09fd03c51823aeb0bcbd7898aada33e9228d6
  • refs/remotes/origin/master
Revision: 48a02487ae940446bb7c2ee3d4c93ba7cdc6b9cf
  • refs/remotes/origin/master
Test Result (no failures)