1. [mips] Remove duplicated case from the `StringSwitch`. NFC (details)
  2. [mips] Replace call `expandLoadAddress` by `loadAndAddSymbolAddress`. (details)
  3. [TableGen] Include directly into the (details)
  4. [MVT] Add v16f16 and v32f16 vectors. (details)
Commit bb2f85724722f6c2f256c9475220b16a56c3c5b8 by simon
[mips] Remove duplicated case from the `StringSwitch`. NFC
llvm-svn: 369562
The file was modifiedllvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
Commit 159f621c5c84c0a834394893f7abff222cbc19ad by simon
[mips] Replace call `expandLoadAddress` by `loadAndAddSymbolAddress`.
In case of expanding `lw/sw $reg, symbol($reg)` instruction for PIC it's
enough to call the `loadAndAddSymbolAddress` method. Additional work
performed by the `expandLoadAddress` is not required here.
llvm-svn: 369563
The file was modifiedllvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
Commit 8d5fbecf8ba7a2ef98d003e5d1f85c023b761ad2 by craig.topper
[TableGen] Include directly into the
This prevents needing to keep the test in sync with
This is not the only test that includes
llvm-svn: 369564
The file was modifiedllvm/test/TableGen/
Commit 3f59bfd5be39687cd3a853aaffe8ef2d84ab2ff8 by craig.topper
[MVT] Add v16f16 and v32f16 vectors.
I might look at improving PR43065 which will require being able to mark
a 256 and 512 bit vector of f16 as Legal.
Differential Revision:
llvm-svn: 369565
The file was modifiedllvm/include/llvm/CodeGen/
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/ValueTypes.cpp