Started 16 days ago
Took 9 min 53 sec

Success Build #8707 (Feb 11, 2020 11:40:31 AM)

Changes
  1. [AMDGPU] Remove AMDGPURegisterInfo (details)
  2. [gn build] Port 453a8f3af78 (details)
  3. [X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models (details)
  4. [BasicAA] Make BasicAA a cfg pass. (details)
  5. [mlir] [VectorOps] Implement vector.reduce operation (details)
  6. [clang-tidy] Added check to disable bugprone-infinite-loop on known false condition (details)
  7. [lldb][NFC] Test ModuleCompletion mode by completing the target modules load argument (details)
  8. [gn] Paper over Py3 urllib2 incompatibility in gn/get.py (details)

Started by timer (3 times)

This run spent:

  • 25 min waiting;
  • 9 min 53 sec build duration;
  • 35 min total from scheduled to completion.
Revision: cbccdbde6fbbfd4ab945a3bff18d6bc43a4b66bc
  • refs/remotes/origin/master
Revision: 2040831d0566221aa01640123451b7839fc45920
  • refs/remotes/origin/master
Revision: cbccdbde6fbbfd4ab945a3bff18d6bc43a4b66bc
  • refs/remotes/origin/master
Test Result (no failures)