SuccessChanges

Summary

  1. [NFC][ARM] Add more LowOverheadLoop tests. (details)
  2. [mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments (details)
  3. [SCEV] Verify that all mapped SCEV AddRecs refer to valid loops. (details)
  4. InstCombine] collectBitParts - cleanup variable names. NFCI. (details)
  5. [InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI. (details)
Commit 3cbd01ddb9372b725dcea3dd5fed21ef5b3d9578 by sam.parker
[NFC][ARM] Add more LowOverheadLoop tests.
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
Commit 0b17d4754a94b7129c2483762acd586783802b12 by limo
[mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments

Current setup for conv op vectorization does not enable user to specify tile
sizes as well as dimensions for vectorization. In this commit we change that by
adding tile sizes as pass arguments. Every dimension with corresponding tile
size > 1 is automatically vectorized.

Differential Revision: https://reviews.llvm.org/D88533
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nchw-call.mlir
The file was modifiedmlir/test/Conversion/LinalgToVector/linalg-to-vector.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ndhwc-call.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-ncw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ncdhw-call.mlir
The file was modifiedmlir/test/lib/Transforms/TestConvVectorization.cpp
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nhwc-call.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-nwc-call.mlir
Commit 0eab9d5823815c6520697f8d725c402c88e5d050 by flo
[SCEV] Verify that all mapped SCEV AddRecs refer to valid loops.

This check helps to guard against cases where expressions referring to
invalidated/deleted loops are not properly invalidated.

The additional check is motivated by the reproducer shared for 8fdac7cb7abb
and I think in general make sense as a sanity check.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D88166
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 05290eead3f95e02700890321ccf6719770f91fe by llvm-dev
InstCombine] collectBitParts - cleanup variable names. NFCI.

Fix a number of WShadow warnings (I was used as the instruction and index......) and fix cases to match style.

Also, replaced the Bit APInt mask check in AND instructions with a direct APInt[] bit check.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 413b4998bd722ab671e29e6dff5d458d1869f39b by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI.

Post-commit feedback on D88316
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp