Commit
3f88c10a6b25668bb99f5eee7867dcbf37df973c
by sam.parker[RDA] isSafeToDefRegAt: Look at global uses
We weren't looking at global uses of a value, so we could happily overwrite the register incorrectly.
Differential Revision: https://reviews.llvm.org/D88554
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 | llvm/lib/CodeGen/ReachingDefAnalysis.cpp |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir |
Commit
621c6c89627972d52796e64a9476a7d05f22f2cd
by llvm-dev[InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI.
Early out if both pattern matches have failed (or we don't want them). Fix case of bit index iterator (and avoid Wshadow issue).
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 | llvm/lib/Transforms/Utils/Local.cpp |
Commit
08c5720405d5204ec2329b7f6c561062c7dddee2
by llvm-dev[InstCombine] Add PR47191 bswap tests
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 | llvm/test/Transforms/InstCombine/bswap.ll |
Commit
f794160c6cb7da4b5ef354a91fe498341f651d36
by emaste[lldb] Fix FreeBSD Arm Process Plugin build
Add a missing include and some definitions in 769533216666.
Patch by: Brooks Davis
Reviewed by: labath
Differential Revision: https://reviews.llvm.org/D88453
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 | lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.cpp |
 | lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.h |
Commit
d8563654701c79fb9ab28ecf94567d9934baed05
by flo[VPlan] Change recipes to inherit from VPUser instead of a member var.
Now that VPUser is not inheriting from VPValue, we can take the next step and turn the recipes that already manage their operands via VPUser into VPUsers directly. This is another small step towards traversing def-use chains in VPlan.
This is NFC with respect to the generated code, but makes the interface more powerful.
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 | llvm/unittests/Transforms/Vectorize/VPlanTest.cpp |
 | llvm/lib/Transforms/Vectorize/VPlanValue.h |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
 | llvm/lib/Transforms/Vectorize/VPlan.h |
Commit
762e8f9bbdaf43300dbc75637a8bce1ce643cc06
by mgorny[lldb] [Process/NetBSD] Fix operating on ftag register
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 | lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp |
Commit
d5545a8993489ee426b757482a64c9373cf7cf38
by llvm-dev[InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI.
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 | llvm/lib/Transforms/Utils/Local.cpp |
Commit
7fcad5583a12026ce19afe487681753ac633064a
by llvm-dev[InstCombine] Remove %tmp variable names from bswap tests
Appease update_test_checks script that was complaining about potential %TMP clashes
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 | llvm/test/Transforms/InstCombine/bswap.ll |
Commit
c722b3259690d3aad20f31d0ffe6c12b1416bccc
by llvm-dev[InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI.
There doesn't seem to be any good reason for having a separate path for when we bswap/bitreverse at a smaller size than the destination size - so merge these to make the instruction generation a lot clearer.
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 | llvm/lib/Transforms/Utils/Local.cpp |
Commit
216af81c39d1cc4e90af7b991d517c4c7acc912e
by sam.mccall[clangd] Fix invalid UTF8 when extracting doc comments.
Differential Revision: https://reviews.llvm.org/D88567
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 | clang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp |
 | clang-tools-extra/clangd/unittests/CodeCompletionStringsTests.cpp |
 | clang-tools-extra/clangd/CodeCompletionStrings.cpp |
Commit
dfb717da1f794c235b81a985a57dc238c82318e6
by sd.fertile[PowerPC] Remove support for VRSAVE save/restore/update.
After removal of Darwin as a PowerPC subtarget, the VRSAVE save/restore/spill/update code is no longer needed by any supported subtarget, so remove it while keeping support for vrsave and related instruction aliases for inline asm. I've pre-commited tests to document the existing vrsave handling in relation to @llvm.eh.unwind.init and inline asm usage, as well as a test which shows a beahviour change on AIX related to returning vector type as we were wrongly emiting VRSAVE_UPDATE on AIX.
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 | llvm/lib/Target/PowerPC/PPCISelLowering.cpp |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.td |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp |
 | llvm/lib/Target/PowerPC/PPCRegisterInfo.h |
 | llvm/lib/Target/PowerPC/README_ALTIVEC.txt |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.h |
 | llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h |
 | llvm/test/CodeGen/PowerPC/aix-vector-return.ll |
 | llvm/lib/Target/PowerPC/PPCFrameLowering.cpp |
 | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp |
 | llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp |
Commit
43d239d0fadb1f8ea297580ca39dfbee96c913c1
by mikael.holmen[GlobalISel] Fix incorrect setting of ValNo when splitting
Before, for each original argument i, ValNo was set to i + PartIdx, but ValNo is intended to reflect the index of the value before splitting. Hence, ValNo should always be set to i and not consider the PartIdx.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D86511
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 | llvm/lib/CodeGen/GlobalISel/CallLowering.cpp |
Commit
f33f8a2b30325d89c4b7daef1b7d11d6da38fd56
by benny.kraMove AffineMapAttr into BaseOps.td
AffineMapAttr is already part of base, it's just impossible to refer to it from ODS without pulling in the definition from Affine dialect.
Differential Revision: https://reviews.llvm.org/D88555
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 | mlir/include/mlir/IR/OpBase.td |
 | mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td |
 | mlir/include/mlir/Dialect/GPU/ParallelLoopMapperAttr.td |
 | mlir/include/mlir/Dialect/Vector/VectorOps.td |
 | mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td |
 | mlir/test/lib/Dialect/Test/TestOps.td |
 | mlir/include/mlir/Dialect/Affine/IR/AffineOps.td |
 | mlir/include/mlir/Dialect/Affine/IR/AffineOpsBase.td |
Commit
dc261d23d07cccfa7b10a3d1a43903138aee94dc
by ro[sanitizers] Fix internal__exit on Solaris `TestCases/log-path_test.cpp` currently `FAIL`s on Solaris:
$ env ASAN_OPTIONS=log_path=`for((i=0;i<10000;i++)); do echo -n $i; done` ./log-path_test.cpp.tmp ==5031==ERROR: Path is too long: 01234567... Segmentation Fault (core dumped)
The `SEGV` happens here:
Thread 2 received signal SIGSEGV, Segmentation fault. [Switching to Thread 1 (LWP 1)] 0x00000000 in ?? () (gdb) where #0 0x00000000 in ?? () #1 0x080a1e63 in __interceptor__exit (status=1) at /vol/gcc/src/llvm/llvm/local/projects/compiler-rt/lib/asan/../sanitizer_common/sanitizer_common_interceptors.inc:3808 #2 0x08135ea8 in __sanitizer::internal__exit (exitcode=1) at /vol/gcc/src/llvm/llvm/local/projects/compiler-rt/lib/sanitizer_common/sanitizer_solaris.cc:139
when `__interceptor__exit` tries to call `__interception::real__exit` which is `NULL` at this point because the interceptors haven't been initialized yet.
Ultimately, the problem lies elsewhere, however: `internal__exit` in `sanitizer_solaris.cpp` calls `_exit` itself since there doesn't exit a non-intercepted version in `libc`. Using the `syscall` interface instead isn't usually an option on Solaris because that interface isn't stable. However, in the case of `SYS_exit` it can be used nonetheless: `SYS_exit` has remained unchanged since at least Solaris 2.5.1 in 1996, and this is what this patch does.
Tested on `amd64-pc-solaris2.11`.
Differential Revision: https://reviews.llvm.org/D88404
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 | compiler-rt/lib/sanitizer_common/sanitizer_solaris.cpp |
 | compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp |
Commit
944691f0b7fa8d99790a4544545e55f014c37295
by Xiangling.Liao[NFC][FE] Replace TypeSize with StorageUnitSize
On some targets like AIX, last bitfield size is not always equal to last bitfield type size. Some bitfield like bool will have the same alignment as [unsigned]. So we'd like to use a more general term `StorageUnit` to replace type in this field.
Differential Revision: https://reviews.llvm.org/D88260
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 | clang/lib/AST/RecordLayoutBuilder.cpp |
Commit
89baeaef2fa9a2441d087a218ac82e11a5d4e548
by Matthew.ArsenaultReapply "RegAllocFast: Rewrite and improve"
This reverts commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4.
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 | llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll |
 | llvm/test/CodeGen/PowerPC/spill-nor0.mir |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll |
 | llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll |
 | llvm/test/CodeGen/Thumb2/high-reg-spill.mir |
 | llvm/test/CodeGen/X86/pr32451.ll |
 | llvm/test/CodeGen/AMDGPU/spill-m0.ll |
 | llvm/test/CodeGen/X86/avx-load-store.ll |
 | llvm/test/CodeGen/PowerPC/vsx.ll |
 | llvm/test/CodeGen/ARM/fast-isel-select.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll |
 | llvm/test/CodeGen/AMDGPU/wwm-reserved.ll |
 | llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll |
 | llvm/test/CodeGen/X86/pr32241.ll |
 | llvm/test/DebugInfo/X86/dbg-declare-arg.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll |
 | llvm/test/CodeGen/X86/pr30430.ll |
 | llvm/test/CodeGen/AArch64/popcount.ll |
 | llvm/test/CodeGen/ARM/Windows/alloca.ll |
 | llvm/test/CodeGen/X86/pr44749.ll |
 | llvm/test/CodeGen/PowerPC/spill-nor0.ll |
 | llvm/lib/CodeGen/RegAllocFast.cpp |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll |
 | llvm/test/CodeGen/AMDGPU/spill-agpr.mir |
 | llvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll |
 | llvm/test/CodeGen/X86/x86-64-intrcc.ll |
 | llvm/test/DebugInfo/X86/pieces-1.ll |
 | llvm/test/DebugInfo/X86/prologue-stack.ll |
 | llvm/test/CodeGen/Mips/implicit-sret.ll |
 | llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll |
 | llvm/test/CodeGen/X86/pr32284.ll |
 | llvm/test/CodeGen/X86/pr30813.ll |
 | llvm/test/CodeGen/X86/pr34592.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll |
 | llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll |
 | llvm/test/CodeGen/PowerPC/aix-overflow-toc.py |
 | llvm/test/CodeGen/AArch64/GlobalISel/builtin-return-address-pacret.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll |
 | llvm/test/CodeGen/Mips/micromips-eva.mir |
 | llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir |
 | llvm/test/CodeGen/Mips/msa/ldr_str.ll |
 | llvm/test/CodeGen/X86/x86-32-intrcc.ll |
 | llvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll |
 | llvm/test/DebugInfo/AArch64/prologue_end.ll |
 | llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll |
 | llvm/test/CodeGen/X86/swift-return.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll |
 | llvm/test/CodeGen/PowerPC/fp64-to-int16.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctpop.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll |
 | llvm/test/CodeGen/X86/fast-isel-x86-64.ll |
 | llvm/test/CodeGen/X86/stack-protector-msvc.ll |
 | llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_split_because_of_memsize_or_align.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll |
 | llvm/test/CodeGen/X86/fast-isel-select.ll |
 | llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll |
 | llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll |
 | llvm/test/CodeGen/X86/win64_eh.ll |
 | llvm/test/CodeGen/X86/pr42452.ll |
 | llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll |
 | llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll |
 | llvm/test/DebugInfo/X86/parameters.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll |
 | llvm/test/CodeGen/Mips/copy-fp64.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll |
 | llvm/test/CodeGen/PowerPC/popcount.ll |
 | llvm/test/CodeGen/AArch64/cmpxchg-O0.ll |
 | llvm/test/CodeGen/X86/pr32484.ll |
 | llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll |
 | llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll |
 | llvm/test/CodeGen/AArch64/swifterror.ll |
 | llvm/test/CodeGen/AArch64/unwind-preserved.ll |
 | llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll |
 | llvm/test/CodeGen/AMDGPU/spill192.mir |
 | llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll |
 | llvm/test/CodeGen/X86/volatile.ll |
 | llvm/test/CodeGen/SPARC/fp16-promote.ll |
 | llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll |
 | llvm/test/CodeGen/ARM/fast-isel-vararg.ll |
 | llvm/test/CodeGen/PowerPC/addegluecrash.ll |
 | llvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_constants.ll |
 | llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll |
 | llvm/test/CodeGen/PowerPC/elf-common.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll |
 | llvm/test/CodeGen/X86/bug47278.mir |
 | llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll |
 | llvm/test/CodeGen/AArch64/arm64_32-null.ll |
 | llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll |
 | llvm/test/CodeGen/ARM/debug-info-blocks.ll |
 | llvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll |
 | llvm/test/DebugInfo/Mips/prologue_end.ll |
 | llvm/test/CodeGen/ARM/swifterror.ll |
 | llvm/test/CodeGen/X86/atomic-monotonic.ll |
 | llvm/test/CodeGen/AArch64/br-cond-not-merge.ll |
 | llvm/test/CodeGen/AArch64/swift-return.ll |
 | llvm/test/CodeGen/X86/bug47278-eflags-error.mir |
 | llvm/test/CodeGen/X86/pr34653.ll |
 | llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll |
 | lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll |
 | llvm/test/CodeGen/X86/pr27591.ll |
 | llvm/test/CodeGen/X86/phys-reg-local-regalloc.ll |
 | llvm/test/CodeGen/ARM/thumb-big-stack.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll |
 | llvm/test/CodeGen/Mips/atomic64.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll |
 | llvm/test/CodeGen/X86/pr32340.ll |
 | llvm/test/CodeGen/ARM/ldrd.ll |
 | llvm/test/CodeGen/X86/atomic64.ll |
 | llvm/test/DebugInfo/X86/reference-argument.ll |
 | llvm/test/CodeGen/ARM/stack-guard-reassign.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll |
 | llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll |
 | llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll |
 | llvm/test/CodeGen/X86/pr47000.ll |
 | llvm/test/CodeGen/X86/fast-isel-select-sse.ll |
 | llvm/test/CodeGen/ARM/fast-isel-call.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll |
 | llvm/test/CodeGen/SystemZ/swift-return.ll |
 | llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll |
 | llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll |
 | llvm/test/CodeGen/X86/fast-isel-nontemporal.ll |
 | llvm/test/CodeGen/X86/pr32345.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll |
 | llvm/test/CodeGen/X86/mixed-ptr-sizes.ll |
 | llvm/test/CodeGen/ARM/pr47454.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll |
 | llvm/test/CodeGen/Thumb2/mve-vector-spill.ll |
 | llvm/test/CodeGen/X86/pr11415.ll |
 | llvm/test/CodeGen/ARM/cmpxchg-O0.ll |
 | llvm/test/CodeGen/PowerPC/vsx-args.ll |
 | llvm/test/DebugInfo/ARM/prologue_end.ll |
 | llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll |
 | llvm/test/DebugInfo/X86/subreg.ll |
 | llvm/test/CodeGen/X86/atomic6432.ll |
 | llvm/test/CodeGen/X86/crash-O0.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll |
 | llvm/test/CodeGen/AArch64/arm64_32-fastisel.ll |
 | llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address_pic.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll |
 | llvm/test/CodeGen/ARM/legalize-bitcast.ll |
 | llvm/test/CodeGen/Mips/atomic-min-max.ll |
 | llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir |
 | llvm/test/CodeGen/Mips/atomic.ll |
 | llvm/test/CodeGen/SystemZ/swifterror.ll |
 | llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll |
 | llvm/test/CodeGen/X86/atomic-unordered.ll |
 | llvm/test/DebugInfo/AArch64/frameindices.ll |
 | llvm/test/CodeGen/X86/atomic32.ll |
 | llvm/test/DebugInfo/X86/sret.ll |
 | llvm/test/CodeGen/AArch64/combine-loads.ll |
 | llvm/test/DebugInfo/Mips/delay-slot.ll |
 | llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll |
 | llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll |
 | llvm/test/DebugInfo/X86/op_deref.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll |
 | llvm/test/DebugInfo/X86/fission-ranges.ll |
 | llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll |
 | llvm/test/CodeGen/X86/pr39733.ll |
 | llvm/test/CodeGen/ARM/crash-greedy-v6.ll |
 | llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll |
 | llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/var_arg.ll |
 | llvm/test/CodeGen/PowerPC/anon_aggr.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll |
 | llvm/test/CodeGen/X86/pr1489.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll |
 | llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll |
 | llvm/test/CodeGen/X86/swifterror.ll |
Commit
a66fca44ac926b25820f0e9344db1947d966291b
by Matthew.ArsenaultRegAllocFast: Add extra DBG_VALUE for live out spills
This allows LiveDebugValues to insert the proper DBG_VALUEs in live out blocks if a spill is inserted before the use of a register. Previously, this would see the register use as the last DBG_VALUE, even though the stack slot should be treated as the live out value.
This avoids an lldb test regression when D52010 is re-applied.
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 | llvm/test/DebugInfo/X86/subreg.ll |
 | llvm/lib/CodeGen/RegAllocFast.cpp |
 | llvm/test/DebugInfo/X86/sret.ll |
 | llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir |
 | llvm/test/DebugInfo/X86/op_deref.ll |
 | llvm/test/DebugInfo/X86/parameters.ll |
 | llvm/test/DebugInfo/X86/fission-ranges.ll |
Commit
d93459992e559e774e7b14208e5bd8bf27a58280
by Matthew.ArsenaultLiveDebugValues: Fix typos and indentation
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 | llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp |
Commit
5aa1119537fe6569b54d0da4d9d649a6940decff
by Matthew.ArsenaultGlobalISel: Assert if MoreElements uses a non-vector type
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 | llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp |
Commit
2ef73025afda6481625b74eb99cdbc2eb1cfef95
by llvm-dev[InstCombine] Remove %tmp variable names from bswap-fold tests
Appease update_test_checks script that was complaining about potential %TMP clashes
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 | llvm/test/Transforms/InstCombine/bswap-fold.ll |
Commit
3a7487f903e2a6be29de39058eee2372e30798d5
by Xiangling.Liao[FE] Use preferred alignment instead of ABI alignment for complete object when applicable
On some targets, preferred alignment is larger than ABI alignment in some cases. For example, on AIX we have special power alignment rules which would cause that. Previously, to support those cases, we added a “PreferredAlignment” field in the `RecordLayout` to store the AIX special alignment values in “PreferredAlignment” as the community suggested.
However, that patch alone is not enough. There are places in the Clang where `PreferredAlignment` should have been used instead of ABI-specified alignment. This patch is aimed at fixing those spots.
Differential Revision: https://reviews.llvm.org/D86790
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 | clang/test/CodeGen/aix-alignment.c |
 | clang/lib/CodeGen/TargetInfo.cpp |
 | clang/include/clang/AST/ASTContext.h |
 | clang/lib/CodeGen/ItaniumCXXABI.cpp |
 | clang/test/CodeGenCXX/aix-alignment.cpp |
 | clang/lib/CodeGen/CGExprCXX.cpp |
 | clang/lib/AST/ASTContext.cpp |