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Success Build clang-r365512-t57830-b57830.tar.gz (Jul 9, 2019 10:43:19 AM)


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Build Log

Revision: 364448
  1. [AMDGPU] Created a sub-register class for the return address operand in the return instruction.

    Function return instruction lowering, currently uses the fixed register pair s[30:31] for holding
    the return address. It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class
    exclusive of the CSRs, and used this regclass while lowering the return instruction.

    Reviewed By: arsenm

    Differential Revision: (detail)
    by cdevadas
  2. [RISCV] Fix ICE in isDesirableToCommuteWithShift

    There was an error being thrown from isDesirableToCommuteWithShift in
    some tests. This was tracked down to the method being called before
    legalisation, with an extended value type, not a machine value type.

    In the case I diagnosed, the error was only hit with an instruction sequence
    involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is
    instead an Extended ValueType which was causing the issue.

    I have added a test to cover this case, and fixed the error in the callback.

    Reviewers: asb, luismarques

    Reviewed By: asb

    Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits

    Tags: #llvm

    Differential Revision: (detail)
    by lenary
  3. [AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches

    If we have an icmp->brcond->br sequence where the brcond just branches to the
    next block jumping over the br, while the br takes the false edge, then we can
    modify the conditional branch to jump to the br's target while inverting the
    condition of the incoming icmp. This means we can eliminate the br as an
    unconditional branch to the fallthrough block.

    Differential Revision: (detail)
    by Amara Emerson
  4. [mips] Show error in case of using FP64 mode on pre MIPS32R2 CPU (detail)
    by atanasyan
  5. [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC

    Support for 64-bit coprocessors on a 32-bit architecture
    was added in `MIPS32 R2`. (detail)
    by atanasyan
Revision: 364448
  1. Revert Revert Devirtualize destructor of final class.

    Revert r364359 and recommit r364100.

    r364100 was reverted as r364359 due to an internal test failure, but it was a
    false alarm. (detail)
    by yamauchi

Started by upstream project relay-lnt-ctmark build number 8784
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