SuccessChanges

Summary

  1. [AMDGPU] Created a sub-register class for the return address operand in the return instruction. Function return instruction lowering, currently uses the fixed register pair s[30:31] for holding the return address. It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class exclusive of the CSRs, and used this regclass while lowering the return instruction. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D63924
  2. [RISCV] Fix ICE in isDesirableToCommuteWithShift Summary: There was an error being thrown from isDesirableToCommuteWithShift in some tests. This was tracked down to the method being called before legalisation, with an extended value type, not a machine value type. In the case I diagnosed, the error was only hit with an instruction sequence involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is instead an Extended ValueType which was causing the issue. I have added a test to cover this case, and fixed the error in the callback. Reviewers: asb, luismarques Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64425
  3. [AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches If we have an icmp->brcond->br sequence where the brcond just branches to the next block jumping over the br, while the br takes the false edge, then we can modify the conditional branch to jump to the br's target while inverting the condition of the incoming icmp. This means we can eliminate the br as an unconditional branch to the fallthrough block. Differential Revision: https://reviews.llvm.org/D64354
  4. [mips] Show error in case of using FP64 mode on pre MIPS32R2 CPU
  5. [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC Support for 64-bit coprocessors on a 32-bit architecture was added in `MIPS32 R2`.
Revision 365512 by cdevadas:
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.

Function return instruction lowering, currently uses the fixed register pair s[30:31] for holding
the return address. It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class
exclusive of the CSRs, and used this regclass while lowering the return instruction.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D63924
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpptrunk/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.tdtrunk/lib/Target/AMDGPU/SIRegisterInfo.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.tdtrunk/lib/Target/AMDGPU/SOPInstructions.td
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/call-graph-register-usage.lltrunk/test/CodeGen/AMDGPU/call-graph-register-usage.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/call-preserved-registers.lltrunk/test/CodeGen/AMDGPU/call-preserved-registers.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/callee-frame-setup.lltrunk/test/CodeGen/AMDGPU/callee-frame-setup.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.lltrunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/chain-hi-to-lo.lltrunk/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.lltrunk/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.log.f16.lltrunk/test/CodeGen/AMDGPU/llvm.log.f16.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.log10.f16.lltrunk/test/CodeGen/AMDGPU/llvm.log10.f16.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/load-lo16.lltrunk/test/CodeGen/AMDGPU/load-lo16.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/nested-calls.lltrunk/test/CodeGen/AMDGPU/nested-calls.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/wave32.lltrunk/test/CodeGen/AMDGPU/wave32.ll
Revision 365511 by lenary:
[RISCV] Fix ICE in isDesirableToCommuteWithShift

Summary:
There was an error being thrown from isDesirableToCommuteWithShift in
some tests. This was tracked down to the method being called before
legalisation, with an extended value type, not a machine value type.

In the case I diagnosed, the error was only hit with an instruction sequence
involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is
instead an Extended ValueType which was causing the issue.

I have added a test to cover this case, and fixed the error in the callback.

Reviewers: asb, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64425
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpptrunk/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/RISCV/add-before-shl.lltrunk/test/CodeGen/RISCV/add-before-shl.ll
Revision 365510 by aemerson:
[AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches

If we have an icmp->brcond->br sequence where the brcond just branches to the
next block jumping over the br, while the br takes the false edge, then we can
modify the conditional branch to jump to the br's target while inverting the
condition of the incoming icmp. This means we can eliminate the br as an
unconditional branch to the fallthrough block.

Differential Revision: https://reviews.llvm.org/D64354
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerHelper.htrunk/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modified/llvm/trunk/include/llvm/CodeGen/MachineOperand.htrunk/include/llvm/CodeGen/MachineOperand.h
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/CombinerHelper.cpptrunk/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpptrunk/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.lltrunk/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mirtrunk/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
The file was modified/llvm/trunk/test/CodeGen/AArch64/speculation-hardening.lltrunk/test/CodeGen/AArch64/speculation-hardening.ll
Revision 365508 by atanasyan:
[mips] Show error in case of using FP64 mode on pre MIPS32R2 CPU
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpptrunk/lib/Target/Mips/MipsSubtarget.cpp
The file was modified/llvm/trunk/test/CodeGen/Mips/fp64a.lltrunk/test/CodeGen/Mips/fp64a.ll
Revision 365507 by atanasyan:
[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC

Support for 64-bit coprocessors on a 32-bit architecture
was added in `MIPS32 R2`.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/Mips/abiflags32.lltrunk/test/CodeGen/Mips/abiflags32.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-fpxx1.lltrunk/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/cconv/return-hard-float.lltrunk/test/CodeGen/Mips/cconv/return-hard-float.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/cfi_offset.lltrunk/test/CodeGen/Mips/cfi_offset.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/fp-contract.lltrunk/test/CodeGen/Mips/fp-contract.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/fp64a.lltrunk/test/CodeGen/Mips/fp64a.ll
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The file was modified/llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.lltrunk/test/CodeGen/Mips/msa/3rf_float_int.ll
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The file was modified/llvm/trunk/test/CodeGen/Mips/msa/3rf_q.lltrunk/test/CodeGen/Mips/msa/3rf_q.ll
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The file was modified/llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.lltrunk/test/CodeGen/Mips/msa/arithmetic_float.ll
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The file was modified/llvm/trunk/test/CodeGen/Mips/msa/bitcast.lltrunk/test/CodeGen/Mips/msa/bitcast.ll
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The file was modified/llvm/trunk/test/CodeGen/Mips/msa/compare_float.lltrunk/test/CodeGen/Mips/msa/compare_float.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/elm_copy.lltrunk/test/CodeGen/Mips/msa/elm_copy.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.lltrunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/elm_insv.lltrunk/test/CodeGen/Mips/msa/elm_insv.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/elm_move.lltrunk/test/CodeGen/Mips/msa/elm_move.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.lltrunk/test/CodeGen/Mips/msa/elm_shift_slide.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/endian.lltrunk/test/CodeGen/Mips/msa/endian.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/frameindex.lltrunk/test/CodeGen/Mips/msa/frameindex.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/i10.lltrunk/test/CodeGen/Mips/msa/i10.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/i5-a.lltrunk/test/CodeGen/Mips/msa/i5-a.ll
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The file was modified/llvm/trunk/test/CodeGen/Mips/msa/i5-s.lltrunk/test/CodeGen/Mips/msa/i5-s.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.lltrunk/test/CodeGen/Mips/msa/i5_ld_st.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/i8.lltrunk/test/CodeGen/Mips/msa/i8.ll
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The file was modified/llvm/trunk/test/CodeGen/Mips/msa/inline-asm.lltrunk/test/CodeGen/Mips/msa/inline-asm.ll
The file was modified/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1704963983.lltrunk/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
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The file was modified/llvm/trunk/test/CodeGen/Mips/stack-alignment.lltrunk/test/CodeGen/Mips/stack-alignment.ll

Summary

  1. Revert Revert Devirtualize destructor of final class. Revert r364359 and recommit r364100. r364100 was reverted as r364359 due to an internal test failure, but it was a false alarm.
Revision 365509 by yamauchi:
Revert Revert Devirtualize destructor of final class.

Revert r364359 and recommit r364100.

r364100 was reverted as r364359 due to an internal test failure, but it was a
false alarm.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/CodeGen/CGExprCXX.cpptrunk/lib/CodeGen/CGExprCXX.cpp
The file was added/cfe/trunk/test/CodeGenCXX/devirtualize-dtor-final.cpptrunk/test/CodeGenCXX/devirtualize-dtor-final.cpp