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Success Build clang-r365383-t57803-b57803.tar.gz (Jul 8, 2019 2:41:39 PM)

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Build Log

Revision: 364448
Changes
  1. Remove extraRecipients for sanitizer-x86_64-linux-gn

    Reviewers: eugenis

    Differential Revision: https://reviews.llvm.org/D64363 (detail)
    by Vitaly Buka
Revision: 364448
Changes
  1. Revert "Reapply [llvm-ar][test] Increase llvm-ar test coverage"

    llvm-ar.extract.test has been failing on greendragon and gone unfixed. (detail)
    by jfb
  2. [InstCombine] fold insertelement into splat of same scalar

    Forming the canonical splat shuffle improves analysis and
    may allow follow-on transforms (although some possibilities
    are missing as shown in the test diffs).

    The backend generically turns these patterns into build_vector,
    so there should be no codegen regressions. All targets are
    expected to be able to lower splats efficiently. (detail)
    by spatel
  3. AMDGPU: Fix unused variable in release build (detail)
    by arsenm
  4. Teach the symbolizer lib symbolize objects directly.

    Currently, the symbolizer lib can only symbolize a file on disk.
    This patch teaches the symbolizer lib to symbolize objects.
    llvm-objdump needs this to support archive disassembly with source info.

    https://bugs.llvm.org/show_bug.cgi?id=41871

    Reviewed by: jhenderson, grimar, MaskRay

    Differential Revision: https://reviews.llvm.org/D63521 (detail)
    by yuanfang
  5. AMDGPU: Fix stray typing (detail)
    by arsenm
  6. AMDGPU: Make s34 the FP register

    Make the FP register callee saved.

    This is tricky because now the FP needs to be spilled in the prolog
    relative to the incoming SP register, rather than the frame register
    used throughout the rest of the function. I don't like how this
    bypassess the standard mechanism for CSR spills just to get the
    correct insert point. I may look for a better solution, since all CSR
    VGPRs may also need to have all lanes activated. Another option might
    be to make getFrameIndexReference change the base register if the
    frame index is a CSR, and then try to figure out the right insertion
    point in emitProlog.

    If there is a free VGPR lane available for SGPR spilling, try to use
    it for the FP. If that would require intrtoducing a new VGPR spill,
    try to use a free call clobbered SGPR. Only fallback to introducing a
    new VGPR spill as a last resort.

    This also doesn't attempt to handle SGPR spilling with scalar stores. (detail)
    by arsenm
  7. RegUsageInfoCollector: Don't iterate all regs for every reg class

    This is extremly slow on AMDGPU, which has a lot of physical register
    and a lot of register classes.

    determineCalleeSaves, via MachineRegisterInfo::isPhysRegUsed already
    added all of the super registers to the saved set. (detail)
    by arsenm
  8. AMDGPU: Move DEBUG_TYPE definition below includes (detail)
    by arsenm
  9. Keep the order of the basic blocks in the cloned loop as the original
    loop
    Summary:
    Do the cloning in two steps, first allocate all the new loops, then
    clone the basic blocks in the same order as the original loop.
    Reviewer: Meinersbur, fhahn, kbarton, hfinkel
    Reviewed By: hfinkel
    Subscribers: hfinkel, hiraditya, llvm-commits
    Tag: https://reviews.llvm.org/D64224
    Differential Revision: (detail)
    by whitneyt
  10. Fix issues building libraries as more than one type with Xcode

    Summary:
    CMake+Xcode doesn't seem to handle targets that only have object
    sources. This patch works around that limitation by adding a dummy
    soruce file to any library target that is generated by llvm_add_library
    when object libraries are generated.

    Object libraries are generated whenever llvm_add_library is passed more
    than one library type, which is now the default case for clang static
    libraries (which generate STATIC and OBJECT libraries).

    Reviewers: zturner, compnerd, joanlluch

    Reviewed By: joanlluch

    Subscribers: joanlluch, xbolva00, mgorny, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64300 (detail)
    by cbieneman
  11. [SCEV] Fix for PR42397. SCEVExpander wrongly adds nsw to shl instruction.

    Change-Id: I76c9f628c092ae3e6e78ebdaf55cec726e25d692 (detail)
    by dendibakh
  12. [InstCombine] add tests for insert of same splatted scalar; NFC (detail)
    by spatel
  13. Update gn files (detail)
    by Vitaly Buka
  14. Revert "[BPF] add new intrinsics preserve_{array,union,struct}_access_index"

    This reverts commit r365352.

    Test ThinLTO/X86/lazyload_metadata.ll failed. Revert the commit
    and at the same time to fix the issue. (detail)
    by yhs
  15. Update gn files (detail)
    by Vitaly Buka
  16. [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.

    Corrected a typo. (detail)
    by dpreobra
  17. [BPF] add new intrinsics preserve_{array,union,struct}_access_index

    For background of BPF CO-RE project, please refer to
      http://vger.kernel.org/bpfconf2019.html
    In summary, BPF CO-RE intends to compile bpf programs
    adjustable on struct/union layout change so the same
    program can run on multiple kernels with adjustment
    before loading based on native kernel structures.

    In order to do this, we need keep track of GEP(getelementptr)
    instruction base and result debuginfo types, so we
    can adjust on the host based on kernel BTF info.
    Capturing such information as an IR optimization is hard
    as various optimization may have tweaked GEP and also
    union is replaced by structure it is impossible to track
    fieldindex for union member accesses.

    Three intrinsic functions, preserve_{array,union,struct}_access_index,
    are introducted.
      addr = preserve_array_access_index(base, index, dimension)
      addr = preserve_union_access_index(base, di_index)
      addr = preserve_struct_access_index(base, gep_index, di_index)
    here,
      base: the base pointer for the array/union/struct access.
      index: the last access index for array, the same for IR/DebugInfo layout.
      dimension: the array dimension.
      gep_index: the access index based on IR layout.
      di_index: the access index based on user/debuginfo types.

    For example, for the following example,
      $ cat test.c
      struct sk_buff {
         int i;
         int b1:1;
         int b2:2;
         union {
           struct {
             int o1;
             int o2;
           } o;
           struct {
             char flags;
             char dev_id;
           } dev;
           int netid;
         } u[10];
      };

      static int (*bpf_probe_read)(void *dst, int size, const void *unsafe_ptr)
          = (void *) 4;

      #define _(x) (__builtin_preserve_access_index(x))

      int bpf_prog(struct sk_buff *ctx) {
        char dev_id;
        bpf_probe_read(&dev_id, sizeof(char), _(&ctx->u[5].dev.dev_id));
        return dev_id;
      }
      $ clang -target bpf -O2 -g -emit-llvm -S -mllvm -print-before-all \
        test.c >& log

    The generated IR looks like below:

      ...
      define dso_local i32 @bpf_prog(%struct.sk_buff*) #0 !dbg !15 {
        %2 = alloca %struct.sk_buff*, align 8
        %3 = alloca i8, align 1
        store %struct.sk_buff* %0, %struct.sk_buff** %2, align 8, !tbaa !45
        call void @llvm.dbg.declare(metadata %struct.sk_buff** %2, metadata !43, metadata !DIExpression()), !dbg !49
        call void @llvm.lifetime.start.p0i8(i64 1, i8* %3) #4, !dbg !50
        call void @llvm.dbg.declare(metadata i8* %3, metadata !44, metadata !DIExpression()), !dbg !51
        %4 = load i32 (i8*, i32, i8*)*, i32 (i8*, i32, i8*)** @bpf_probe_read, align 8, !dbg !52, !tbaa !45
        %5 = load %struct.sk_buff*, %struct.sk_buff** %2, align 8, !dbg !53, !tbaa !45
        %6 = call [10 x %union.anon]* @llvm.preserve.struct.access.index.p0a10s_union.anons.p0s_struct.sk_buffs(
             %struct.sk_buff* %5, i32 2, i32 3), !dbg !53, !llvm.preserve.access.index !19
        %7 = call %union.anon* @llvm.preserve.array.access.index.p0s_union.anons.p0a10s_union.anons(
             [10 x %union.anon]* %6, i32 1, i32 5), !dbg !53
        %8 = call %union.anon* @llvm.preserve.union.access.index.p0s_union.anons.p0s_union.anons(
             %union.anon* %7, i32 1), !dbg !53, !llvm.preserve.access.index !26
        %9 = bitcast %union.anon* %8 to %struct.anon.0*, !dbg !53
        %10 = call i8* @llvm.preserve.struct.access.index.p0i8.p0s_struct.anon.0s(
             %struct.anon.0* %9, i32 1, i32 1), !dbg !53, !llvm.preserve.access.index !34
        %11 = call i32 %4(i8* %3, i32 1, i8* %10), !dbg !52
        %12 = load i8, i8* %3, align 1, !dbg !54, !tbaa !55
        %13 = sext i8 %12 to i32, !dbg !54
        call void @llvm.lifetime.end.p0i8(i64 1, i8* %3) #4, !dbg !56
        ret i32 %13, !dbg !57
      }

      !19 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "sk_buff", file: !3, line: 1, size: 704, elements: !20)
      !26 = distinct !DICompositeType(tag: DW_TAG_union_type, scope: !19, file: !3, line: 5, size: 64, elements: !27)
      !34 = distinct !DICompositeType(tag: DW_TAG_structure_type, scope: !26, file: !3, line: 10, size: 16, elements: !35)

    Note that @llvm.preserve.{struct,union}.access.index calls have metadata llvm.preserve.access.index
    attached to instructions to provide struct/union debuginfo type information.

    For &ctx->u[5].dev.dev_id,
      . The "%6 = ..." represents struct member "u" with index 2 for IR layout and index 3 for DI layout.
      . The "%7 = ..." represents array subscript "5".
      . The "%8 = ..." represents union member "dev" with index 1 for DI layout.
      . The "%10 = ..." represents struct member "dev_id" with index 1 for both IR and DI layout.

    Basically, traversing the use-def chain recursively for the 3rd argument of bpf_probe_read() and
    examining all preserve_*_access_index calls, the debuginfo struct/union/array access index
    can be achieved.

    The intrinsics also contain enough information to regenerate codes for IR layout.
    For array and structure intrinsics, the proper GEP can be constructed.
    For union intrinsics, replacing all uses of "addr" with "base" should be enough.

    Signed-off-by: Yonghong Song <yhs@fb.com>

    Differential Revision: https://reviews.llvm.org/D61810 (detail)
    by yhs
  18. [WebAssembly] tablegen: distinguish float/int immediate operands.

    Summary:
    Before, they were one category of operands which could cause
    crashes in non-sensical combinations, e.g. "f32.const symbol".
    Now these are forced to be an error.

    Reviewers: dschuff

    Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64039 (detail)
    by aardappel
  19. AMDGPU: Remove mubuf specific PatFrags

    These are identical to the *_global PatFrag, and will only create more
    work to get the GlobalISel importer to handle them. (detail)
    by arsenm
  20. AMDGPU: Move waitcnt intrinsic to instruction definition pattern (detail)
    by arsenm
  21. [llvm\test\Object] - An initial step to cleanup the test cases.

    This patch removes trivial-object-test.elf-i386,
    trivial-object-test.elf-x86-64 and trivial-object-test2.elf-x86-64
    precompiled objects from test/Object/Inputs folder.

    I adjusted the existent test cases to use YAML instead.

    Differential revision: https://reviews.llvm.org/D64206 (detail)
    by grimar
  22. [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.

    Summary of changes:
    - added description of GFX10;
    - added description of operands sccz, vccz, lds_direct, etc;
    - minor bugfixing and improvements. (detail)
    by dpreobra
  23. Add, and infer, a nofree function attribute

    Removing dead code leftover from refactor.

    Reviewers: jdoerfert

    Differential Revision: https://reviews.llvm.org/D49165 (detail)
    by homerdin
  24. GlobalISel: Convert some build functions to using SrcOp/DstOp (detail)
    by arsenm
  25. [InstCombine] canonicalize insert+splat to/from element 0 of vector

    We recognize a splat from element 0 in (VectorUtils) llvm::getSplatValue()
    and also in ShuffleVectorInst::isZeroEltSplatMask(), so this converts
    to that form for better matching.

    The backend generically turns these patterns into build_vector,
    so there should be no codegen difference. (detail)
    by spatel
  26. [Bitcode][NFC] Remove unused variable from BitcodeAnalyzer (detail)
    by thegameg
  27. Teach the IRBuilder about fadd and friends.

    The IRBuilder has calls to create floating point instructions like fadd.
    It does not have calls to create constrained versions of them. This patch
    adds support for constrained creation of fadd, fsub, fmul, fdiv, and frem.

    Reviewed by: John McCall, Sanjay Patel
    Approved by: John McCall
    Differential Revision: https://reviews.llvm.org/D53157 (detail)
    by kpn
  28. Add, and infer, a nofree function attribute

    This patch adds a function attribute, nofree, to indicate that a function does
    not, directly or indirectly, call a memory-deallocation function (e.g., free,
    C++'s operator delete).

    Reviewers: jdoerfert

    Differential Revision: https://reviews.llvm.org/D49165 (detail)
    by homerdin
  29. [docs][llvm-readobj][llvm-readelf] Improve wording (detail)
    by jhenderson
  30. [InstCombine] fix typo in test; NFC

    I added this test in rL365325, but didn't mean to create an undef insert. (detail)
    by spatel
  31. [PowerPC][NFC]Update testcases using script. (detail)
    by jsji
  32. [X86] ISD::INSERT_SUBVECTOR - use uint64_t index. NFCI.

    Keep the uint64_t type from getConstantOperandVal to stop truncation/extension overflow warnings in MSVC in subvector index math. (detail)
    by rksimon
  33. [Triple] Add isRISCV function

    This matches isARM, isThumb, isAArch64 and similar helpers. Future commits
    which clean-up code that currently checks for Triple::riscv32 ||
    Triple::riscv64.

    Differential Revision: https://reviews.llvm.org/D54215
    Patch by Simon Cook.
    Test case added by Alex Bradbury. (detail)
    by asb
  34. [InstCombine] add tests for splat shuffles; NFC (detail)
    by spatel
  35. [Float2Int] Add support for unary FNeg to Float2Int

    Differential Revision: https://reviews.llvm.org/D63941 (detail)
    by mcinally
  36. [MIPS GlobalISel] Register bank select for G_LOAD. Select i64 load

    Select gprb or fprb when loaded value is used by either:
    copy to physical register or
    instruction with only one mapping available for that use operand.

    Load of integer s64 is handled with narrowScalar when mapping is applied,
    produced artifacts are combined away. Manually set gprb to all register
    operands of instructions created during narrowScalar.

    Differential Revision: https://reviews.llvm.org/D64269 (detail)
    by petar.avramovic
  37. [MIPS GlobalISel] Register bank select for G_STORE. Select i64 store

    Select gprb or fprb when stored value is defined by either:
    copy from physical register or
    instruction with only one mapping available for that def operand.

    Store of integer s64 is handled with narrowScalar when mapping is applied,
    produced artifacts are combined away. Manually set gprb to all register
    operands of instructions created during narrowScalar.

    Differential Revision: https://reviews.llvm.org/D64268 (detail)
    by petar.avramovic
  38. [AMDGPU][MC] Corrected parsing of FLAT offset modifier

    Summary of changes:

    - simplified handling of FLAT offset: offset_s13 and offset_u12 have been replaced with flat_offset;
    - provided information about error position for pre-gfx9 targets;
    - improved errors handling.

    Reviewers: artem.tamazov, arsenm, rampitec

    Differential Revision: https://reviews.llvm.org/D64244 (detail)
    by dpreobra
Revision: 364448
Changes
  1. [Sema] Resolve placeholder types before type deduction to silence
    spurious `-Warc-repeated-use-of-weak` warnings

    The spurious -Warc-repeated-use-of-weak warnings are issued when an
    initializer expression uses a weak ObjC pointer.

    My first attempt to silence the warnings (r350917) caused clang to
    reject code that is legal in C++17. The patch is based on the feedback I
    received from Richard when the patch was reverted.

    http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20190422/268945.html
    http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20190422/268943.html

    Differential Revision: https://reviews.llvm.org/D62645 (detail)
    by ahatanak
  2. Add missing declarations of explicit member specializations.

    This should fix the build under -Wundefined-func-template and certain
    versions of GCC. (detail)
    by rsmith
  3. [OPENMP]Improve error message for device unsupported types.

    Provide more data to the user in the error message about unsupported
    type for device compilation. (detail)
    by abataev
  4. Replace temporary variable matches in test since r363952 causes an
    extra temporary variable to be created. (detail)
    by akhuang
  5. [Syntax] Introduce syntax trees

    Summary:
    A tooling-focused alternative to the AST. This commit focuses on the
    memory-management strategy and the structure of the AST.

    More to follow later:
      - Operations to mutate the syntax trees and corresponding textual
        replacements.
      - Mapping between clang AST nodes and syntax tree nodes.
      - More node types corresponding to the language constructs.

    Reviewers: sammccall

    Reviewed By: sammccall

    Subscribers: llvm-commits, mgorny, cfe-commits

    Tags: #clang, #llvm

    Differential Revision: https://reviews.llvm.org/D61637 (detail)
    by ibiryukov
  6. Add nofree attribute to CodeGenOpenCL/convergent.cl test

    The revision at https://reviews.llvm.org/rL365336 added inference of the nofree
    attribute.  This revision updates the test to reflect this.

    Differential Revision: https://reviews.llvm.org/D49165 (detail)
    by homerdin
  7. [OPENMP]Add -Wunintialized to the erroneous tests for future fix PR42392,
    NFC. (detail)
    by abataev
  8. [clangd] A code tweak to expand a macro

    Reviewers: sammccall

    Reviewed By: sammccall

    Subscribers: mgorny, MaskRay, jkorous, arphaman, kadircet, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D61681 (detail)
    by ibiryukov
  9. [RISCV][NFC] Make use of Triple::isRISCV

    Use new helper introduced in rL365327. (detail)
    by asb
Revision: 364448
Changes
  1. A test commit following 'Obtaining Commit Access' (https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access) (detail)
    by jcai19
  2. [clangd] Don't insert absolute paths, give up instead.

    Summary: Also implement resolution of paths relative to mainfile without HeaderSearchInfo.

    Reviewers: kadircet

    Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64293 (detail)
    by sammccall
  3. [clangd] Use -completion-style=bundled by default if signature help is available

    Summary:
    I didn't manage to find something nicer than optional<bool>, but at least I
    found a sneakier comment.

    Reviewers: kadircet

    Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64216 (detail)
    by sammccall
  4. [clangd] A code tweak to expand a macro

    Reviewers: sammccall

    Reviewed By: sammccall

    Subscribers: mgorny, MaskRay, jkorous, arphaman, kadircet, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D61681 (detail)
    by ibiryukov
Revision: 364448
Changes
  1. [sanitizers][windows] Rtl-Heap Interception and tests
       - Adds interceptors for Rtl[Allocate|Free|Size|ReAllocate]Heap
       - Adds unit tests for the new interceptors and expands HeapAlloc
         tests to demonstrate new functionality.
       Reviewed as D62927 (detail)
    by mcgov
  2. Revert "[TSan] Attempt to fix iOS on-device test"

    This reverts commit a2ca358291a3a621bfae66eeb01f51eeb69d2dd4. (detail)
    by yln
  3. Revert "[TSan] Attempt to fix linker error for Linux on AArch64"

    This reverts commit be4148062b155f3be52e0f6ebcb228f2dc137dcf. (detail)
    by yln
Revision: 364448
Changes
  1. Revert "[libc++] Take 2: Do not cleverly link against libc++abi just because it happens to be there"

    r365326 still breaks bots:
    http://lab.llvm.org:8011/builders/netbsd-amd64/builds/20712/steps/ninja%20build%20local/logs/stdio
    http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/39477/steps/test%20tsan%20in%20debug%20compiler-rt%20build/logs/stdio

    And probably others

    This reverts commit 945b9ec0693390ef35fe8c6b774495312246b8b6. (detail)
    by Vitaly Buka
  2. [libc++] Take 2: Do not cleverly link against libc++abi just because it happens to be there

    Summary:
    Otherwise, when libcxxabi is not an enabled project in the monorepo, we
    get a link error because we try to link against non-existent cxxabi_shared.

    More generally, we shouldn't change the behavior of the build based on
    implicit things like whether a file happens to be at a specific path or
    not.

    This is a re-application of r365222 that had been reverted in r365233
    because it broke the build bots. However, the build bots now specify
    explicitly what ABI library they want to use (libc++abi), so this
    commit should now be OK to merge.

    Differential Revision: https://reviews.llvm.org/D63883 (detail)
    by Louis Dionne

Started by upstream project relay-lnt-ctmark build number 8758
originally caused by:

This run spent:

  • 7 min 11 sec waiting;
  • 13 min build duration;
  • 13 min total from scheduled to completion.