Started 7 days 17 hr ago
Took 3 hr 17 min on green-dragon-16

Success Build rL:371412 - C:371410 - #515 (Sep 9, 2019 8:46:22 AM)

  • : 371412
  • : 371410
  • : 371400
  • : 364589
  • : 371154
  • : 371324
  • : 371408
  1. AMDGPU/GlobalISel: Select G_PTR_MASK (detail/ViewSVN)
    by arsenm
  2. AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads

    The pointer is always a VGPR. Also fix hardcoding the pointer size to
    64. (detail/ViewSVN)
    by arsenm
  3. [NFC] Add aacps bitfields access test (detail/ViewSVN)
    by dnsampaio
  4. AMDGPU/GlobalISel: Use known bits for selection (detail/ViewSVN)
    by arsenm
  5. [clangd] Use pre-populated mappings for standard symbols

    This takes ~5% of time when running clangd unit tests.

    To achieve this, move mapping of system includes out of CanonicalIncludes
    and into a separate class

    Reviewers: sammccall, hokein

    Reviewed By: sammccall

    Subscribers: MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by ibiryukov
  6. AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic (detail/ViewSVN)
    by arsenm
  7. AMDGPU/GlobalISel: Try generated matcher before add/sub code

    This will allow optimization patterns which fold adds away to work. (detail/ViewSVN)
    by arsenm
  8. [ARM] Remove some spurious MVE reduction instructions.

    The family of 'dual-accumulating' vector multiply-add instructions
    (VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
    unsigned integer types, and they all have an 'exchange' variant (with
    an X in the name) that modifies which pairs of vector lanes in the two
    inputs are multiplied together. But there's a clause in the spec that
    says that the X variants //don't// operate on unsigned integer types,
    only signed. You can have X, or unsigned, or neither, but not both.

    We didn't notice that clause when we implemented the MC support for
    these instructions, so LLVM believes that things like VMLADAVX.U8 do
    exist, contradicting the spec. Here I fix that by conditioning them
    out in Tablegen.

    In order to do that, I've reversed the nesting order of the Tablegen
    multiclasses for those instructions. Previously, the innermost
    multiclass generated the X and not-X variants, and the one outside
    that generated the A and not-A variants. Now X is done by the outer
    multiclass, which allows me to bypass that one when I only want the
    two not-X variants.

    Changing the multiclass nesting order also changes the names of the
    instruction ids unless I make a special effort not to. I decided that
    while I was changing them anyway I'd make them look nicer; so now the
    instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32,
    instead of cumbersome _noacc_noexch suffixes.

    The corresponding multiply-subtract instructions are unaffected. Those
    don't accept unsigned types at all, either in the spec or in LLVM.

    Reviewers: ostannard, dmgreen

    Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by statham
  9. AMDGPU/GlobalISel: Remove dead patterns (detail/ViewSVN)
    by arsenm

Started by an SCM change (5 times)

This run spent:

  • 39 min waiting;
  • 3 hr 17 min build duration;
  • 3 hr 56 min total from scheduled to completion.
LLVM/Clang Warnings: 1 warning.
    Test Result (no failures)