Started 9 days 0 hr ago
Took 1 hr 15 min on green-dragon-20

Success Build rL:371428 - C:371410 - #516 (Sep 9, 2019 10:33:35 AM)

  • : 371428
  • : 371410
  • : 371400
  • : 364589
  • : 371154
  • : 371324
  • : 371422
  1. [mips] Fix decoding of microMIPS JALX instruction

    microMIPS jump and link exchange instruction stores a target in a
    26-bits field. Despite other microMIPS JAL instructions these bits
    are target address shifted right 2 bits [1]. The patch fixes the
    JALX instruction decoding and uses 2-bit shift.

    [1] MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set

    Differential Revision: (detail/ViewSVN)
    by atanasyan
  2. AMDGPU: Move MnemonicAlias out of instruction def hierarchy

    Unfortunately MnemonicAlias defines a "Predicates" field just like an
    instruction or pattern, with a somewhat different interpretation.

    This ends up overriding the intended Predicates set by
    PredicateControl on the pseudoinstruction defintions with an empty
    list. This allowed incorrectly selecting instructions that should have
    been rejected due to the SubtargetPredicate from patterns on the
    instruction definition.

    This does remove the divergent predicate from the 64-bit shift
    patterns, which were already not used for the 32-bit shift, so I'm not
    sure what the point was. This also removes a second, redundant copy of
    the 64-bit divergent patterns. (detail/ViewSVN)
    by arsenm
  3. [SLP] add test for over-vectorization (PR33958); NFC (detail/ViewSVN)
    by spatel
  4. [GlobalISel][AArch64] Handle tail calls with non-void return types

    Just return once you emit the call, which is exactly what SelectionDAG does in
    this situation.

    Update call-translator-tail-call.ll.

    Also update dllimport.ll to show that we tail call here in GISel again. Add
    -verify-machineinstrs to the GISel line too, to defend against verifier

    Differential revision: (detail/ViewSVN)
    by paquette
  5. AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE

    Handle the simple case that lowers to a constant. (detail/ViewSVN)
    by arsenm

    Treat this as legal on gfx9 since it can use S_PACK_* instructions for

    This isn't used by anything yet. The same will probably apply to
    16-bit G_BUILD_VECTOR without the trunc. (detail/ViewSVN)
    by arsenm
  7. [clangd] Attempt to fix failing Windows buildbots.

    The assertion is failing on Windows, probably because path separator is different.

    For the failure see: (detail/ViewSVN)
    by ibiryukov
  8. Revert "[MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp"

    This reverts commit 371359. I'm suspecting a miscompile, I posted a
    reproducer to (detail/ViewSVN)
    by gribozavr
  9. [yaml2obj] Simplify p_filesz/p_memsz computing

    This fixes a bug as well. When "FileSize:" (p_filesz) is specified and
    different from the actual value, the following code probably should not
    use PHeader.p_filesz:

      if (SHeader->sh_offset == PHeader.p_offset + PHeader.p_filesz)
        PHeader.p_memsz += SHeader->sh_size;

    Reviewed By: jhenderson

    Differential Revision: (detail/ViewSVN)
    by maskray
  10. [ARM] Fix loads and stores for predicate vectors

    These predicate vectors can usually be loaded and stored with a single
    instruction, a VSTR_P0. However this instruction will store the entire P0
    predicate, 16 bits, zeroextended to 32bits. Each lane of the the
    v4i1/v8i1/v16i1 representing 4/2/1 bits.

    As far as I understand, when llvm says "store this v4i1", it really does need
    to store 4 bits (or 8, that being the size of a byte, with this bottom 4 as the
    interesting bits). For example a bitcast from a v8i1 to a i8 is defined as a
    store followed by a load, which is how the code is expanded.

    So this instead lowers the v4i1/v8i1 load/store through some shuffles to get
    the bits into the correct positions. This, as you might imagine, is not as
    efficient as a single instruction. But I believe it is needed for correctness.
    v16i1 equally should not load/store 32bits, only storing the 16bits of data.
    Stack loads/stores are still using the VSTR_P0 (as can be seen by the test not
    changing). This is fine as they are self-consistent, it is only "externally
    observable loads/stores" (from our point of view) that need to be corrected.

    Differential revision: (detail/ViewSVN)
    by dmgreen
  11. AMDGPU/GlobalISel: Select atomic loads

    A new check for an explicitly atomic MMO is needed to avoid
    incorrectly matching pattern for non-atomic loads (detail/ViewSVN)
    by arsenm
  12. AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant loads (detail/ViewSVN)
    by arsenm
  13. Fix typo in comment noticed in D60295. NFCI. (detail/ViewSVN)
    by rksimon
  14. AMDGPU/GlobalISel: Fix regbankselect for uniform extloads

    There are no scalar extloads. (detail/ViewSVN)
    by arsenm
  15. AMDGPU: Remove code address space predicates

    Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due
    to not be reported as legal. (detail/ViewSVN)
    by arsenm

Started by an SCM change (10 times)

This run spent:

  • 1 hr 46 min waiting;
  • 1 hr 15 min build duration;
  • 3 hr 1 min total from scheduled to completion.
LLVM/Clang Warnings: 1 warning.
    Test Result (no failures)