Started 1 mo 4 days ago
Took 1 hr 20 min on green-dragon-17

Success Build rL:371694 - C:371694 - #559 (Sep 11, 2019 5:03:41 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 371694
  • http://llvm.org/svn/llvm-project/cfe/trunk : 371694
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 371691
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 364589
  • http://llvm.org/svn/llvm-project/zorg/trunk : 371690
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 371639
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 371661
Changes
  1. [X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs.

    AVX512 instructions can cause a frequency drop on these CPUs. This
    can negate the performance gains from using wider vectors. Enabling
    prefer-vector-width=256 will prevent generation of zmm registers
    unless explicit 512 bit operations are used in the original source
    code.

    I believe gcc and icc both do something similar to this by default.

    Differential Revision: https://reviews.llvm.org/D67259 (detail/ViewSVN)
    by ctopper
  2. [AArch64][GlobalISel] Fall back on attempts to allocate split types on the stack.

    First we were asserting that the ValNo of a VA was the wrong value. It doesn't actually
    make a difference for us in CallLowering but fix that anyway to silence the assert.

    The bigger issue was that after fixing the assert we were generating invalid MIR
    because the merging/unmerging of values split across multiple registers wasn't
    also implemented for memory locs. This happens when we run out of registers and
    have to pass the split types like i128 -> i64 x 2 on the stack. This is do-able, but
    for now just fall back. (detail/ViewSVN)
    by aemerson
  3. [GlobalISel][AArch64] Check caller for swifterror params in tailcall eligibility

    Before, we only checked the callee for swifterror. However, we should also be
    checking the caller to see if it has a swifterror parameter.

    Since we don't currently handle outgoing arguments, this didn't show up in the
    swifterror.ll testcase.

    Also, remove the swifterror checks from call-translator-tail-call.ll, since
    they are covered by the existing swifterror testing. Better to have it all in
    one place.

    Differential Revision: https://reviews.llvm.org/D67465 (detail/ViewSVN)
    by paquette
  4. [dfsan] Revert dfsan_set_label removal

    It's part of interface, maybe it is used in external code. (detail/ViewSVN)
    by Vitaly Buka
  5. Replaced non-existent argument 'target_arch' for 'vs_target_arch'. (detail/ViewSVN)
    by gkistanova
  6. Remove NOLINTs from compiler-rt (detail/ViewSVN)
    by Vitaly Buka
  7. Run svn cleanup before svn up on Windows annotated build bots

    This should help them recover better form random svn flakiness for
    another few months. (detail/ViewSVN)
    by rnk
  8. [TableGen] Skip CRLF conversion when writing output

    Doing the CRLF translation while writing the file defeats our
    optimization to not update the file if it hasn't changed.

    Fixes PR43271. (detail/ViewSVN)
    by rnk
  9. [InstCombine] rename variable for readability; NFC

    There's more that can be done here, but "OpI"
    doesn't convey that we casted to BinaryOperator. (detail/ViewSVN)
    by spatel
  10. Add some missing changes to GSYM that was addressing a gcc compilation error due to a type and variable with the same name (detail/ViewSVN)
    by dblaikie
  11. Fix mac build (detail/ViewSVN)
    by Vitaly Buka
  12. PR43278: Temporarily disable llvm-reduce tests due to exhausting temp files (detail/ViewSVN)
    by dblaikie
  13. [X86] Fix latent bugs in 32-bit CMPXCHG8B inserter

    I found three issues:
    1. the loop over E[ABCD]X copies run over BB start
    2. the direct address of cmpxchg8b could be a frame index
    3. the displacement of cmpxchg8b could be a global instead of an
       immediate

    These were all introduced together in r287875, and should be fixed with
    this change.

    Issue reported by Zachary Turner. (detail/ViewSVN)
    by rnk
  14. [ConstantFolding] Refactor math functions to use LLVM ones (NFC)

    When possible, replace calls to library routines on the host with equivalent
    ones in LLVM.

    Differential revision: https://reviews.llvm.org/D67459 (detail/ViewSVN)
    by evandro
  15. Revert [llvm-nm] Add tapi file support

    This reverts r371576 (git commit f88f46358dbffa20af3b054a9346e5154789d50f) (detail/ViewSVN)
    by cishida
  16. Update compiler-rt cpplint.py
    https://github.com/cpplint/cpplint/commit/adb3500107f409ac5491188ae652ac3f4d03d9d3 (detail/ViewSVN)
    by Vitaly Buka
  17. Revert [Object][TextAPI] NFC, fix tapi lit tests

    This reverts r371577 (git commit b2b0ccab2f76733679eeceecf31b21ebc1fe23ac) (detail/ViewSVN)
    by cishida
  18. [X86] Add test case for v16i64->v16i32 truncate on min-legal-vector-width=256.

    I think this case would crash before I added back the -x86-experimental-vector-widening command line option. Adding this test case to prevent breaking it again when we remove the option. (detail/ViewSVN)
    by ctopper
  19. [X86] Move x86_64 fp128 conversion to libcalls from type legalization to DAG legalization

    fp128 is considered a legal type for a register, but has almost no legal operations so everything needs to be converted to a libcall. Previously this was implemented by tricking type legalization into softening the operations with various checks for "is legal in hardware register" to change the behavior to still use f128 as the resulting type instead of converting to i128.

    This patch abandons this approach and instead moves the libcall conversions to LegalizeDAG. This is the approach taken by AArch64 where they also have a legal fp128 type, but no legal operations. I think this is more in spirit with how SelectionDAG's phases are supposed to work.

    I had to make some hacks for STRICT_FP_ROUND because some of the strict FP handling checks if ISD::FP_ROUND is Legal for a given result type, but I had to make ISD::FP_ROUND Custom to allow making a libcall when the input is f128. For all other types the Custom handler just returns the original node. These hacks are incomplete and don't work for a strict truncate from f128, but I don't think it worked before either since LegalizeFloatTypes doesn't know about strict ops yet. I've also raised PR43209 against AArch64 which currently crashes on a strict ftrunc from f64->f32 because of FP_ROUND being marked Custom for the same reason there.

    Differential Revision: https://reviews.llvm.org/D67128 (detail/ViewSVN)
    by ctopper
  20. AMDGPU: Move m0 initializations earlier

    Summary:
    After hoisting and merging m0 initializations schedule them as early as
    possible in the MBB. This helps the scheduler avoid hazards in some
    cases.

    Reviewers: rampitec, arsenm

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, arphaman, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67450 (detail/ViewSVN)
    by kerbowa
  21. gn build: Merge r371661 (detail/ViewSVN)
    by nico
  22. gn build: Merge r371657 (detail/ViewSVN)
    by nico
  23. [DWARF] Emit call site parameter info when tuning for lldb

    Emit debug entry values using standard DWARF5 opcodes when the debugger
    tuning is set to lldb.

    Differential Revision: https://reviews.llvm.org/D67410 (detail/ViewSVN)
    by Vedant Kumar

Started by an SCM change

This run spent:

  • 21 min waiting;
  • 1 hr 20 min build duration;
  • 1 hr 42 min total from scheduled to completion.
LLVM/Clang Warnings: 1 warning.
    Test Result (no failures)