SuccessChanges

Summary

  1. Revert r371785. r371785 is causing fails on clang-hexagon-elf buildbots.
  2. AMDGPU/GlobalISel: Select G_CTPOP
  3. DAG/GlobalISel: Correct type profile of bitcount ops The result integer does not need to be the same width as the input. AMDGPU, NVPTX, and Hexagon all have patterns working around the types matching. GlobalISel defines these as being different type indexes.
  4. [libclang] Fix UninstallAbortingLLVMFatalErrorHandler test
  5. AMDGPU: Add immarg to llvm.amdgcn.init.exec.from.input As far as I can tell this has to be a constant.
  6. LiveIntervals: Remove assertion This testcase is invalid, and caught by the verifier. For the verifier to catch it, the live interval computation needs to complete. Remove the assert so the verifier catches this, which is less confusing. In this testcase there is an undefined use of a subregister, and lanes which aren't used or defined. An equivalent testcase with the super-register shrunk to have no untouched lanes already hit this verifier error.
  7. AMDGPU: Inline constant when materalizing FI with add on gfx9 This was relying on the SGPR usable for the carry out clobber to also be used for the input. There was no carry out on gfx9. With no carry out clobber to worry about, so the literal can just be directly used with a VOP2 add.
  8. [Test] Restructure check lines to show differences between modes more clearly With the landing of the previous patch (in particular D66318) there are a lot fewer diffs now. I added an experimental O0 line, and updated all the tests to group experimental and non-experimental O0/O3 together. Skimming the remaining diffs, there's only a few which are obviously incorrect. There's a large number which are questionable, so more todo.
Revision 371799 by manojgupta:
Revert r371785.

r371785 is causing fails on clang-hexagon-elf buildbots.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td (diff)clang.src/include/clang/Basic/DiagnosticCommonKinds.td
The file was modified/cfe/trunk/lib/Frontend/InitHeaderSearch.cpp (diff)clang.src/lib/Frontend/InitHeaderSearch.cpp
The file was removed/cfe/trunk/test/Frontend/Inputs/sysroot_x86_64_cross_linux_treeclang.src/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree
The file was removed/cfe/trunk/test/Frontend/warning-poison-system-directories.cclang.src/test/Frontend/warning-poison-system-directories.c
Revision 371798 by arsenm:
AMDGPU/GlobalISel: Select G_CTPOP
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (diff)llvm.src/lib/Target/AMDGPU/SIInstrInfo.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SIInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SOPInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (diff)llvm.src/lib/Target/AMDGPU/VOP2Instructions.td
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
Revision 371797 by arsenm:
DAG/GlobalISel: Correct type profile of bitcount ops

The result integer does not need to be the same width as the input.
AMDGPU, NVPTX, and Hexagon all have patterns working around the types
matching. GlobalISel defines these as being different type indexes.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (diff)llvm.src/include/llvm/Target/TargetSelectionDAG.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SIInstructions.td
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (diff)llvm.src/lib/Target/Hexagon/HexagonPatterns.td
The file was modified/llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td (diff)llvm.src/lib/Target/NVPTX/NVPTXInstrInfo.td
The file was modified/llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td (diff)llvm.src/lib/Target/Sparc/SparcInstr64Bit.td
The file was modified/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (diff)llvm.src/lib/Target/Sparc/SparcInstrInfo.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (diff)llvm.src/lib/Target/SystemZ/SystemZInstrInfo.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
Revision 371794 by Jan Korous:
[libclang] Fix UninstallAbortingLLVMFatalErrorHandler test
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/unittests/libclang/CrashTests/LibclangCrashTest.cpp (diff)clang.src/unittests/libclang/CrashTests/LibclangCrashTest.cpp
Revision 371793 by arsenm:
AMDGPU: Add immarg to llvm.amdgcn.init.exec.from.input

As far as I can tell this has to be a constant.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td (diff)llvm.src/include/llvm/IR/IntrinsicsAMDGPU.td
Revision 371792 by arsenm:
LiveIntervals: Remove assertion

This testcase is invalid, and caught by the verifier. For the verifier
to catch it, the live interval computation needs to complete. Remove
the assert so the verifier catches this, which is less confusing.

In this testcase there is an undefined use of a subregister, and lanes
which aren't used or defined. An equivalent testcase with the
super-register shrunk to have no untouched lanes already hit this
verifier error.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/LiveInterval.cpp (diff)llvm.src/lib/CodeGen/LiveInterval.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mirllvm.src/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
Revision 371791 by arsenm:
AMDGPU: Inline constant when materalizing FI with add on gfx9

This was relying on the SGPR usable for the carry out clobber to also
be used for the input. There was no carry out on gfx9. With no carry
out clobber to worry about, so the literal can just be directly used
with a VOP2 add.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll (diff)llvm.src/test/CodeGen/AMDGPU/frame-index-elimination.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mirllvm.src/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
Revision 371790 by reames:
[Test] Restructure check lines to show differences between modes more clearly

With the landing of the previous patch (in particular D66318) there are a lot fewer diffs now.  I added an experimental O0 line, and updated all the tests to group experimental and non-experimental O0/O3 together.

Skimming the remaining diffs, there's only a few which are obviously incorrect.  There's a large number which are questionable, so more todo.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-unordered.ll (diff)llvm.src/test/CodeGen/X86/atomic-unordered.ll