Started 3 days 20 hr ago
Took 1 hr 33 min on green-dragon-20

Success Build rL:371846 - C:371839 - #579 (Sep 13, 2019 5:46:33 AM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 371846
  • http://llvm.org/svn/llvm-project/cfe/trunk : 371839
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 371822
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 364589
  • http://llvm.org/svn/llvm-project/zorg/trunk : 371835
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 371763
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 371773
Changes
  1. [ADT] Make DenseMap use allocate_buffer

    This unlocks some goodies like sized deletion and gets the alignment
    right on platforms that chose to provide a lower default new alignment. (detail/ViewSVN)
    by d0k
  2. [llvm-size] Fix spelling errors (Berkely -> Berkeley) (detail/ViewSVN)
    by jhenderson
  3. [Orc] Roll back ThreadPool to std::function

    MSVC doesn't allow move-only types in std::packaged_task. Boo. (detail/ViewSVN)
    by d0k
  4. [Orc] Address the remaining move-capture FIXMEs

    This required spreading unique_function a bit more, which I think is a
    good thing. (detail/ViewSVN)
    by d0k
  5. [X86] negateFMAOpcode - extend to support FMADDSUB/FMSUBADD and output negation. NFCI.

    Some prep work for PR42863, this change allows us to move all the FMA opcode mappings into the negateFMAOpcode helper.

    For the FMADDSUB/FMSUBADD cases, we can only negate the accumulator - any other negations will result in an error. (detail/ViewSVN)
    by rksimon
  6. [ASTImporter] Add development internals docs

    Reviewers: a_sidorin, shafik, teemperor, gamesh411, balazske, dkrupp, a.sidorin

    Subscribers: rnkovacs, Szelethus, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D66336 (detail/ViewSVN)
    by martong
  7. [ARM] Add earlyclobber for cross beat MVE instructions

    rL367544 added @earlyclobbers for the MVE VREV64 instruction. This adds the
    same for a number of other 32bit instructions that are similarly unpredictable
    if the destination equals the source (due to the cross beat nature of the
    instructions).
    This includes:
      VCADD.f32
      VCADD.i32
      VCMUL.f32
      VHCADD.s32
      VMULLT/B.s/u32
      VQDMLADH{X}.s32
      VQRDMLADH{X}.s32
      VQDMLSDH{X}.s32
      VQRDMLSDH{X}.s32
      VQDMULLT/B.s32 with Qm and Rm

    No tests here as this would require intrinsics (or very interesting codegen) to
    manifest. The tests will follow naturally as the intrinsics are added.

    Differential Revision: https://reviews.llvm.org/D67462 (detail/ViewSVN)
    by dmgreen

Started by an SCM change (5 times)

This run spent:

  • 1 hr 24 min waiting;
  • 1 hr 33 min build duration;
  • 2 hr 58 min total from scheduled to completion.
LLVM/Clang Warnings: 1 warning.
    Test Result (no failures)