Started 1 mo 0 days ago
Took 1 hr 36 min on green-dragon-22

Success Build rL:371932 - C:371924 - #599 (Sep 15, 2019 7:53:55 AM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 371932
  • http://llvm.org/svn/llvm-project/cfe/trunk : 371924
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 371926
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 364589
  • http://llvm.org/svn/llvm-project/zorg/trunk : 371835
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 371925
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 371890
Changes
  1. [ARM] Masked loads and stores

    Masked loads and store fit naturally with MVE, the instructions being easily
    predicated. This adds lowering for the simple cases of masked loads and stores.
    It does not yet deal with widening/narrowing or pre/post inc, and so is
    currently behind an option.

    The llvm masked load intrinsic will accept a "passthru" value, dictating the
    values used for the zero masked lanes. In MVE the instructions write 0 to the
    zero predicated lanes, so we need to match a passthru that isn't 0 (or undef)
    with a select instruction to pull in the correct data after the load.

    Differential Revision: https://reviews.llvm.org/D67186 (detail/ViewSVN)
    by dmgreen

Started by an SCM change (2 times)

This run spent:

  • 37 min waiting;
  • 1 hr 36 min build duration;
  • 2 hr 14 min total from scheduled to completion.
LLVM/Clang Warnings: 1 warning.
    Test Result (no failures)