SuccessChanges

Summary

  1. [libc++] Remove XFAILs for macOS 10.15, which were fixed in later dot releases (details)
  2. [libTooling] Add option for `buildAST` to report diagnostics. (details)
  3. [lldb] Merge RangeArray and RangeVector (details)
  4. AMDGPU/GlobalISel: Adjust branch target when lowering loop intrinsic (details)
  5. [Assembler] Emit summary index flags (details)
  6. Reland D74436 "Change clang option -ffp-model=precise to select ffp-contract=on"" (details)
  7. [AArch64] Add Cortex-A34 Support for clang and llvm (details)
  8. [mlir] NFC: Rename LLVMOpLowering::lowering to LLVMOpLowering::typeConverter (details)
  9. [VE] TLS codegen (details)
  10. Prevent gcc from issuing a warning upon coffnamecpy (details)
  11. Revert "Reland "[DebugInfo] Enable the debug entry values feature by default"" (details)
  12. [libc++] Add ABI list for 9.0 release (details)
  13. Add OffsetIsScalable to getMemOperandWithOffset (details)
  14. [RISCV] Implement mayBeEmittedAsTailCall for tail call optimization (details)
  15. Drop a constexpr in favor of const, MSVC complains. (details)
Commit 1cff2aa51239463456d6e5d75ff8ca3e9fa14f63 by Louis Dionne
[libc++] Remove XFAILs for macOS 10.15, which were fixed in later dot releases
The file was modifiedlibcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/facet.num.get.members/get_long.pass.cpp
The file was modifiedlibcxx/test/std/input.output/iostreams.base/ios.base/ios.types/ios_Init/ios_Init.multiple.pass.cpp
Commit 523cae324d79d2e532d2be797058a94e8214ec45 by yitzhakm
[libTooling] Add option for `buildAST` to report diagnostics.

Summary:
Currently, `buildAST[WithArgs]` either succeeds or fails.  This patch adds
support for the caller to pass a `DiagnosticConsumer` to receive all relevant
diagnostics.

Reviewers: gribozavr

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74763
The file was modifiedclang/lib/Tooling/Tooling.cpp
The file was modifiedclang/include/clang/Tooling/Tooling.h
The file was modifiedclang/unittests/Tooling/ToolingTest.cpp
Commit b807a28787638f36a907f6f3ee832b840d1be08c by pavel
[lldb] Merge RangeArray and RangeVector

The two classes are equivalent, except:
- the former uses a llvm::SmallVector (with a configurable size), while
  the latter uses std::vector.
- the former has a typo in one of the functions name

This patch just leaves one class, using llvm::SmallVector, and defaults
the small size to zero. This is the same thing we did with the
RangeDataVector class in D56170.
The file was modifiedlldb/include/lldb/Utility/RangeMap.h
The file was modifiedlldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.h
The file was modifiedlldb/include/lldb/Target/Memory.h
The file was modifiedlldb/include/lldb/Symbol/LineTable.h
The file was modifiedlldb/source/Target/Memory.cpp
The file was modifiedlldb/include/lldb/Core/dwarf.h
The file was modifiedlldb/include/lldb/Symbol/Block.h
Commit 37c452a2895071dac1782668bfcd884951ec2aa5 by Matthew.Arsenault
AMDGPU/GlobalISel: Adjust branch target when lowering loop intrinsic

This needs to steal the branch target like the other control flow
intrinsics.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit c85055b20392ab0e5d2ac2a9112224106e04f6a2 by evgeny
[Assembler] Emit summary index flags

Differential revision: https://reviews.llvm.org/D74420
The file was modifiedllvm/lib/IR/AsmWriter.cpp
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was modifiedllvm/lib/AsmParser/LLParser.h
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/IR/ModuleSummaryIndex.cpp
The file was modifiedllvm/include/llvm/IR/ModuleSummaryIndex.h
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was addedllvm/test/Assembler/summary-flags.ll
Commit cd2c5af6dfd6e32ee7043894bcb42981ce99e8ac by melanie.blower
Reland D74436 "Change clang option -ffp-model=precise to select ffp-contract=on""
    Change clang option -ffp-model=precise, the default, to select ffp-contract=on
    The patch caused some problems for PowerPC but ibm has made
    adjustments so I am resubmitting this patch.  Additionally, Andy looked
    at the performance regressions on LNT and it looks like a loop
    unrolling decision that could be adjusted.

    Reviewers: rjmccall, Andy Kaylor

    Differential Revision: https://reviews.llvm.org/D74436
The file was modifiedclang/test/CodeGen/ppc-xmmintrin.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/fp-model.c
The file was modifiedclang/docs/UsersManual.rst
The file was modifiedclang/test/CodeGen/ppc-emmintrin.c
Commit 4518aab289a090a668af0ca4ecde976e18fb2b1e by luke.geeson
[AArch64] Add Cortex-A34 Support for clang and llvm

This patch upstreams support for the AArch64 Armv8-A cpu Cortex-A34.

In detail adding support for:
- mcpu option in clang
- AArch64 Target Features in clang
- llvm AArch64 TargetParser definitions

details of the cpu can be found here:
https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34

Reviewers: SjoerdMeijer

Reviewed By: SjoerdMeijer

Subscribers: SjoerdMeijer, kristof.beyls, hiraditya, cfe-commits,
llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74483

Change-Id: Ida101fc544ca183a0a0e61a1277c8957855fde0b
The file was modifiedllvm/test/CodeGen/AArch64/remat.ll
The file was modifiedllvm/test/CodeGen/AArch64/cpus.ll
The file was modifiedllvm/include/llvm/Support/AArch64TargetParser.def
The file was modifiedllvm/unittests/Support/TargetParserTest.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
The file was modifiedclang/test/Driver/aarch64-cpus.c
The file was modifiedllvm/lib/Support/Host.cpp
The file was modifiedclang/test/Preprocessor/aarch64-target-features.c
Commit 0f04384daf78e26652bae3c5ea9cc201c9099b9d by zinenko
[mlir] NFC: Rename LLVMOpLowering::lowering to LLVMOpLowering::typeConverter

The existing name is an artifact dating back to the times when we did not have
a dedicated TypeConverter infrastructure. It is also confusing with with the
name of classes using it.

Differential revision: https://reviews.llvm.org/D74707
The file was modifiedmlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
The file was modifiedmlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
Commit 5526786a56bd5fb187a8c6f601268e58e351b3c8 by simon.moll
[VE] TLS codegen

Summary:
Codegen and tests for thread-local storage.
This implements only the general dynamic model due to limitations in nld 2.26.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D74718
The file was modifiedllvm/lib/Target/VE/VEAsmPrinter.cpp
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h
The file was modifiedllvm/lib/Target/VE/VEISelLowering.h
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp
The file was modifiedllvm/lib/Target/VE/VEISelLowering.cpp
The file was addedllvm/test/CodeGen/VE/tls.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
Commit 498a6136a271bfb95bcd9488d1036e57a5e0fae0 by sguelton
Prevent gcc from issuing a warning upon coffnamecpy

This is a follow up to d1262a6e9, more explicit to cope with GCC smartness.

Differential Revision: https://reviews.llvm.org/D74666
The file was modifiedllvm/lib/Object/WindowsResource.cpp
Commit 2bf44d11cb42a952bdeb778210d8b3e737f0b96e by djordje.todorovic
Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""

This reverts commit rGa82d3e8a6e67.
The file was modifiedllvm/test/CodeGen/X86/statepoint-allocas.ll
The file was modifiedllvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
The file was modifiedclang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
The file was modifiedllvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
The file was modifiedllvm/test/CodeGen/AArch64/arm64-anyregcc.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
The file was modifiedllvm/test/tools/llvm-locstats/locstats.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
The file was modifiedllvm/test/DebugInfo/X86/dbg-value-range.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/DebugInfo/X86/loclists-dwp.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
The file was modifiedclang/include/clang/Driver/CC1Options.td
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
The file was modifiedllvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/call-site-info-error2.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir
The file was modifiedllvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
The file was modifiedllvm/test/CodeGen/X86/xray-typed-event-log.ll
The file was modifiedllvm/lib/CodeGen/MIRParser/MIRParser.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/X86/xray-custom-log.ll
The file was modifiedllvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/locstats.ll
The file was modifiedllvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
The file was modifiedlldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was modifiedllvm/include/llvm/CodeGen/CommandFlags.inc
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
The file was modifiedllvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
The file was modifiedllvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
The file was modifiedllvm/test/CodeGen/X86/tail-dup-repeat.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-patchpoint.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
The file was modifiedllvm/test/DebugInfo/AArch64/call-site-info-output.ll
The file was modifiedllvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
The file was modifiedllvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
The file was modifiedclang/test/CodeGen/debug-info-extern-call.c
The file was modifiedllvm/lib/CodeGen/TargetOptionsImpl.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was modifiedllvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
The file was modifiedllvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
The file was modifiedllvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
The file was modifiedllvm/test/CodeGen/ARM/smml.ll
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedllvm/lib/CodeGen/LiveDebugValues.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
The file was modifiedllvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
The file was modifiedllvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
The file was modifiedllvm/test/CodeGen/X86/call-site-info-output.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was modifiedllvm/include/llvm/Target/TargetOptions.h
The file was modifiedllvm/test/CodeGen/X86/hoist-invariant-load.ll
The file was removedllvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/DebugInfo/ARM/call-site-info-output.ll
The file was modifiedllvm/test/CodeGen/MIR/X86/call-site-info-error3.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/call-site-info-error1.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
The file was modifiedlldb/packages/Python/lldbsuite/test/decorators.py
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedllvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
Commit 5e52effca6289a438a2751db532d625097cc6af7 by Louis Dionne
[libc++] Add ABI list for 9.0 release

I just took a snapshot of the current ABI lists on master, since I don't
think they changed since the actual 9.0 release.
The file was addedlibcxx/lib/abi/9.0/x86_64-apple-darwin.v1.abilist
The file was addedlibcxx/lib/abi/9.0/x86_64-unknown-linux-gnu.v1.abilist
The file was addedlibcxx/lib/abi/9.0/x86_64-apple-darwin.v2.abilist
Commit 8fbc92580769dd42b4f00fd41200e0fa9de98405 by sander.desmalen
Add OffsetIsScalable to getMemOperandWithOffset

Summary:
Making `Scale` a `TypeSize` in AArch64InstrInfo::getMemOpInfo,
has the effect that all places where this information is used
(notably, TargetInstrInfo::getMemOperandWithOffset) will need
to consider Scale - and derived, Offset - possibly being scalable.

This patch adds a new operand `bool &OffsetIsScalable` to
TargetInstrInfo::getMemOperandWithOffset and fixes up all
the places where this function is used, to consider the
offset possibly being scalable.

In most cases, this means bailing out because the algorithm does not
(or cannot) support scalable offsets in places where it does some
form of alias checking for example.

Reviewers: rovka, efriedma, kristof.beyls

Reviewed By: efriedma

Subscribers: wuzish, kerbowa, MatzeB, arsenm, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, javed.absar, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72758
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/Lanai/LanaiInstrInfo.h
The file was modifiedllvm/lib/CodeGen/ModuloSchedule.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiInstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/lib/CodeGen/TargetInstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/ImplicitNullChecks.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/MachinePipeliner.cpp
Commit 4ca753f4e3ed194ada95f3911a58d70915ce2acd by weiwei64
[RISCV] Implement mayBeEmittedAsTailCall for tail call optimization

Implement TargetLowering callback mayBeEmittedAsTailCall for riscv in CodeGenPrepare,
which will duplicate return instructions to enable tailcall optimization.

Differential Revision: https://reviews.llvm.org/D73699
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/test/CodeGen/RISCV/tail-calls.ll
Commit 44bbc767000494c5702ca49c870e6642a93bbb02 by benny.kra
Drop a constexpr in favor of const, MSVC complains.

lib\Target\Hexagon\HexagonGenDFAPacketizer.inc(109): error C2131: expression did not evaluate to a constant
The file was modifiedllvm/utils/TableGen/DFAEmitter.cpp