SuccessChanges

Summary

  1. [lldb/Test] Remove un(used|needed|maintained) files from lldbsuite. (details)
  2. [lldb/Test] Python <3.5 requires **kwargs to come last (details)
  3. [mlir] [VectorOps] Use 'vector.flat_transpose' for 2-D 'vector.tranpose' (details)
  4. [clangd] Fix forgotten propagation of AsnycPreamble flag (details)
  5. [mlir][Linalg] Add support for fusion between indexed_generic ops and generic ops on tensors. (details)
  6. [mlir][Linalg] Add support for fusion between indexed_generic ops and tensor_reshape ops (details)
  7. Introduce a "gc-live" bundle for the gc arguments of a statepoint (details)
  8. [mlir][StandardToSPIRV] Handle i1 case for lowering std.zexti to SPIR-V. (details)
  9. [AArch64][GlobalISel] Select uzp1 and uzp2 (details)
  10. [Statepoint] Fix signed vs unsigned in index handling (details)
  11. Fix bug in newly added VersionBase::operator>= (details)
  12. [AArch64][GlobalISel] Add selection support for rev16, rev32, and rev64 (details)
  13. [WebAssembly] Fix ISel crash in SIGN_EXTEND_INREG lowering (details)
  14. [AArch64][NFC] Regenerate arm64-rev.ll (details)
  15. [Statepoints][CGP] Minor parameter type cleanup (details)
  16. Fix typo in filename comment. (details)
  17. Fix "Statistics are disabled" (details)
Commit 9caa34a24cb7d20a129143281cc0e1b2f44bd95c by Jonas Devlieghere
[lldb/Test] Remove un(used|needed|maintained) files from lldbsuite.
The file was removedlldb/packages/Python/lldbsuite/.clang-format
The file was removedlldb/packages/Python/lldbsuite/test/redo.py
The file was removedlldb/packages/Python/lldbsuite/test/lock.py
Commit 5fa9c9d7f276b44b3da949382e0d0b5dbfd0ac8b by Jonas Devlieghere
[lldb/Test] Python <3.5 requires **kwargs to come last

Thanks Martin Böhme for pointing this out.
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbtest.py
Commit 6391da98f43a995fe3dfb96a5376b2d9c652ed87 by ajcbik
[mlir] [VectorOps] Use 'vector.flat_transpose' for 2-D 'vector.tranpose'

Summary:
Progressive lowering of vector.transpose into an operation that
is closer to an intrinsic, and thus the hardware ISA. Currently
under the common vector transform testing flag, as we prepare
deploying this transformation in the LLVM lowering pipeline.

Reviewers: nicolasvasilache, reidtatge, andydavis1, ftynse

Reviewed By: nicolasvasilache, ftynse

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, jurahul, llvm-commits

Tags: #llvm, #mlir

Differential Revision: https://reviews.llvm.org/D80772
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Dialect/Vector/vector-contract-transforms.mlir
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.h
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was addedmlir/test/Dialect/Vector/vector-flat-transforms.mlir
Commit 49cbe56a657b91e612f8305e7f8f9119ffe84378 by kadircet
[clangd] Fix forgotten propagation of AsnycPreamble flag
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp
Commit cc11ceda165b5ba0a87e812fbd6ed1bce4fefd2f by hanchung
[mlir][Linalg] Add support for fusion between indexed_generic ops and generic ops on tensors.

Summary:
Different from the fusion between generic ops, indices are involved. In this
context, we need to re-map the indices for producer since the fused op is built
on consumer's perspective. This patch supports all combination of the fusion
between indexed_generic ops and generic ops, which includes tests case:
  1) generic op as producer and indexed_generic op as consumer.
  2) indexed_generic op as producer and generic op as consumer.
  3) indexed_generic op as producer and indexed_generic op as consumer.

Differential Revision: https://reviews.llvm.org/D80347
The file was modifiedmlir/test/Dialect/Linalg/fusion-tensor.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
Commit 27fca57546c2828e2684c02b7aa677cbd6603bfd by hanchung
[mlir][Linalg] Add support for fusion between indexed_generic ops and tensor_reshape ops

Summary:
The fusion for tensor_reshape is embedding the information to indexing maps,
thus the exising pattenr also works for indexed_generic ops.

Depends On D80347

Differential Revision: https://reviews.llvm.org/D80348
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/test/Dialect/Linalg/fusion-tensor.mlir
Commit 0e7c77053f560d391fecbec5d5e0e42082865c8a by listmail
Introduce a "gc-live" bundle for the gc arguments of a statepoint

Currently, gc.relocates are defined in terms of indices into the statepoint's operand list. Given the gc args are at the end of a variable length list of operands, this makes interpreting their indices by hand a tad challenging. We can simplify the statepoint sequence and improve readability quite a bit by pulling these new operands into their own named operand bundle.

This patch defines a new operand bundle tag "gc-live". The semantics of the bundle are the same as the existing gc arguments of a statepoint. This patch simply introduces the definition and codegen for the bundle, future patches will migrate RS4GC to emitting the new form.

Interestingly, with this done and the recent migration to using deopt and gc-transition bundles, we really don't have much left in the statepoint itself. It really looks like the existing ID and flags fields are redundant; we have (existing!) attributes for all of them. I think we'll be able to reduce the gc.statepoint signature to simply a wrapped call (e.g. actual target and actual arguments).

Differential Revision: https://reviews.llvm.org/D80937
The file was modifiedllvm/include/llvm/IR/Statepoint.h
The file was modifiedllvm/test/Bitcode/operand-bundles-bc-analyzer.ll
The file was addedllvm/test/CodeGen/X86/statepoint-gc-live.ll
The file was modifiedllvm/include/llvm/IR/LLVMContext.h
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/lib/IR/LLVMContext.cpp
The file was modifiedllvm/docs/Statepoints.rst
The file was modifiedllvm/docs/LangRef.rst
Commit 0b025d2733d02a8080f38d767cceab4812c5d6e2 by hanchung
[mlir][StandardToSPIRV] Handle i1 case for lowering std.zexti to SPIR-V.

Differential Revision: https://reviews.llvm.org/D80965
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
Commit 8dd34cce0716e0d83c2f05375e8352b5fb4c680c by Jessica Paquette
[AArch64][GlobalISel] Select uzp1 and uzp2

Porting the mask stuff for uzp1 and uzp2 from AArch64ISelLowering.

Add two custom opcodes: G_UZP1 and G_UZP2.

Produce them in the post-legalizer combiner when the mask checks out.

Tests:

- postlegalizer-combiner-uzp.mir verifies that we create G_UZP1 and G_UZP2.
The testcases that check that we create them come from neon-perm.ll.

- select-uzp.mir verifies that we can select G_UZP1 and G_UZP2.

Differential Revision: https://reviews.llvm.org/D81049
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-uzp.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/lib/Target/AArch64/AArch64PostLegalizerCombiner.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-uzp.mir
Commit ff529e0f2792e1383a602e4b8a466337fd0c2926 by listmail
[Statepoint] Fix signed vs unsigned in index handling

As noted in a comment on D80937, all of these are specified as unsigned values, but the verifier code was using signed.  Given the practical values involved, the different in range didn't matter, but we might as well clean it up.
The file was modifiedllvm/lib/IR/Verifier.cpp
Commit cab4b3b8e3a4a2822e459e5f103e49fcab16efaf by julian.lettner
Fix bug in newly added VersionBase::operator>=

Fixup for ba6b1b4353e33a7a36bcbad1d1c1157826197fd2.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mac.h
Commit 969d2d1ea9466143e7099040f5f0735cc81963b1 by Jessica Paquette
[AArch64][GlobalISel] Add selection support for rev16, rev32, and rev64

This does three things:

1) Adds G_REV16, G_REV32, and G_REV64. These are equivalent to AArch64rev16,
   AArch64rev32, and AArch64rev64 respectively.

2) Adds support for producing G_REV64 in the postlegalizer combiner.
   We don't legalize any of the shuffles which could give us a G_REV32 or
   G_REV16 yet. Since the function for detecting the rev mask is lifted from
   AArch64ISelLowering, it should work for G_REV32 and G_REV16 when we get
   there.

3) Adds a selection test for a good portion of the patterns imported for the rev
   family. The only ones which are not tested are the ones with bitconvert.

This also does a little cleanup, and adds a struct for shuffle vector pseudo
matchdata. This lets us still use `applyShuffleVectorPseudo` rather than adding
a new function.

It should also make it a bit easier to port some of the other masks from
AArch64ISelLowering. (e.g. `isZIP_v_undef_Mask` and friends)

Differential Revision: https://reviews.llvm.org/D81112
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-rev.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64PostLegalizerCombiner.cpp
Commit 25af2126f93a76f39c3121b3ddccdfd9f1aba4be by tlively
[WebAssembly] Fix ISel crash in SIGN_EXTEND_INREG lowering

Summary:
The code previously assumed that the index of a vector extract was
constant, but this was not always true. This patch fixes the problem
by bailing out of the lowering if the index is nonconstant and also
replaces `static_cast`s in the lowering function with `cast`s because
the latter contain type-checking asserts that would make similar
issues easier to find and debug.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81025
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was addedllvm/test/CodeGen/WebAssembly/simd-nonconst-sext.ll
Commit 06ae439110395e9d5cf9fdfbd9570130cc2f1a1e by Jessica Paquette
[AArch64][NFC] Regenerate arm64-rev.ll

Test had some GISel stuff in it which was changed by 969d2d1ea94.
The file was modifiedllvm/test/CodeGen/AArch64/arm64-rev.ll
Commit 382b3023cbbcffc07c7de73441d6b86f02486099 by listmail
[Statepoints][CGP] Minor parameter type cleanup
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
Commit 053fce9a02ad679f14f9dba33220f7d63fc11812 by echristo
Fix typo in filename comment.
The file was modifiedllvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
Commit 5477cf06d654e319ed066ba7f497e278853762be by Vitaly Buka
Fix "Statistics are disabled"

There is no -DLLVM_ENABLE_STATS, only
-DLLVM_FORCE_ENABLE_STATS.
It was renamed by 6cf299cf01e4a83844126f7faf17cbeb78e88da9
The file was modifiedllvm/lib/Support/Statistic.cpp