SuccessChanges

Summary

  1. [StackSafety,NFC] Add statistic counters (details)
  2. lld: add basic static library search (details)
  3. GlobalISel: Fail expansion of G_DYN_STACKALLOC for StackGrowsUp (details)
  4. AMDGPU/GlobalISel: Handle uniform G_DYN_STACKALLOC (details)
  5. AArch64/GlobalISel: Fix assert on call returning 0 sized type (details)
  6. consitfy and auto -> auto * a few places to clean up uses. (details)
  7. Make linter happy (details)
  8. [RegisterCoalescer] Update empty subranges when rematerializing (details)
  9. GlobalISel: Start defining strict FP instructions (details)
Commit 291dabefde01eae7473da224b49f6359766e0663 by Vitaly Buka
[StackSafety,NFC] Add statistic counters
The file was modifiedllvm/lib/Analysis/StackSafetyAnalysis.cpp
Commit 116e38fd8b89fb20279cbf7edb4a49a7ab5c7764 by Saleem Abdulrasool
lld: add basic static library search

This is a very basic static library search addition. This is the pre-Xcode4
behaviour of searching all paths for the shared version before searching for
the static version of the library. This behaviour is supposed to be inverted
with `-search_paths_first` being the default. This adds the library search
with the intention of providing the setup to merge the paths into one path
and making it controllable by `OPT_search_paths_first`.
The file was modifiedlld/MachO/Driver.cpp
The file was addedlld/test/MachO/static-link.s
Commit 3866e0a563ebfd622a0041d107f8d402097db0c1 by arsenm2
GlobalISel: Fail expansion of G_DYN_STACKALLOC for StackGrowsUp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit a1a93ca48ac80434ce8d490c9cb8efcf1412945d by arsenm2
AMDGPU/GlobalISel: Handle uniform G_DYN_STACKALLOC
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
Commit 9cdc27ffac48acfc458d4d6ae9db1f90757645a1 by arsenm2
AArch64/GlobalISel: Fix assert on call returning 0 sized type

I don't know why this is considered valid IR, but it probably should
not be.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64CallLowering.cpp
Commit 21a7b8a77dd47dd184e3f717a1c8e2f5591c803b by echristo
consitfy and auto -> auto * a few places to clean up uses.
The file was modifiedllvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
Commit eb9ca9da3e94e0c0d5eb8d98a388e92da0df9f12 by julian.lettner
Make linter happy

Fixup for ba6b1b4353e33a7a36bcbad1d1c1157826197fd2.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mac.cpp
Commit ccb3c8e8613413846d6c2f17cc1c1e2a8b6a98ef by qcolombet
[RegisterCoalescer] Update empty subranges when rematerializing

When we rematerialize a value as part of the coalescing, we may
widen the register class of the destination register.
When this happens, updateRegDefUses may create additional subranges
to account for the wider register class.
The created subranges are empty and if they are not defined by
the rematerialized instruction we clean them up.
However, if they are defined by the rematerialized instruction but
unused, we failed to flag them as dead definition and would leave
them as empty live-range.
This is wrong because empty live-ranges don't interfere with anything,
thus if we don't fix them, we would fail to account that the
rematerialized instruction clobbers some lanes.

E.g., let us consider the following pseudo code:
def.lane_low64:reg128 = ldimm
newdef:reg32 = COPY def.lane_low64_low32

When rematerialization happens for newdef, we end up with:
newdef.lane_low64:reg128 = ldimm
= use newdef.lane_low64_low32

Let's look at the live interval of newdef.
Before rematerialization, we would get:
newdef [defIdx, useIdx:0) 0@defIdx

Right after updateRegDefUses, newdef register class is widen to reg128
and the subrange definitions will be augmented to fill the subreg that
is used at the definition point, here lane_low64.
The resulting live interval would be:
newdef [newDefIdx, useIdx:0) 0@newDefIdx
* lane_low64_high32 EMPTY
* lane_low64_low32 [newDefIdx, useIdx:0)

Before this patch this would be the final status of the live interval.
Therefore we miss that lane_low64_high32 is actually live on the
definition point of newdef.

With this patch, after rematerializing, we check all the added subranges
and for the ones that are defined but empty, we flag them as dead def.
Thus, in that case, newdef would look like this:
newdef [newDefIdx, useIdx:0) 0@newDefIdx
* lane_low64_high32 [newDefIdx, newDefIdxDead) ; <-- instead of EMPTY
* lane_low64_low32 [newDefIdx, useIdx:0)

This fixes https://www.llvm.org/PR46154
The file was modifiedllvm/lib/CodeGen/RegisterCoalescer.cpp
The file was addedllvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
Commit ed5017e153c76adc13badcfd123c68dd074e75d1 by arsenm2
GlobalISel: Start defining strict FP instructions

The AMDGPU lowering for unconstrained G_FDIV sometimes needs to
introduce a mode switch in the middle, so it's helpful to have
constrained instructions available to legalize this. Right now nothing
is preventing reordering of the mode switch with the other
instructions in the expansion.
The file was modifiedllvm/include/llvm/Target/GenericOpcodes.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
The file was modifiedllvm/include/llvm/Support/TargetOpcodes.def
The file was modifiedllvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll