SuccessChanges

Summary

  1. Revert "Temporarily disable email notification for test-suite pipeline jobs" (details)
Commit 334aee1e5a0e7690f7490a2619c94d3a15c0b181 by Azharuddin Mohammed
Revert "Temporarily disable email notification for test-suite pipeline jobs"

This reverts commit 17e1c3a1e4acbebc29a0a913b1a80d7fc387e749.
The file was modifiedzorg/jenkins/common.groovy (diff)

Summary

  1. Fix typo: s/epomymous/eponymous/ NFC (details)
  2. Allow .dSYM's to be directly placed in an alternate directory (details)
  3. [CodeGen][ObjC] Mark calls to objc_unsafeClaimAutoreleasedReturnValue as (details)
  4. [MC] Set sh_link to 0 if the associated symbol is undefined (details)
  5. [ARM] Test for converting VPSEL to VMOVT. NFC (details)
  6. Revert "[X86][SSE] Shuffle combine blends to OR(X,Y) if the relevant elements are known zero." (details)
  7. [WebAssembly] Implement prototype v128.load{32,64}_zero instructions (details)
  8. [ARM] Convert VPSEL to VMOV in tail predicated loops (details)
  9. [HWASan] [GlobalISel] Add +tagged-globals backend feature for GlobalISel (details)
Commit 7f1556f292ccfd80c4ffa986d5b849f915e5cd82 by jonathan_roelofs
Fix typo: s/epomymous/eponymous/ NFC
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
Commit 7209f83112db4dbe15d8328705f9d2aff0624fbd by daniel_l_sanders
Allow .dSYM's to be directly placed in an alternate directory

Once available in the relevant toolchains this will allow us to implement
LLVM_EXTERNALIZE_DEBUGINFO_OUTPUT_DIR after D84127 by directly placing the dSYM
in the desired location instead of emitting next to the output file and moving
it.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D84572
The file was modifiedclang/test/Driver/darwin-dsymutil.c
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Driver/Driver.cpp
Commit 41b1e97b12c1407e40d8e5081bf1f9cf183934b0 by Akira
[CodeGen][ObjC] Mark calls to objc_unsafeClaimAutoreleasedReturnValue as
notail on x86-64

This is needed because the epilogue code inserted before tail calls on
x86-64 breaks the handshake between the caller and callee.

Calls to objc_retainAutoreleasedReturnValue used to have the same
problem, which was fixed in https://reviews.llvm.org/D59656.

rdar://problem/66029552

Differential Revision: https://reviews.llvm.org/D84540
The file was modifiedclang/lib/CodeGen/CGObjC.cpp
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedclang/test/CodeGenObjC/arc-unsafeclaim.m
The file was modifiedclang/lib/CodeGen/TargetInfo.h
Commit 11bb7c220ccdff1ffec4780ff92fb5acec8f6f0b by i
[MC] Set sh_link to 0 if the associated symbol is undefined

Part of https://bugs.llvm.org/show_bug.cgi?id=41734

LTO can drop externally available definitions. Such AssociatedSymbol is
not associated with a symbol. ELFWriter::writeSection() will assert.

Allow a SHF_LINK_ORDER section to have sh_link=0.

We need to give sh_link a syntax, a literal zero in the linked-to symbol
position, e.g. `.section name,"ao",@progbits,0`

Reviewed By: pcc

Differential Revision: https://reviews.llvm.org/D72899
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/lib/MC/MCSectionELF.cpp
The file was modifiedllvm/test/CodeGen/X86/elf-associated.ll
The file was modifiedllvm/lib/MC/MCParser/ELFAsmParser.cpp
The file was addedllvm/test/MC/ELF/section-linkorder.s
The file was addedllvm/test/CodeGen/X86/elf-associated-discarded.ll
The file was modifiedllvm/lib/MC/ELFObjectWriter.cpp
Commit 21de4e74acf603f02f886a9e6030945f077bca3f by david.green
[ARM] Test for converting VPSEL to VMOVT. NFC
The file was addedllvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
Commit 66e7dce714fabd3ddb1aed635e4b826476d4f1a2 by 31459023+hctim
Revert "[X86][SSE] Shuffle combine blends to OR(X,Y) if the relevant elements are known zero."

This reverts commit 219f32f4b68679563443cdaae7b8174c9976409a.

Commit contains unsigned compasions that break bots that build with
-Wsign-compare.
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
The file was modifiedllvm/test/CodeGen/X86/insertelement-ones.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
Commit cb327922101b28ea70ec68d7f026da0e5e388eed by tlively
[WebAssembly] Implement prototype v128.load{32,64}_zero instructions

Specified in https://github.com/WebAssembly/simd/pull/237, these
instructions load the first vector lane from memory and zero the other
lanes. Since these instructions are not officially part of the SIMD
proposal, they are only available on an opt-in basis via LLVM
intrinsics and clang builtin functions. If these instructions are
merged to the proposal, this implementation will change so that the
instructions will be generated from normal IR. At that point the
intrinsics and builtin functions would be removed.

This PR also changes the opcodes for the experimental f32x4.qfm{a,s}
instructions because their opcodes conflicted with those of the
v128.load{32,64}_zero instructions. The new opcodes were chosen to
match those used in V8.

Differential Revision: https://reviews.llvm.org/D84820
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was addedllvm/test/CodeGen/WebAssembly/simd-load-zero-offset.ll
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
The file was modifiedllvm/test/MC/WebAssembly/simd-encodings.s
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
Commit 22916481c11e1d46132752086290a668e62fc9ce by david.green
[ARM] Convert VPSEL to VMOV in tail predicated loops

VPSEL has slightly different semantics under tail predication (it can
end up selecting from Qn, Qm and Qd). We do not model that at the moment
so they block tail predicated loops from being formed.

This just converts them into a predicated VMOV instead (via a VORR),
allowing tail predication to happen whilst still modelling the original
behaviour of the input.

Differential Revision: https://reviews.llvm.org/D85110
The file was modifiedllvm/lib/Target/ARM/MVEVPTOptimisationsPass.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-selectop3.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vctp.ll
Commit 9a05fa10bd05525adedb6117351333699a3d4ae2 by 31459023+hctim
[HWASan] [GlobalISel] Add +tagged-globals backend feature for GlobalISel

GlobalISel is the default ISel for aarch64 at -O0. Prior to D78465, GlobalISel
didn't have support for dealing with address-of-global lowerings, so it fell
back to SelectionDAGISel.

HWASan Globals require special handling, as they contain the pointer tag in the
top 16-bits, and are thus outside the code model. We need to generate a `movk`
in the instruction sequence with a G3 relocation to ensure the bits are
relocated properly. This is implemented in SelectionDAGISel, this patch does
the same for GlobalISel.

GlobalISel and SelectionDAGISel differ in their lowering sequence, so there are
differences in the final instruction sequence, explained in
`tagged-globals.ll`. Both of these implementations are correct, but GlobalISel
is slightly larger code size / slightly slower (by a couple of arithmetic
instructions). I don't see this as a problem for now as GlobalISel is only on
by default at `-O0`.

Reviewed By: aemerson, arsenm

Differential Revision: https://reviews.llvm.org/D82615
The file was modifiedllvm/test/CodeGen/AArch64/tagged-globals.ll
The file was addedcompiler-rt/test/hwasan/TestCases/exported-tagged-global.c
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp