SuccessChanges

Summary

  1. [DAGCombine] Remove the check for unsafe-fp-math when we are checking the AFN (details)
  2. [RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags. (details)
  3. [LoopUnroll] Fix a crash (details)
  4. [PowerPC] Add variants of 64-bit vector types for vec_sel. (details)
  5. [IR Parser] Fix a crash handling zero width integer attributes. (details)
  6. CGDebugInfo: Delete redundant test (details)
  7. CGDebugInfo: Delete unneeded UnwrapTypeForDebugInfo (details)
  8. [MLIR][SPIRV] Add (de-)serialization support for SpecConstantOpeation. (details)
  9. [NFC][AsmPrinter] Make comments for spill/reload more precise. (details)
  10. [JITLink] Rename PostAllocationPasses to PreFixupPasses. (details)
  11. [RISCV] Clear isCodeGenOnly flag on VMSGE(U) pseudo instructions. Remove InstAliases that duplicate the asm strings in the pseudos. (details)
  12. Remove redundant casts. (details)
  13. [CSKY] Add visibility macro to fix link error (details)
  14. [clang-format] Skip UTF8 Byte Order Mark while sorting includes (details)
  15. [ARM] Additional trunc cost tests. NFC (details)
  16. [clang-format] turn on formatting after "clang-format on" while sorting includes (details)
  17. [clang-format] Find main include after block ended with #pragma hdrstop (details)
  18. [ARM] Update trunc costs (details)
  19. [NFC] Remove min/max functions from InstructionCost (details)
  20. Reapply "[clang][cli] Port DiagnosticOpts to new option parsing system" (details)
  21. [NFC][InstructionCost] Change LoopVectorizationCostModel::getInstructionCost to return InstructionCost (details)
  22. [ARM] Add debug messages for the load store optimizer. NFC (details)
  23. [clangd] Add metrics for go-to-implementation. (details)
  24. [X86] Fix tile register spill issue. (details)
  25. Require chained analyses in BasicAA and AAResults to be transitive (details)
  26. [SVE][CodeGen] Fix legalisation of floating-point masked gathers (details)
  27. Revert rGd43a264a5dd3 "Revert "[X86][SSE] Fold unpack(hop(),hop()) -> permute(hop())"" (details)
  28. [X86][SSE] Add missing SSE test coverage for permute(hop,hop) folds (details)
  29. [VE] Support intrinsic to isnert/extract_subreg of v512i1 (details)
  30. [VE] Support additional VMRGW and VMV intrinsic instructions (details)
  31. [obj2yaml] - Fix the crash in getUniquedSectionName(). (details)
  32. [clang][AArch64][SVE] Avoid going through memory for coerced VLST return values (details)
  33. [llvm-readelf/obj] - Index phdrs and relocations from 0 when reporting warnings. (details)
  34. [VPlan] Move initial quote emission from ::print to ::dumpBasicBlock. (details)
  35. [obj2yaml][test] - Improve and fix section-group.yaml test. (details)
  36. [lldb] Disable PipeTest.OpenAsReader on windows (details)
  37. [X86][SSE] Add 'vectorized sum' test patterns (details)
  38. [ARM] Add uses for locals introduced for debug messages. NFC. (details)
  39. [AMDGPU] Fix a urem combine test to test what it was supposed to (details)
  40. [mlir] Remove unnecessary llvm.mlir.cast in AsyncToLLVM lowering. (details)
  41. [mlir] Make GpuAsyncRegion pass depend on async dialect. (details)
  42. [flang][driver] Copy input files into a temp dir when testing (details)
  43. [mlir][linalg] Support parsing attributes in named op spec (details)
  44. [mlir][linalg] Support permutation when lowering to loop nests (details)
  45. [DAGCombiner] Use getVectorElementCount inside visitINSERT_SUBVECTOR (details)
  46. [attributes]  Add a facility for enforcing a Trusted Computing Base. (details)
  47. [VPlan] Unify value/recipe printing after VPDef transition. (details)
  48. Revert "[attributes]  Add a facility for enforcing a Trusted Computing Base." (details)
  49. [mlir] Fix gpu-to-llvm lowering for gpu.alloc with dynamic sizes. (details)
  50. [X86] Add nounwind to lzcnt-cmp tests (details)
  51. [X86] Extend lzcnt-cmp tests to test on non-lzcnt targets (details)
  52. [ARM] Update existing test case with +pauth targets (details)
  53. [clangd] Fix -check mode doesn't respect any tidy configs. (details)
  54. [OpenMPOpt][WIP] Expand parallel region merging (details)
  55. [clangd] Remove ScratchFS from tests (details)
  56. NFC: Use -LABEL more (details)
  57. [FastISel] Flush local value map on every instruction (details)
  58. [X86][AVX] Attempt to fold vpermf128(op(x,i),op(y,i)) -> op(vpermf128(x,y),i) (details)
  59. [mlir][Linalg] Fold init_tensor -> linalg.tensor_reshape. (details)
  60. [Clang][Docs] Fix ambiguity in clang-offload-bundler docs (details)
  61. [NFC] Disallow unused prefixes in CodeGen/PowerPC tests. (details)
  62. [mlir][vector] Add memory effects to transfer_read transfer_write ops (details)
  63. [mlir][Linalg] Fix reshape fusion to reshape the outs instead of creating new tensors. (details)
  64. [FastISel] NFC: Remove obsolete -fast-isel-sink-local-values option (details)
  65. [ELF] --exclude-libs: localize defined libcall symbols referenced by lto.tmp (details)
  66. [SystemZ]  Minor NFC fix in SchedModels. (details)
  67. [FastISel] NFC: Clean up unnecessary bookkeeping (details)
  68. [X86] Regenerate vector-constrained-fp-intrinsics.ll tests (details)
  69. [attributes]  Add a facility for enforcing a Trusted Computing Base. (details)
  70. [Hexagon] Custom-widen SETCC's operands (details)
  71. [AMDGPU] Deduplicate VOP tablegen asm & ins (details)
  72. [mlir] Add Python bindings for AffineExpr (details)
  73. [mlir] More Python bindings for AffineMap (details)
  74. [mlir] Expose MemRef layout in Python bindings (details)
  75. [flang][openxx][NFC] Remove duplicated function to check required clauses (details)
  76. -funique-internal-linkage-names appends a hex md5hash suffix to the symbol name which is not demangler friendly, convert it to decimal. (details)
  77. Introduce new quiet mode and new option handling for -print-changed. (details)
  78. Fix minor build issue (NFC) (details)
  79. [SystemZ][z/OS] Fix Permission denied pattern matching (details)
  80. [mlir] Add structural conversion to async dialect lowering. (details)
  81. [RISCV] Add scalable vector fcmp ISel patterns (details)
  82. [libc++] Turn off auto-formatting of generated files. NFC. (details)
  83. [NFC][AMDGPU] Clarify memory model support for volatile (details)
  84. [mlir][ODS] Add a C++ abstraction for OpBuilders (details)
  85. [mlir][TypeDefGen] Add support for adding builders when generating a TypeDef (details)
  86. [mlir][IR][NFC] Move the definitions of Complex/Function/Integer/Opaque/TupleType to ODS (details)
  87. [ADT] Add makeIntrusiveRefCnt helper function (details)
  88. [tools] Mark output of tools as text if it is really text (details)
  89. [NFC] Disallow unused prefixes under llvm/test/CodeGen (details)
  90. [mlir][vector] Add side-effect information to different load/store ops (details)
  91. Enable python bindings for tensor, shape and linalg dialects. (details)
  92. [mlir][CAPI] Introduce standard source layout for mlir-c dialect registration. (details)
  93. Revert "[mlir][linalg] Support parsing attributes in named op spec" (details)
  94. [InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test (details)
  95. [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT (details)
  96. [libc][NFC] Make __support/common.h an in tree header. (details)
  97. [c++20] Don't consider string literal operator templates for numeric (details)
  98. Add an assert to CGDebugInfo::getTypeOrNull (details)
  99. [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns (details)
  100. [mlir][vector] verify memref of vector memory ops (details)
  101. [PredicateInfo] Add test for one unknown condition in and/or (NFC) (details)
  102. [SCCP] Fix misclassified conditions in test (NFC) (details)
  103. CGDebugInfo: Delete unused parameters (details)
  104. Rename debug linkage name with -funique-internal-linkage-names (details)
  105. [OpenMP] Take elf_common.c as a interface library (details)
  106. [RISCV] Add scalable vector vselect ISel patterns (details)
  107. clang: Always pass PowerPC endian information to GNU as (details)
  108. Update syntax for tensor and memref types to match parser. (details)
  109. [RISCV] Use vmv.v.i vd, 0 instead of vmv.v.x vd, x0 for llvm.riscv.vfmv.v.f with 0.0 (details)
  110. [SimplifyCFG] SwitchToLookupTable(): don't insert a DomTree edge that already exists (details)
  111. [SimplifyCFG] SimplifyBranchOnICmpChain(): don't insert a DomTree edge that already exists (details)
  112. [SimplifyCFG] FoldValueComparisonIntoPredecessors(): don't insert a DomTree edge if it already exists (details)
  113. [NFCI][Utils/Local] removeUnreachableBlocks(): cleanup support for lazy DomTreeUpdater (details)
  114. [SimplifyCFGPass] mergeEmptyReturnBlocks(): skip blocks scheduled for removal as per DomTreeUpdater (details)
  115. [SimplifyCFGPass] iterativelySimplifyCFG(): support lazy DomTreeUpdater (details)
  116. ADT: Fix pointer comparison UB in SmallVector (details)
  117. [RISCV] Define the vfclass RVV intrinsics (details)
  118. NFC: Pre-commit test: -Wpointer-sign with plain char to [un]signed char (details)
  119. [clang] Fix message text for `-Wpointer-sign` to account for plain char (details)
  120. [github] Move repo lockdown config into llvm-project repo (details)
  121. [MLIR][Linalg] Refactor transforms to use linalg::getDynOperands helper (details)
  122. [MC] Make getEHFrameSection const like every other getter (NFC) (details)
  123. [JITLink] Add a new PostAllocationPasses list. (details)
  124. [VE][compiler-rt] Add VE as a target of crt (details)
  125. [WebAssembly] Ensure terminate pads are a single BB (details)
  126. [NFC][LICM] Minor improvements to debug output (details)
  127. [OpenMP] Move memory manager to plugin and make it a common interface (details)
  128. [llvm] Use llvm::find_if (NFC) (details)
  129. [llvm] Use *Set::contains (NFC) (details)
  130. [llvm] Simplify string comparisons (NFC) (details)
  131. [CodeGen] Try to make the print of memory operand alignment a little more user friendly. (details)
  132. Add unconditional logging to debugserver for launch/attach processes (details)
  133. [SelectionDAG] Make isConstantIntBuildVectorOrConstantInt and isConstantFPBuildVectorOrConstantFP methods const. (details)
  134. [CMake] Split the target side of runtimes build (details)
  135. [DAGCombiner] Replace static helper function isConstantFPBuildVectorOrConstantFP with the identical version in SelectionDAG. NFC (details)
  136. [ELF] Drop .rel[a].debug_gnu_pub{names,types} for --gdb-index --emit-relocs (details)
  137. [WebAssembly] Misc. refactoring in CFGStackify (NFC) (details)
  138. Adapt CastExpr::getSubExprAsWritten to ConstantExpr (details)
  139. [LiveDebugValues] Fix comparison operator in VarLocBasedImpl (details)
  140. [AMDGPU] Fix failing assert with scratch ST mode (details)
  141. [clang][cli] Remove -f[no-]trapping-math from -cc1 command line (details)
  142. [mlir] use built-in vector types instead of LLVM dialect types when possible (details)
  143. [Test] Add failing test for PR48725 (details)
  144. [WebAssembly] Remove more unnecessary brs in CFGStackify (details)
  145. [llvm-readef/obj] - Change the design structure of ELF dumper. NFCI. (details)
  146. [llvm-readobj] - Add 'override' to fix build bots. (details)
  147. [llvm-readobj] - An attempt to fix BB. (details)
  148. [mlir][openmp][NFCI] Rename `continuationIP` to `continuationBlock` (details)
  149. [llvm-readobj] - One more attempt to fix BB. (details)
  150. [clang][AST] Get rid of an alignment hack in DeclObjC.h [NFCI] (details)
  151. [SlotIndexes] Fix and simplify basic block splitting (details)
  152. [AMDGPU][GlobalISel] Remove some duplicate RUN lines (details)
  153. [obj2yaml,yaml2obj] - Fix issues with creating/dumping group sections. (details)
  154. [obj2yaml] - Don't crash when an object has an empty symbol table. (details)
  155. Revert "[Test] Add failing test for PR48725" (details)
  156. Change the LLVM_ATTRIBUTE_DEPRECATED macro to use C++14 attribute. (details)
  157. [RISCV] Improve scalable-vector shift tests (NFC) (details)
  158. [X86][SSE] combineSubToSubus - remove SSE2 early-out. (details)
  159. [Fixed Point] Add codegen for conversion between fixed-point and floating point. (details)
  160. [X86][SSE] combineSubToSubus - add v16i32 handling on pre-AVX512BW targets. (details)
  161. [X86][SSE] getFauxShuffleMask - handle PACKSS(SRAI(),SRAI()) shuffle patterns. (details)
  162. [mlir][Linalg] NFC - Refactor fusion APIs (details)
  163. [TableGen] Improve error message for semicolon after braced body. (details)
  164. [mlir][openacc] Use TableGen information for default enum (details)
  165. [X86] Improved lowering for saturating float to int. (details)
  166. [VE] Update VELIntrinsic tests (details)
  167. [mlir][spirv] NFC: place ops in the proper file for their categories (details)
  168. [SLP] Add test case showing a bug when dealing with padded types (details)
  169. [PowerPC] Add support for embedded devices with EFPU2 (details)
  170. Reland "[mlir][linalg] Support parsing attributes in named op spec" (details)
  171. [mlir][CAPI] Fix inline function declaration (details)
  172. [mlir] Fix for LIT tests (details)
  173. [libc++] [C++2b] [P1048] Add is_scoped_enum and is_scoped_enum_v. (details)
  174. [mlir][spirv] NFC: split deserialization into multiple source files (details)
  175. [PowerPC][NFCI] PassSubtarget to ASMWriter (details)
  176. [MLIR] Disallow `sym_visibility`, `sym_name` and `type` attributes in the parsed attribute dictionary. (details)
  177. [X86] Regenerate sdiv_fix_sat.ll + udiv_fix_sat.ll tests (details)
  178. Fix typo in diagnostic message (details)
  179. [AMDGPU] Regenerate umax crash test (details)
  180. [SVE][NFC] Regenerate a few CodeGen tests (details)
  181. Add -ansi option to CompileOnly group (details)
  182. [doc] Place sha256 in lld/README.md into backticks (details)
  183. Return false from __has_declspec_attribute() if not explicitly enabled (details)
  184. [llvm] [cmake] Remove obsolete /usr/local hack for *BSD (details)
  185. [Tests] Add tests for new InstCombine OR transformation, NFC (details)
  186. [instCombine] Add (A ^ B) | ~(A | B) -> ~(A & B) (details)
  187. [Flang][openmp][openacc] Extend CheckNoBranching to handle branching provided by LabelEnforce. (details)
  188. [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO. (details)
  189. [clangd] Avoid recursion in TargetFinder::add() (details)
  190. [NewPM] Run non-trivial loop unswitching under -O2/3/s/z (details)
  191. [RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 scalar operand. (details)
  192. [FunctionAttrs] Precommit tests for willreturn inference. (details)
  193. [libc++] Add a missing `<_Compare>` template argument. (details)
  194. [libcxx] Port to OpenBSD (details)
  195. [InstSimplify] Don't fold gep p, -p to null (details)
  196. [OpenMP] Fixed include directories for OpenMP when building OpenMP with LLVM_ENABLE_RUNTIMES (details)
  197. [libomptarget][amdgpu][nfc] Fix build on centos (details)
  198. [clang][aarch64] Precondition isHomogeneousAggregate on isCXX14Aggregate (details)
  199. [FunctionAttrs] Derive willreturn for fns with readonly` & `mustprogress`. (details)
  200. [IR] move nomerge attribute from function declaration/definition to callsites (details)
  201. [clang-tidy] Add test for Transformer-based checks with diagnostics. (details)
  202. [InstCombine] Regenerate test checks (NFC) (details)
  203. [LV] Relax assumption that LCSSA implies single entry (details)
  204. Fix for crash in __builtin_return_address in template context. (details)
  205. [InstCombine] Duplicate tests for logical and/or (NFC) (details)
  206. [LV] Weaken spuriously strong assert in LoopVersioning (details)
  207. [SLP] reduce code duplication while matching reductions; NFC (details)
  208. [SLP] reduce code duplication in processing reductions; NFC (details)
  209. [SLP] rename variable to improve readability; NFC (details)
  210. [SLP] reduce code duplication while processing reductions; NFC (details)
  211. [RISCV] Add double test cases to vfmerge-rv32.ll. NFC (details)
  212. [InstCombine] Add tests for logical and/or poison implication (NFC) (details)
  213. [RISCV] Legalize select when Zbt extension available (details)
  214. [InstCombine] Handle logical and/or in assume optimization (details)
  215. [mlir] Update LLVM dialect type documentation (details)
  216. [Inliner] Change inline remark format and update ReplayInlineAdvisor to use it (details)
  217. [OpenMP] Fixed the link error that cannot find static data member (details)
  218. [AArch64] [Windows] Properly add :lo12: reloc specifiers when generating assembly (details)
  219. [libcxx] Avoid overflows in the windows __libcpp_steady_clock_now() (details)
  220. [OpenMP] Fixed a typo in openmp/CMakeLists.txt (details)
  221. AMDGPU: Remove wrapper only call limitation (details)
  222. [Driver] Fix assertion failure when -fprofile-generate -fcs-profile-generate are used together (details)
  223. [NFC] Disallow unused prefixes in MC/AMDGPU (details)
  224. [ADT][NFC] Use empty base optimisation in BumpPtrAllocatorImpl (details)
  225. [RISCV] Remove '.mask' from vcompress intrinsic name. NFC (details)
  226. [ELF][NFCI] small cleanup to OutputSections.h (details)
  227. Add sample-profile-suffix-elision-policy attribute with -funique-internal-linkage-names. (details)
  228. [MIPatternMatch] Add matcher for G_PTR_ADD (details)
  229. [Sanitizer][Darwin] Fix test for macOS 11+ point releases (details)
  230. [NFC] Disallow unused prefixes under MC/AMDGPU (details)
  231. Delete unused function (was breaking the -Werror build) (details)
  232. [AMDGPU] Add _e64 suffix to VOP3 Insts (details)
  233. [libc] add isascii and toascii implementations (details)
  234. [libc][NFC] Use more specific comparison macros in LdExpTest.h. (details)
  235. [LangRef] State that a nocapture pointer cannot be returned (details)
  236. [DAGCombiner] Fold BRCOND(FREEZE(COND)) to BRCOND(COND) (details)
  237. [MSan] Tweak CopyOrigin (details)
  238. [gn build] (manually) port 79f99ba65d96 (details)
  239. [mlir][Python] Add checking process before create an AffineMap from a permutation. (details)
  240. [X86][AMX] Prohibit pointer cast on load. (details)
  241. [Coroutine] Update promise object's final layout index (details)
  242. [PDB] Defer relocating .debug$S until commit time and parallelize it (details)
  243. [OpenMP] Update allocator trait key/value definitions (details)
  244. [gn build] Reorganize libcxx/include/BUILD.gn a bit (details)
  245. [libc++] Give extern templates default visibility on gcc (details)
  246. [OpenMP] Use persistent memory for omp_large_cap_mem (details)
  247. [NFC] Use generic name for scalable vector stack ID. (details)
  248. [dsymutil] Warn on timestmap mismatch between object file and debug map (details)
  249. [Orc] Add a unit test for asynchronous definition generation. (details)
  250. [InlineSpiller] Re-tie operands if folding failed (details)
  251. [dsymutil] Copy eh_frame content into the dSYM companion file. (details)
  252. [libomptarget][nvptx] Include omp_data.cu in bitcode deviceRTL (details)
  253. [dsymutil] s/dwarfdump/llvm-dwarfdump/ in test (details)
  254. [dsymutil] Fix spurious space in REQUIRES: line (details)
  255. [AMDGPU] Add SI_EARLY_TERMINATE_SCC0 for early terminating shader (details)
  256. [Statepoint Lowering] Add an option to allow use gc values in regs for landing pad (details)
  257. [Verifier] Extend statepoint verifier to cover more constants (details)
  258. [llvm] Remove redundant string initialization (NFC) (details)
  259. [CodeGen] Remove unused function isRegLiveInExitBlocks (NFC) (details)
  260. [llvm] Use Optional::getValueOr (NFC) (details)
  261. [dsymutil] Add preliminary support for DWARF 5. (details)
  262. [MSan] Partially revert some changes from D94552 (details)
  263. [Verifier] Add tied-ness verification to statepoint intsruction (details)
  264. [ARM] Additional tests for different interleaving patterns. NFC (details)
  265. [llvm-readelf/obj] - Add support of multiple SHT_SYMTAB_SHNDX sections. (details)
  266. [ARM] Update isVMOVNOriginalMask to handle single input shuffle vectors (details)
  267. [obj2yaml,yaml2obj] - Refine how we set/dump the sh_entsize field. (details)
  268. [clang][driver] Restore the original help text for `-I` (details)
  269. [LTO] Replace anonymous namespace with static functions (NFC). (details)
  270. [NFC][InstructionCost] Use InstructionCost in Transforms/Scalar/RewriteStatepointsForGC.cpp (details)
  271. [AArch64][SVE] Remove chains of unnecessary SVE reinterpret intrinsics (details)
  272. [X86][AVX] combineVectorSignBitsTruncation - limit AVX512 truncations to 128-bits (PR48727) (details)
  273. [SVE] Add ISel pattern for addvl (details)
  274. Hwasan InitPrctl check for error using internal_iserror (details)
  275. [ADT] Fix join_impl using the wrong size when calculating total length (details)
  276. [LTO] Add test to ensure objc-arc-contract is executed. (details)
  277. Fix build errors after ceb9379a9 (details)
  278. Revert "[dsymutil] Warn on timestmap mismatch between object file and debug map" (details)
  279. [SVE][CodeGen] CTLZ, CTTZ & CTPOP operations (predicates) (details)
  280. [ValueTracking] Fix one s/dyn_cast/dyn_cast_or_null/ (details)
  281. Revert "Hwasan InitPrctl check for error using internal_iserror" (details)
  282. [Tests] Added test for memcpy loop idiom recognization (details)
  283. [X86] canonicalizeShuffleMaskWithHorizOp - minor refactor to support multiple src ops. NFCI. (details)
  284. [libc] Refresh benchmark progress bar when needed. (details)
  285. [OpenCL] Improve OpenCL operator tests (details)
  286. [X86] Add tests for rv_marker lowering. (details)
  287. [mlir][linalg] Use attributes in named ops' indexing maps (details)
  288. [clangd] Split out a base class for delegating GlobalCompilationDatabases. NFC (details)
  289. [AArch64] Attempt to sink mul operands (details)
  290. GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper (details)
  291. [NFC][RISCV] Add double type in RISC-V V CodeGen test cases for RV32. (details)
  292. [AArch64][GlobalISel] Add support for FCONSTANT of FP128 type (details)
  293. [lld][WebAssembly] Fix for TLS + --relocatable (details)
  294. [Frontend] Add pragma align natural and sort out pragma pack stack effect (details)
  295. [OpenMP] Add documentation for error messages and release notes (details)
  296. [OpenMP] Fix hierarchical barrier (details)
  297. [clangd] Explicitly avoid background-indexing the same file twice. (details)
  298. [clangd] Avoid reallocating buffers for each message read: (details)
  299. [SLP] add reduction test for FMF; NFC (details)
  300. [InstCombine] Fold select -> and/or using impliesPoison (details)
  301. [clangd] Remove "decision-forest-base" experimental flag. (details)
  302. [clangd] Remove some old CodeCompletion options that are never (un)set.  NFC (details)
  303. [IROutliner] Adapting to hoisted bitcasts in CodeExtractor (details)
  304. [dsymutil] Warn on timestmap mismatch between object file and debug map (details)
  305. [X86][SSE] canonicalizeShuffleMaskWithHorizOp - simplify shuffle(HOP(HOP(X,Y),HOP(Z,W))) style chains. (details)
  306. [X86][AVX] Add test for another 'reverse HADD' pattern mentioned in PR41813 (details)
  307. [DAG] visitVECTOR_SHUFFLE - use all_of to check for all-undef shuffle mask. NFCI. (details)
  308. [ARM] Add a pass that re-arranges blocks when there is a backwards WLS branch (details)
  309. [gn build] Port 60fda8ebb6d (details)
  310. [flang] Fix classification of shape inquiries in specification exprs (details)
  311. [Hexagon] Improve legalizing of ISD::SETCC result (details)
  312. [SLP] simplify type check for reductions (details)
  313. [flang] Do not create HostAssoc symbols in derived type scopes (details)
  314. [CSSPGO][llvm-profgen] Pseudo probe decoding and disassembling (details)
  315. [CSSPGO][llvm-profgen] Refactor to unify hashable interface for trace sample and context-sensitive counter (details)
  316. [CSSPGO][llvm-profgen] Virtual unwinding with pseudo probe (details)
  317. [NFC] fix missing SectionName declaration (details)
  318. [mlir] Correct 2 places that result in corrupted conversion rollbacks (details)
  319. [LLD][COFF] Avoid std::vector resizes during type merging (details)
  320. [NFC] Use correct ssa.copy spelling when referring to the intrinsic (details)
  321. [mlir][sparse] add vectorization strategies to sparse compiler (details)
  322. [LTO] Add test for freestanding LTO option. (details)
  323. [flang] Fix accessibility of USEd name in .mod file (details)
  324. [libc][NFC] add macro for fuchsia to switch test backend to zxtest (details)
  325. Fix the warnings on unused variables (NFC) (details)
  326. [FuncAttrs] Add additional willreturn tests (NFC) (details)
  327. [DSE] Add tests with stores of existing values. (details)
  328. [libc][NFC] change isblank and iscntrl from implicit casting (details)
  329. [test] Add Clang side tests for -fdebug-info-for-profiling (details)
  330. [NFC] Fix build break by a initializer list converting error (details)
  331. Revert "[AsmParser] make .ascii support spaces as separators" (details)
  332. [NewPM] Only non-trivially loop unswitch at -O3 and for non-optsize functions (details)
  333. [SPARC] Fix fp128 load/stores (details)
  334. Fix llvm::Optional build breaks in MSVC using std::is_trivially_copyable (details)
  335. [NFC] Rename ThinLTOPhase to ThinOrFullLTOPhase and move it from PassBuilder.h (details)
  336. [SystemZ]  Clear Available set in SystemZPostRASchedStrategy::initialize(). (details)
  337. [libunwind] Unwind through aarch64/Linux sigreturn frame (details)
  338. [flang] Add tests for procedure arguments with implicit interfaces (details)
  339. [RISCV] Custom lower ISD::VSCALE. (details)
  340. Fix grammar in diagnostic for wrong arity in a structured binding. (details)
  341. [Support] On Windows, take the affinity mask into account (details)
  342. [PowerPC] Try to fold sqrt/sdiv test results with the branch. (details)
  343. Revert "[Support] On Windows, take the affinity mask into account" (details)
  344. ADT: Fix reference invalidation in SmallVector::push_back and single-element insert (details)
  345. [NFC] Remove unused entry in PassRegistry.def (details)
  346. Revert "ADT: Fix reference invalidation in SmallVector::push_back and single-element insert" (details)
  347. [llvm] Use *Set::contains (NFC) (details)
  348. [llvm] Use llvm::stable_sort (NFC) (details)
  349. [llvm] Use std::any_of (NFC) (details)
  350. Reapply "ADT: Fix reference invalidation in SmallVector::push_back and single-element insert" (details)
  351. ADT: Fix reference invalidation in N-element SmallVector::append and insert (details)
  352. [NFC] Fix -Wsometimes-uninitialized (details)
  353. ADT: Fix reference invalidation in SmallVector::resize (details)
  354. ADT: Reduce code duplication in SmallVector::resize by using pop_back_n, NFC (details)
  355. ADT: Reduce code duplication in SmallVector by reusing reserve, NFC (details)
  356. [Driver] -gsplit-dwarf: Produce .dwo regardless of -gN for -fthinlto-index= (details)
  357. ADT: Reduce code duplication in SmallVector by calling reserve and clear, NFC (details)
  358. Fix unused variable in CoroFrame.cpp when building Release with GCC 10 (details)
  359. Add func call so we don't instruction-step into the builtin_trap (details)
  360. [lldb][wasm] Parse DWO section names (details)
  361. Implement vAttachWait in lldb-server (details)
  362. [mlir] Update doc to omit the usage of LLVMIntegerType (details)
  363. [lldb] Fix TestPlatformProcessConnect.py (details)
  364. [NFC][AsmPrinter] Windows warning: Use explicit cast (details)
  365. [AArch64] Adding ACLE intrinsics for the LS64 extension (details)
  366. [LTO] Expose opt() in LTOBackend (NFC). (details)
  367. [lld][WebAssembly] Add support for handling table symbols (details)
  368. [SLP] Don't vectorize stores of non-packed types (like i1, i2) (details)
  369. [clang] Use SourceLocations in unions [NFCI] (details)
  370. [DAG] visitVECTOR_SHUFFLE - pull out shuffle merging code into lambda helper. NFCI. (details)
  371. [X86] Improve sum-of-reductions v4f32 test coverage (details)
  372. [lldb/test] Ensure launched processes are ready to be attached (details)
  373. [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - reset shuffle ops and reorder early-out and second op matching. NFCI. (details)
  374. [clangd] Add main file macros into the main-file index. (details)
  375. Change XCore code owner. (details)
  376. [clang][cli] NFC: Remove SSPBufferSize assignment (details)
  377. [clang][cli] Port more CodeGenOptions to marshalling infrastructure (details)
  378. Revert "Fix llvm::Optional build breaks in MSVC using std::is_trivially_copyable" (details)
  379. [clang-tidy] Use DenseSet<SourceLocation> in UpgradeDurationConversionsCheck, NFCI (details)
  380. [flang][driver] Unify f18_version.h.in and Version.inc.in (details)
  381. [InferFunctionAttrs] Improve CHECK variable names (NFC). (details)
  382. [SelectionDAG] Make use of KnownBits::commonBits. NFC. (details)
  383. [Analysis,CodeGen] Make use of KnownBits::makeConstant. NFC. (details)
  384. [Support] Simplify KnownBits::icmp helpers. NFC. (details)
  385. [Support] Add KnownBits::sextInReg exhaustive tests (details)
  386. [docs] Update DebuggingJITedCode page after fix in LLDB (details)
  387. [Support] Ensure KnownBits::sextInReg can handle the src == dst sext-in-reg case. (details)
  388. [flang] Fix dangling pointer in LabelEnforce (details)
  389. [OpenCL] Improve online documentation. (details)
  390. [mlir][linalg] Add docstring support for named op spec (details)
  391. [Support] Simplify KnownBits::sextInReg implementation. (details)
  392. [TableGen] Enhance !cast<string> to handle bit and bits types. (details)
  393. Revert "[AArch64] Attempt to sink mul operands" (details)
  394. [Support] Remove redundant sign bit tests from KnownBits::getSignedMinValue/getSignedMaxValue (details)
  395. [SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds (details)
  396. [clangd] Remove another option that was effectively always true. NFC (details)
  397. Revert "[RISCV] Legalize select when Zbt extension available" (details)
  398. [flang][driver] Use __FLANG_VERISION__ in f18.cpp (nfc) (details)
  399. [NFC] Disallow unused prefixes under MC/ARM (details)
  400. [clangd] Make AST-based signals available to runWithPreamble. (details)
  401. [clangd] Trivial: Documentation fix in ASTSignals. (details)
  402. [gn build] Port 2f395b7092bd (details)
  403. [flang] Fix some module file issues exposed by Whizard (details)
  404. [NFC] Disallow unused prefixes under MC/AArch64 (details)
  405. [NewPM] Fix placement of LoopFlatten (details)
  406. [X86][AVX] Adjust unsigned saturation downconvert negative test (details)
  407. [libomptarget][amdgpu] Fix kernel launch tracing to match previous behavior (details)
  408. [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax (details)
  409. [LLDB] MinidumpParser: Prefer executable module even at higher address (details)
  410. [HIP] Add signbit(long double) decl (details)
  411. Support emptiness checks for unbounded FlatAffineConstraints. (details)
  412. [OpenMP] Drop the static library libomptarget-nvptx (details)
  413. [clang][MSVC] Fix missing MSInheritanceAttr in template specialization. (details)
  414. [X86] Add the FSRM feature (Fast Short Rep Mov) to Zen3. (details)
  415. [OpenMP] Dropped unnecessary define when compiling deviceRTLs for NVPTX (details)
  416. [GWP-ASan] Minor refactor of optional components. (details)
  417. [openacc] Rename generated file from ACC.cpp.inc to ACC.inc to match D92955 (details)
  418. [NFC] Update test to not check for 'opaque' in the file name. (details)
  419. [MLIR][TOSA] First lowerings from Tosa to Linalg (details)
  420. Add newline to terminate debug message (NFC) (details)
  421. [BasicAA] Handle recursive queries more efficiently (details)
  422. [mlir][ODS] Add new RangedTypesMatchWith operation predicate (details)
  423. [mlir][OpFormatGen] Format enum attribute cases as keywords when possible (details)
  424. [Driver] -gsplit-dwarf: Produce .dwo regardless of -gN for IR input (details)
  425. [RISCV] Merge Utils library into MCTargetDesc (details)
  426. [mlir][PatternRewriter] Add a new hook to selectively replace uses of an operation (details)
  427. [mlir] Remove TosaToLinalg dependency on all Passes (details)
  428. [clang] Do not crash when CXXRecordDecl has a non-CXXRecordDecl base. (details)
  429. [mlir][docs] Bring bufferization docs up to date. (details)
  430. [PowerPC] Only use some extend mne if assembler is modern enough (details)
  431. [gn build] (manually) port 387d3c24792f (details)
  432. [libc] Use #undef isascii in specific header (details)
  433. Add -fexceptions to test as it uses them and fails on platforms where it is not on by default (like the PS4). (details)
  434. [RISCV] Optimize select_cc after fp compare expansion (details)
  435. Re-land [Support] On Windows, take the affinity mask into account (details)
  436. [LTO] Test format fix (NFC) (details)
  437. [RISCV][NFC] Regenerate Calling Convention Tests (details)
  438. [mlir] Remove over specified memory effects (details)
  439. [clangd] Reduce logspam for CDB scanning (details)
  440. [mlir][Linalg] Add canonicalization to remove no-op linalg operations. (details)
  441. [SLP] remove unnecessary state in matching reductions (details)
  442. [OpenMP] Remove omptarget-nvptx from deps as it is no longer a valid target (details)
  443. [mlir][Linalg] Add canonicalization of linalg op -> dim op. (details)
  444. [mlir][Linalg] NFC: Verify tiling on linalg.generic operation on tensors. (details)
  445. [libomptarget][nvptx][nfc] Move target_impl functions out of header (details)
  446. [flang] Fix use-associated procedure in generic (details)
  447. [AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions. (details)
  448. Reland "[AsmParser] make .ascii support spaces as separators" (details)
  449. [libomptarget][nvptx] Reduce calls to cuda header (details)
  450. [libTooling] Change `addInclude` to use expansion locs. (details)
  451. [AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP. (details)
  452. [libc] Add memmove implementation. (details)
  453. [CodeGen, Transforms] Use llvm::sort (NFC) (details)
  454. [llvm] Use llvm::drop_begin (NFC) (details)
  455. [llvm] Remove redundant return and continue statements (NFC) (details)
  456. Add Semantic check for Flang OpenMP 4.5 - 2.7.1  Do Loop restrictions on single directive and firstprivate clause. (details)
  457. [mlir][sparse] retry sparse-only for cyclic iteration graphs (details)
  458. [clang][cli] NFC: Decrease the scope of ParseLangArgs parameters (details)
  459. [clang][cli] NFC: Decrease the scope of ParseCodeGenArgs parameters (details)
  460. [clang][cli] Specify KeyPath prefixes via TableGen classes (details)
  461. [AArch64] Add Fujitsu A64FX scheduling model (details)
  462. [WebAssembly] Add support for table linking to wasm-ld (details)
  463. Revert "Reapply "ADT: Fix reference invalidation in SmallVector::push_back and single-element insert"" (details)
  464. [Clang] Mutate long-double math builtins into f128 under IEEE-quad (details)
  465. [llvm-readobj] - Fix the compilation with GCC < 7.0. (details)
  466. [AArch64][GlobalISel] Fix fallbacks introduced for G_SITOFP in 8f283cafddfa8d6d01a94b48cdc5d25817569e91 (details)
  467. [libcxx testing] Fix UB in tests for std::lock_guard (details)
  468. [Debuginfo][DW_OP_implicit_pointer] (1/7) Support for DW_OP_LLVM_implicit_pointer (details)
  469. [llvm-nm] - Move MachO specific logic out from the dumpSymbolNamesFromObject(). NFC. (details)
  470. [libc] Allow customization of memcpy via flags. (details)
  471. [llvm-nm] - Simplify the code in dumpSymbolNamesFromObject. NFC. (details)
  472. [ARM][GISel] Treat calls as variadic even if only fixed arguments provided (details)
  473. [yaml2obj/obj2yaml] - Refine handling of SHT_GNU_verdef sections. (details)
  474. [llvm-readobj][test] - Remove excessive YAML fields from tests. (details)
  475. [clangd] exclude symbols from document outline which do not originate from the main file (details)
  476. [LLDB] Add per-thread register infos shared pointer in gdb-remote (details)
  477. DynamicRegisterInfo calculate offsets in separate function (details)
  478. [RISCV] Optimize Branch Comparisons (details)
  479. [SVE] Restrict the usage of REINTERPRET_CAST. (details)
  480. [Orc][NFC] Turn LLJIT member ObjTransformLayer into unique_ptr (details)
  481. [Orc] Allow LLJITBuilder's CreateObjectLinkingLayer to return errors (details)
  482. [NFC][RISCV] Remove useless code in RISCVRegisterInfo.td. (details)
  483. [lldb][docs] Use sphinx instead of epydoc to generate LLDB's Python reference (details)
  484. [Orc] Fix OrcV2Examples after D94690 (details)
  485. Revert "[lldb][docs] Use sphinx instead of epydoc to generate LLDB's Python reference" (details)
  486. [clangd] Make ExpandAutoType not available on template params. (details)
  487. [clangd] Set correct CWD when using compile_flags.txt (details)
  488. [lldb][docs] Translate ASCII art to restructured text formatting (details)
  489. [X86][AVX] combineHorizOpWithShuffle - support target shuffles in HOP(SHUFFLE(X,Y),SHUFFLE(X,Y)) -> SHUFFLE(HOP(X,Y)) (details)
  490. [WebAssembly] MC layer writes table symbols to object files (details)
  491. [ARM] Don't run the block placement pass at O0 (details)
  492. [mlir][linalg] Support generating builders for named op attributes (details)
  493. [SVE] Fix unused variable. (details)
  494. [OpenCL][Docs] Fixed malformed table in OpenCLSupport (details)
  495. [clang][cli] Parse & generate options necessary for LangOptions defaults manually (details)
  496. [X86] Add umin knownbits/demandedbits ult test for D94532 (details)
  497. Set option default for enabling memory ssa for new pass manager loop sink pass to true. (details)
  498. [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - improve shuffle(shuffle(x,y),shuffle(x,y)) merging (details)
  499. [mlir] Add better support for f80 and f128 (details)
  500. [libc] CopyAlignedBlocks can now specify alignment on top of block size (details)
  501. [RISCV][NFC] Fix order of parameters in cmov ge/le tests (details)
  502. [clang][cli] NFC: Add PIE parsing for precompiled input and IR (details)
  503. [clang][cli] NFC: Parse some LangOpts after the defaults are set (details)
  504. [clang][cli] NFC: Promote ParseLangArgs and ParseCodeGenArgs to members (details)
  505. [ARM][Block placement] Check the predecessor exists before processing it (details)
  506. [X86][SSE] Attempt to fold shuffle(binop(),binop()) -> binop(shuffle(),shuffle()) (details)
Commit 7539c75bb438f185575573ed4ea8da7cb37d3f2a by qshanz
[DAGCombine] Remove the check for unsafe-fp-math when we are checking the AFN

We are checking the unsafe-fp-math for sqrt but not for fpow, which behaves inconsistent.
As the direction is to remove this global option, we need to remove the unsafe-fp-math
check for sqrt and update the test with afn fast-math flags.

Reviewed By: Spatel

Differential Revision: https://reviews.llvm.org/D93891
The file was modifiedllvm/test/CodeGen/NVPTX/fast-math.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-combines.ll
The file was modifiedllvm/test/CodeGen/X86/sqrt-fastmath.ll
The file was modifiedllvm/test/CodeGen/NVPTX/sqrt-approx.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/frem.ll
Commit 5cf73dca77e52f54c893d2c5fc2f56a5f2764f7d by craig.topper
[RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags.

This patch moves all but the BaseInstr to bits in TSFlags.

For the index fields, we can just use a bit to indicate their presence.
The locations of the operands are well defined.

This reduces the llc binary by about 32K on my build. It also
removes the binary search of the table from the custom inserter.
Instead we just check that the SEW op is present.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D94375
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrFormats.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 7f69860243e8933c3da1177afde0d3cb6544d04e by serguei.katkov
[LoopUnroll] Fix a crash

Loop peeling as a last step triggers loop simplification and this
can change the loop structure. As a result all cashed values like
latch branch becomes invalid.

Patch re-structure the code to take into account the possible
changes caused by peeling.

Reviewers: dmgreen, Meinersbur, etiotto, fhahn, efriedma, bmahjour
Reviewed By: Meinersbur, fhahn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D93686
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
The file was addedllvm/test/Transforms/LoopUnroll/unroll-after-peel.ll
Commit ffa67873a3f93a6baa0046221edd08a90b0db6f8 by esme.yi
[PowerPC] Add variants of 64-bit vector types for vec_sel.

Summary: This patch added variants of vec_sel and fixed bugzilla 46770.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D94162
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/test/CodeGen/builtins-ppc-vsx.c
Commit dcac2da10632c83737fce6da60fbc4dd09c01034 by clattner
[IR Parser] Fix a crash handling zero width integer attributes.

llvm::APInt cannot hold zero bit values, therefore we shouldn't try
to form them.

Differential Revision: https://reviews.llvm.org/D94384
The file was modifiedmlir/test/IR/invalid-ops.mlir
The file was modifiedmlir/lib/Parser/AttributeParser.cpp
Commit 6215c1b778f62433f3d79addc299a1bbd0e524d0 by i
CGDebugInfo: Delete redundant test
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
Commit b8d28420885a42d16a57e02c28129d0eb92474a1 by i
CGDebugInfo: Delete unneeded UnwrapTypeForDebugInfo

Tested with stage 2 -DCMAKE_BUILD_TYPE=Debug clang, byte identical.
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
Commit a40767ec8851b997e4dcc9987078bd02670f8c7f by kareem.ergawy
[MLIR][SPIRV] Add (de-)serialization support for SpecConstantOpeation.

This commit adds support for (de-)serializing SpecConstantOpeation. One
thing worth noting is that during deserialization, we assign a fake ID to
enclosed ops inside SpecConstantOpeation. We need to do this in order
for deserialization logic to properly update ID to value map and to
later reference the created value from the sibling 'spv::YieldOp'.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D93591
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
The file was modifiedmlir/lib/Target/SPIRV/Serialization.cpp
The file was modifiedmlir/test/Target/SPIRV/spec-constant.mlir
The file was modifiedmlir/lib/Target/SPIRV/Deserialization.cpp
The file was modifiedmlir/test/Dialect/SPIRV/IR/structure-ops.mlir
The file was modifiedmlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
Commit 5e476061deb82ed4e6d440445f8830e1c7bccaa6 by kai.wang
[NFC][AsmPrinter] Make comments for spill/reload more precise.

The size of spill/reload may be unknown for scalable vector types.
When the size is unknown, print it as "Unknown-size" instead of a very
large number.

Differential Revision: https://reviews.llvm.org/D94299
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Commit 7b11f564dcfc867c3e7a2075e8a943014fe30780 by Lang Hames
[JITLink] Rename PostAllocationPasses to PreFixupPasses.

PreFixupPasses better reflects when these passes will run.

A future patch will (re)introduce a PostAllocationPasses list that will run
after allocation, but before JITLinkContext::notifyResolved is called to notify
the rest of the JIT about the resolved symbol addresses.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
The file was modifiedllvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
The file was modifiedllvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
Commit 131ce834e4bbe443a0da0e0ce00c8d0fa4412458 by craig.topper
[RISCV] Clear isCodeGenOnly flag on VMSGE(U) pseudo instructions. Remove InstAliases that duplicate the asm strings in the pseudos.

The Pseudo class sets isCodeGenOnly=1 which causes the asm strings
in the pseudos to be ignored. I think this is why the aliases are
needed at all.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D94024
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
Commit af339f89a142622b6fc56c5f79d19e568af5287a by akuegel
Remove redundant casts.

Differential Revision: https://reviews.llvm.org/D94305
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
Commit cddd3faf5debdfd2c09bb5b723f579fa8c8d5027 by zixuan.wu
[CSKY] Add visibility macro to fix link error

Add LLVM_EXTERNAL_VISIBILITY macro to fix link error of
https://reviews.llvm.org/D88466#2476378
The file was modifiedllvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
Commit ee27c767bd2062c81f0affc0e8992f60a755f099 by marek.kurdej
[clang-format] Skip UTF8 Byte Order Mark while sorting includes

If file contain BOM then first instruction (include or clang-format off) is ignored

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D94201
The file was modifiedclang/lib/Format/Format.cpp
The file was modifiedclang/unittests/Format/SortIncludesTest.cpp
Commit 0c8b748f321736d016da0f6d710778f503a89b51 by david.green
[ARM] Additional trunc cost tests. NFC
The file was modifiedllvm/test/Analysis/CostModel/ARM/cast.ll
Commit 7473940bae0f263832456d2c99a4bd606ed0d76e by marek.kurdej
[clang-format] turn on formatting after "clang-format on" while sorting includes

Formatting is not active after "clang-format on" due to merging lines while formatting is off. Also, use trimmed line. Behaviour with LF is different than with CRLF.

Reviewed By: curdeius, MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D94206
The file was modifiedclang/unittests/Format/SortIncludesTest.cpp
The file was modifiedclang/lib/Format/Format.cpp
Commit 89878e8c966a82ed6b7f0254700017f0a97fb7d7 by marek.kurdej
[clang-format] Find main include after block ended with #pragma hdrstop

Find main include in first include block not ended with #pragma hdrstop

Reviewed By: curdeius

Differential Revision: https://reviews.llvm.org/D94217
The file was modifiedclang/unittests/Format/SortIncludesTest.cpp
The file was modifiedclang/lib/Format/Format.cpp
Commit dcefcd51e01741c79c9d9a729fe803b13287a372 by david.green
[ARM] Update trunc costs

We did not have specific costs for larger than legal truncates that were
not otherwise cheap (where they were next to stores, for example). As
MVE does not have a dedicated instruction for them (and we do not use
loads/stores yet), they should be expensive as they get expanded to a
series of lane moves.

Differential Revision: https://reviews.llvm.org/D94260
The file was modifiedllvm/test/Analysis/CostModel/ARM/arith-overflow.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/ARM/cast.ll
The file was modifiedllvm/test/Analysis/CostModel/ARM/mve-gather-scatter-cost.ll
Commit b7ccaca53700fce21b0e8e5d7bd2a956bd391fee by david.sherwood
[NFC] Remove min/max functions from InstructionCost

Removed the InstructionCost::min/max functions because it's
fine to use std::min/max instead.

Differential Revision: https://reviews.llvm.org/D94301
The file was modifiedllvm/include/llvm/Support/InstructionCost.h
The file was modifiedllvm/unittests/Support/InstructionCostTest.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 97100646d1b4526de1eac3aacdb0b098739c6ec9 by Jan Svoboda
Reapply "[clang][cli] Port DiagnosticOpts to new option parsing system"

This reverts commit 8e3e148c

This commit fixes two issues with the original patch:
* The sanitizer build bot reported an uninitialized value. This was caused by normalizeStringIntegral not returning None on failure.
* Some build bots complained about inaccessible keypaths. To mitigate that, "this->" was added back to the keypath to restore the previous behavior.
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedllvm/include/llvm/Option/OptParser.td
The file was modifiedclang/unittests/Frontend/CompilerInvocationTest.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticOptions.h
The file was modifiedllvm/utils/TableGen/OptParserEmitter.cpp
Commit 40abeb11f4584e8a07163d6c7e24011ac45f104c by david.sherwood
[NFC][InstructionCost] Change LoopVectorizationCostModel::getInstructionCost to return InstructionCost

This patch is part of a series of patches that migrate integer
instruction costs to use InstructionCost. In the function
selectVectorizationFactor I have simply asserted that the cost
is valid and extracted the value as is. In future we expect
to encounter invalid costs, but we should filter out those
vectorization factors that lead to such invalid costs.

See this patch for the introduction of the type: https://reviews.llvm.org/D91174
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html

Differential Revision: https://reviews.llvm.org/D92178
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 8165a0342033e58ce6090fbc425ebdc7c455469f by david.green
[ARM] Add debug messages for the load store optimizer. NFC
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Commit 1677c86124e5b82a8dbf991f2d5fc450d06db4ad by hokein.wu
[clangd] Add metrics for go-to-implementation.

Differential Revision: https://reviews.llvm.org/D94393
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
Commit c5be0e0cc0e2fca19a5d130b742ae16c66f99111 by yuanke.luo
[X86] Fix tile register spill issue.

The tile register spill need 2 instructions.
%46:gr64_nosp = MOV64ri 64
TILESTORED %stack.2, 1, killed %46:gr64_nosp, 0, $noreg, %43:tile
The first instruction load the stride to a GPR, and the second
instruction store tile register to stack slot. The optimization of merge
spill instruction is done after register allocation. And spill tile
register need create a new virtual register to for stride, so we can't
hoist tile spill instruction in postOptimization() of register
allocation. We can't hoist TILESTORED alone and we can't hoist the 2
instuctions together because MOV64ri will clobber some GPR. This patch
is to disble the spill merge for any spill which need 2 instructions.

Differential Revision: https://reviews.llvm.org/D93898
The file was addedllvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp
Commit 675be651062476cd0cd4b491b35c275bb03d7b2c by bjorn.a.pettersson
Require chained analyses in BasicAA and AAResults to be transitive

This patch fixes a bug that could result in miscompiles (at least
in an OOT target). The problem could be seen by adding checks that
the DominatorTree used in BasicAliasAnalysis and ValueTracking was
valid (e.g. by adding DT->verify() call before every DT dereference
and then running all tests in test/CodeGen).

Problem was that the LegacyPassManager calculated "last user"
incorrectly for passes such as the DominatorTree when not telling
the pass manager that there was a transitive dependency between
the different analyses. And then it could happen that an incorrect
dominator tree was used when doing alias analysis (which was a pretty
serious bug as the alias analysis result could be invalid).

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48709

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D94138
The file was modifiedllvm/lib/Analysis/BasicAliasAnalysis.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
The file was modifiedllvm/lib/Transforms/Scalar/GVNHoist.cpp
The file was modifiedllvm/lib/Analysis/AliasAnalysis.cpp
Commit c37f68a8885cf55e9a6603613a918c4e7474e9af by kerry.mclaughlin
[SVE][CodeGen] Fix legalisation of floating-point masked gathers

Changes in this patch:
- When lowering floating-point masked gathers, cast the result of the
  gather back to the original type with reinterpret_cast before returning.
- Added patterns for reinterpret_casts from integer to floating point, and
  concat_vector patterns for bfloat16.
- Tests for various legalisation scenarios with floating point types.

Reviewed By: sdesmalen, david-arm

Differential Revision: https://reviews.llvm.org/D94171
The file was modifiedllvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 41bf338dd1e7f07c1e89f171ff6d53578f5125be by llvm-dev
Revert rGd43a264a5dd3 "Revert "[X86][SSE] Fold unpack(hop(),hop()) -> permute(hop())""

This reapplies commit rG80dee7965dffdfb866afa9d74f3a4a97453708b2.

[X86][SSE] Fold unpack(hop(),hop()) -> permute(hop())

UNPCKL/UNPCKH only uses one op from each hop, so we can merge the hops and then permute the result.

REAPPLIED with a fix for unary unpacks of HOP.
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle-2.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 5963229266303d83b2e9de09bce7e063276e41d0 by llvm-dev
[X86][SSE] Add missing SSE test coverage for permute(hop,hop) folds

Should help avoid bugs like reported in rG80dee7965dff
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle-2.ll
The file was addedllvm/test/CodeGen/X86/horizontal-shuffle-3.ll
Commit b72ca799823e97b94ac0144bb87c094fb2db7324 by marukawa
[VE] Support intrinsic to isnert/extract_subreg of v512i1

Support insert/extract_subreg intrinsic instructions for v512i1
registers and add regression tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D94298
The file was modifiedllvm/lib/Target/VE/VEInstrIntrinsicVL.td
The file was addedllvm/test/CodeGen/VE/VELIntrinsics/insert.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsVE.td
The file was addedllvm/test/CodeGen/VE/VELIntrinsics/extract.ll
Commit d02de13932488841eb104ad2a5665fdf7db4026b by marukawa
[VE] Support additional VMRGW and VMV intrinsic instructions

Support missing VMRGW and VMV intrinsic instructions and add regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D94300
The file was modifiedllvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
The file was modifiedllvm/lib/Target/VE/VEInstrIntrinsicVL.td
The file was modifiedllvm/test/CodeGen/VE/VELIntrinsics/vmv.ll
Commit c74751d4b5bd8e6753ba8dbc5baa88d7c8929c5c by grimar
[obj2yaml] - Fix the crash in getUniquedSectionName().

`getUniquedSectionName(const Elf_Shdr *Sec)` assumes that
`Sec` is not `nullptr`.

I've found one place in `getUniquedSymbolName` where it is
not true (because of that we crash when trying to dump
unnamed null section symbols).

Patch fixes the crash and changes the signature of the
`getUniquedSectionName` section to accept a reference.

Differential revision: https://reviews.llvm.org/D93754
The file was modifiedllvm/test/tools/obj2yaml/ELF/symbol.yaml
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
Commit 8ea72b388734ce660f861e0dfbe53d203e94876a by joe.ellis
[clang][AArch64][SVE] Avoid going through memory for coerced VLST return values

VLST return values are coerced to VLATs in the function epilog for
consistency with the VLAT ABI. Previously, this coercion was done
through memory. It is preferable to use the
llvm.experimental.vector.insert intrinsic to avoid going through memory
here.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D94290
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-call.c
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
The file was modifiedclang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
Commit a6db7cf1ce7f3523adb132819c1697a572bdcfde by grimar
[llvm-readelf/obj] - Index phdrs and relocations from 0 when reporting warnings.

As was mentioned in comments here:
https://reviews.llvm.org/D92636#inline-864967

we are not consistent and sometimes index things from 0, but sometimes
from 1 in warnings.

This patch fixes 2 places: messages reported for
program headers and messages reported for relocations.

Differential revision: https://reviews.llvm.org/D93805
The file was modifiedllvm/test/tools/llvm-readobj/ELF/gnu-notes.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/relocations.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/relocation-errors.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/stack-sizes.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/note-core-ntfile-bad.test
Commit a94497a34290bea077398c83d3031179c08ec2e7 by flo
[VPlan] Move initial quote emission from ::print to ::dumpBasicBlock.

This means there will be no stray " when printing individual recipes
using print()/dump() in a debugger, for example.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
Commit a5b484c4d41a7452b590a2c1c98dc31f43d3dc1a by grimar
[obj2yaml][test] - Improve and fix section-group.yaml test.

It has multiple issues fixed by this patch:
1) It shouldn't test how llvm-readelf/yaml2obj works.
2) It should use "-NEXT" prefix for check lines.
3) It can use YAML macros, that allows to use a single YAML.
4) It should probably test the case when a group member is a null section.

Differential revision: https://reviews.llvm.org/D93753
The file was modifiedllvm/test/tools/obj2yaml/ELF/section-group.yaml
Commit d36e879c21c9620c9b6a1a8f45afe46379142d2f by pavel
[lldb] Disable PipeTest.OpenAsReader on windows

This test seems to be broken there (which is not totally surprising as
this functionality was never used on windows). Disable the test while I
investigate.
The file was modifiedlldb/unittests/Host/PipeTest.cpp
Commit 8112a2598ce180ab4cd106f154a71e813fc28d91 by llvm-dev
[X86][SSE] Add 'vectorized sum' test patterns

These are often generated when building a vector from the reduction sums of independent vectors.

I've implemented some typical patterns from various v4f32/v4i32 based off current codegen emitted from the vectorizers, although these tests are more about tweaking some hadd style backend folds to handle whatever the vectorizers/vectorcombine throws at us...
The file was addedllvm/test/CodeGen/X86/horizontal-sum.ll
Commit 2e17d9c0ee7a0ba2aff7dd449005e4d0fd10fe57 by herhut
[ARM] Add uses for locals introduced for debug messages. NFC.

This adds uses for locals introduced for new debug messages for the load store optimizer. Those locals are only used on debug statements and otherwise create unused variable warnings.

Differential Revision: https://reviews.llvm.org/D94398
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Commit 6dcf9207df11f5cdb0126e5c5632e93532642ed9 by jay.foad
[AMDGPU] Fix a urem combine test to test what it was supposed to
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
Commit 4fe7b16ae3f48a36967e58ab753381cb34295962 by csigg
[mlir] Remove unnecessary llvm.mlir.cast in AsyncToLLVM lowering.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D94400
The file was modifiedmlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
Commit 4c372a35cd892c0847da45540057447633a31d99 by csigg
[mlir] Make GpuAsyncRegion pass depend on async dialect.

Do not cache gpu.async.token type so that the pass can be created before the GPU dialect is registered.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D94397
The file was modifiedmlir/lib/Dialect/GPU/Transforms/AsyncRegionRewriter.cpp
The file was modifiedmlir/include/mlir/Dialect/GPU/Passes.td
The file was modifiedmlir/lib/Dialect/GPU/Transforms/PassDetail.h
Commit 8298ec2d6299a95d2920cb8ee993ac6c5e604097 by andrzej.warzynski
[flang][driver] Copy input files into a temp dir when testing

The following frontend driver invocation will generate 2 output files
in the same directory as the input files:
```
flang-new -fc1 input-1.f input-2.f
```
This is the desired behaviour. However, when testing we need to make
sure that we don't pollute the source directory. To this end, copy test
input files into a temporary directory.

Differential Revision: https://reviews.llvm.org/D94243
The file was modifiedflang/test/Frontend/multiple-input-files.f90
Commit df86f15f0c53c395dac5a14aba08745bc12b9b9b by antiagainst
[mlir][linalg] Support parsing attributes in named op spec

With this, now we can specify a list of attributes on named ops
generated from the spec. The format is defined as

```
attr-id ::= bare-id (`?`)?
attr-typedef ::= type (`[` `]`)?
attr-def ::= attr-id `:` attr-typedef

tc-attr-def ::= `attr` `(` attr-def-list `)`
tc-def ::= `def` bare-id
  `(`tensor-def-list`)` `->` `(` tensor-def-list`)`
  (tc-attr-def)?
```

For example,

```
ods_def<SomeCppOp>
def some_op(...) -> (...)
attr(
  f32_attr: f32,
  i32_attr: i32,
  array_attr : f32[],
  optional_attr? : f32
)
```

where `?` means optional attribute and `[]` means array type.

Reviewed By: hanchung, nicolasvasilache

Differential Revision: https://reviews.llvm.org/D94240
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
Commit 55225471d9838e452cfb31e0edae6162b7226221 by antiagainst
[mlir][linalg] Support permutation when lowering to loop nests

Linalg ops are perfect loop nests. When materializing the concrete
loop nest, the default order specified by the Linalg op's iterators
may not be the best for further CodeGen: targets frequently need
to plan the loop order in order to gain better data access. And
different targets can have different preferences. So there should
exist a way to control the order.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D91795
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Loops.cpp
The file was addedmlir/test/Dialect/Linalg/loop-order.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
Commit 007358239decd45819a6fa44eb2a2e07fd85e796 by joe.ellis
[DAGCombiner] Use getVectorElementCount inside visitINSERT_SUBVECTOR

This avoids TypeSize-/ElementCount-related warnings.

Differential Revision: https://reviews.llvm.org/D92747
The file was addedllvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit c163aae45ef6b7f3bd99601195d3ce4aad5850c6 by Artem Dergachev
[attributes]  Add a facility for enforcing a Trusted Computing Base.

Introduce a function attribute 'enforce_tcb' that prevents the function
from calling other functions without the same attribute. This allows
isolating code that's considered to be somehow privileged so that it could not
use its privileges to exhibit arbitrary behavior.

Introduce an on-by-default warning '-Wtcb-enforcement' that warns
about violations of the above rule.

Introduce a function attribute 'enforce_tcb_leaf' that suppresses
the new warning within the function it is attached to. Such leaf functions
may implement common functionality between the trusted and the untrusted code
but they require extra careful audit with respect to their capabilities.

Differential Revision: https://reviews.llvm.org/D91898
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was modifiedclang/include/clang/Sema/Sema.h
The file was addedclang/test/Sema/attr-enforce-tcb.c
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was addedclang/test/Sema/attr-enforce-tcb.cpp
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was addedclang/test/Sema/attr-enforce-tcb-errors.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
Commit eb0371e403a67fdb580e24b9911107bfc9a828b3 by flo
[VPlan] Unify value/recipe printing after VPDef transition.

This patch unifies the way recipes and VPValues are printed after the
transition to VPDef.

VPSlotTracker has been updated to iterate over all recipes and all
their defined values to number those. There is no need to number
values in Value2VPValue.

It also updates a few places that only used slot numbers for
VPInstruction. All recipes now can produce numbered VPValues.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanSLP.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-printing.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
Commit 419ef38a50293c58078f830517f5e305068dbee6 by thakis
Revert "[attributes]  Add a facility for enforcing a Trusted Computing Base."

This reverts commit c163aae45ef6b7f3bd99601195d3ce4aad5850c6.
Doesn't compile on some bots
(http://lab.llvm.org:8011/#/builders/98/builds/3387/steps/9/logs/stdio),
breaks tests on bots where it does compile
(http://45.33.8.238/linux/36843/step_7.txt).
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was removedclang/test/Sema/attr-enforce-tcb-errors.cpp
The file was removedclang/test/Sema/attr-enforce-tcb.c
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was removedclang/test/Sema/attr-enforce-tcb.cpp
Commit d59ddba777251c59a667d03021900c72f9882a4b by csigg
[mlir] Fix gpu-to-llvm lowering for gpu.alloc with dynamic sizes.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D94402
The file was modifiedmlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
The file was modifiedmlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
The file was modifiedmlir/test/Conversion/GPUCommon/lower-alloc-to-gpu-runtime-calls.mlir
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
Commit a46982a25511bd0da82f3f2637912dfd86042929 by llvm-dev
[X86] Add nounwind to lzcnt-cmp tests

Remove unnecessary cfi markup
The file was modifiedllvm/test/CodeGen/X86/lzcnt-cmp.ll
Commit a0f82749f4f3373ba85de40c69b866081f77abce by llvm-dev
[X86] Extend lzcnt-cmp tests to test on non-lzcnt targets
The file was modifiedllvm/test/CodeGen/X86/lzcnt-cmp.ll
Commit dbd5fa1e75d812ab31b1d71b23f506c2cbc7a93d by ranjeet.singh
[ARM] Update existing test case with +pauth targets

Differential Revision: https://reviews.llvm.org/D94414
The file was modifiedllvm/test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt
Commit a2dbf3443af79426c80e8a808821236c5a2b305e by hokein.wu
[clangd] Fix -check mode doesn't respect any tidy configs.

Differential Revision: https://reviews.llvm.org/D94411
The file was modifiedclang-tools-extra/clangd/tool/Check.cpp
Commit 975170551283559ebe5052b6f83b2cc9e50132db by georgakoudis1
[OpenMPOpt][WIP] Expand parallel region merging

The existing implementation of parallel region merging applies only to
consecutive parallel regions that have speculatable sequential
instructions in-between. This patch lifts this limitation to expand
merging with any sequential instructions in-between, except calls to
unmergable OpenMP runtime functions. In-between sequential instructions
in the merged region are sequentialized in a "master" region and any
output values are broadcasted to the following parallel regions and the
sequential region continuation of the merged region.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D90909
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
The file was modifiedllvm/test/Transforms/OpenMP/parallel_region_merging.ll
Commit 31732e6f52c8e5e722d3e4cca053db793dae3b8c by n.james93
[clangd] Remove ScratchFS from tests

This can lead to issues if files in the tmp directory we don't care about / control are found.
This was partially addressed in D94321, but this is a more permanent fix.
Fixes https://github.com/clangd/clangd/issues/354

Reviewed By: adamcz, sammccall

Differential Revision: https://reviews.llvm.org/D94359
The file was modifiedclang-tools-extra/clangd/unittests/GlobalCompilationDatabaseTests.cpp
Commit e5eb5c8a7f30ddb01b7e00a010714ac9711f29de by paul.robinson
NFC: Use -LABEL more

There were a number of tests needing updates for D91734, and I added a
bunch of LABEL directives to help track down where those had to go.
These directives are an improvement independent of the functional
patch, so I'm committing them as their own separate patch.
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/AArch64/elf-globals-static.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-load-store.ll
Commit c161775decddcc86fbbfefd7485a5d0ef5842aec by paul.robinson
[FastISel] Flush local value map on every instruction

Local values are constants or addresses that can't be folded into
the instruction that uses them. FastISel materializes these in a
"local value" area that always dominates the current insertion
point, to try to avoid materializing these values more than once
(per block).

https://reviews.llvm.org/D43093 added code to sink these local
value instructions to their first use, which has two beneficial
effects. One, it is likely to avoid some unnecessary spills and
reloads; two, it allows us to attach the debug location of the
user to the local value instruction. The latter effect can
improve the debugging experience for debuggers with a "set next
statement" feature, such as the Visual Studio debugger and PS4
debugger, because instructions to set up constants for a given
statement will be associated with the appropriate source line.

There are also some constants (primarily addresses) that could be
produced by no-op casts or GEP instructions; the main difference
from "local value" instructions is that these are values from
separate IR instructions, and therefore could have multiple users
across multiple basic blocks. D43093 avoided sinking these, even
though they were emitted to the same "local value" area as the
other instructions. The patch comment for D43093 states:

  Local values may also be used by no-op casts, which adds the
  register to the RegFixups table. Without reversing the RegFixups
  map direction, we don't have enough information to sink these
  instructions.

This patch undoes most of D43093, and instead flushes the local
value map after(*) every IR instruction, using that instruction's
debug location. This avoids sometimes incorrect locations used
previously, and emits instructions in a more natural order.

In addition, constants materialized due to PHI instructions are
not assigned a debug location immediately; instead, when the
local value map is flushed, if the first local value instruction
has no debug location, it is given the same location as the
first non-local-value-map instruction.  This prevents PHIs
from introducing unattributed instructions, which would either
be implicitly attributed to the location for the preceding IR
instruction, or given line 0 if they are at the beginning of
a machine basic block.  Neither of those consequences is good
for debugging.

This does mean materialized values are not re-used across IR
instruction boundaries; however, only about 5% of those values
were reused in an experimental self-build of clang.

(*) Actually, just prior to the next instruction. It seems like
it would be cleaner the other way, but I was having trouble
getting that to work.

This reapplies commits cf1c774d and dc35368c, and adds the
modification to PHI handling, which should avoid problems
with debugging under gdb.

Differential Revision: https://reviews.llvm.org/D91734
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
The file was modifiedllvm/test/CodeGen/X86/crash-O0.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mcm-2.ll
The file was modifiedllvm/test/DebugInfo/Mips/delay-slot.ll
The file was removedllvm/test/CodeGen/X86/fast-isel-constant.ll
The file was modifiedllvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
The file was modifiedllvm/test/CodeGen/X86/pr44749.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mcm-13.ll
The file was modifiedlld/test/wasm/debug-removed-fn.ll
The file was modifiedllvm/test/CodeGen/X86/pr32284.ll
The file was modifiedllvm/test/CodeGen/X86/pr32256.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mcm-9.ll
The file was modifiedllvm/test/CodeGen/AArch64/large-stack.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-load-store.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mcm-default.ll
The file was modifiedllvm/test/CodeGen/X86/membarrier.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mcm-3.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
The file was modifiedllvm/test/CodeGen/AArch64/cfguard-checks.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mcm-1.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mcm-6.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/elf-common.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
The file was modifiedllvm/test/DebugInfo/COFF/lines-bb-start.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
The file was modifiedllvm/test/CodeGen/X86/volatile.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel.ll
The file was modifiedllvm/test/CodeGen/X86/lvi-hardening-loads.ll
The file was modifiedllvm/test/CodeGen/X86/atomic64.ll
The file was modifiedlldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/AArch64/elf-globals-static.ll
The file was modifiedllvm/test/CodeGen/X86/pr32241.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-select.ll
The file was addedllvm/test/CodeGen/X86/fast-isel-prolog-dbgloc.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-abi_align.ll
The file was modifiedlldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
The file was modifiedllvm/include/llvm/CodeGen/FastISel.h
The file was modifiedllvm/test/CodeGen/X86/fast-isel-mem.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was modifiedllvm/test/CodeGen/X86/pr32340.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
The file was modifiedllvm/test/DebugInfo/X86/fission-ranges.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
Commit 4214ca96145c9487407925b121b85fafb1179209 by llvm-dev
[X86][AVX] Attempt to fold vpermf128(op(x,i),op(y,i)) -> op(vpermf128(x,y),i)

If vpermf128/vpermi128 is acting on 2 similar 'inlane' ops, then try to perform the vpermf128 first which will allow us to merge the ops.

This will help us fix one of the regressions in D56387
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-trunc.ll
Commit 9c0dc0b2c1cc973056237bdd80dbba749941ea63 by ravishankarm
[mlir][Linalg] Fold init_tensor -> linalg.tensor_reshape.

Reshaping an init_tensor can be folded to a init_tensor op of the
final type.

Differential Revision: https://reviews.llvm.org/D93773
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Commit c15b0e2229ea04d1c36fafaa1f717f433a995e9a by scott.linder
[Clang][Docs] Fix ambiguity in clang-offload-bundler docs

Differential Revision: https://reviews.llvm.org/D94338
The file was modifiedclang/docs/ClangOffloadBundler.rst
Commit 7200d2cf0891ef56607fd0336029b33bd4097eed by mtrofin
[NFC] Disallow unused prefixes in CodeGen/PowerPC tests.

Also removed where applicable.

Differential Revision: https://reviews.llvm.org/D94385
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesiltss.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesiltuc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllgeull.ll
The file was modifiedllvm/test/CodeGen/PowerPC/lower-massv.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesileuc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesigeui.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesileull.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllltsll.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllleuc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
The file was modifiedllvm/test/CodeGen/PowerPC/lit.local.cfg
The file was modifiedllvm/test/CodeGen/PowerPC/vmladduhm.ll
The file was modifiedllvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesileui.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesiltsi.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllgeus.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
The file was modifiedllvm/test/CodeGen/PowerPC/srem-lkk.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllltuc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesiltsc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesigeull.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesiltus.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllgeui.ll
The file was modifiedllvm/test/CodeGen/PowerPC/urem-lkk.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesiltui.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesigeuc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/ppc32-pic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllltus.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllleus.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesiltsll.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesileus.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesigeus.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllleui.ll
The file was modifiedllvm/test/CodeGen/PowerPC/testComparesllleull.ll
The file was modifiedllvm/test/CodeGen/PowerPC/popcnt-zext.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_splat.ll
Commit 3d693bd0bd77fe6f0dd922be374b7ba74739871a by thomasraoux
[mlir][vector] Add memory effects to transfer_read transfer_write ops

This allow more accurate modeling of the side effects and allow dead code
elimination to remove dead transfer ops.

Differential Revision: https://reviews.llvm.org/D94318
The file was modifiedmlir/test/Conversion/VectorToSCF/vector-to-loops.mlir
The file was modifiedmlir/test/Dialect/Vector/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
Commit c4486cfd556869a837911c7719fb6c36018bbd1f by ravishankarm
[mlir][Linalg] Fix reshape fusion to reshape the outs instead of creating new tensors.

When fusing tensor_reshape ops with generic/indexed_Generic op, new
linalg.init_tensor operations were created for the `outs` of the fused
op. While correct (technically) it is better to just reshape the
original `outs` operands and rely on canonicalization of init_tensor
-> tensor_reshape to achieve the same effect.

Differential Revision: https://reviews.llvm.org/D93774
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/test/Dialect/Linalg/reshape_fusion.mlir
The file was modifiedmlir/test/Dialect/Linalg/reshape_linearization_fusion.mlir
Commit be179b9946f6dfd6e3d957d9f7a6ee992d1f69d2 by paul.robinson
[FastISel] NFC: Remove obsolete -fast-isel-sink-local-values option

This option is not used for anything after #c161665 (D91737).
This commit reapplies #a474657.
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/X86/pr32241.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel.ll
The file was modifiedllvm/test/DebugInfo/X86/prologue-stack.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-abi_align.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/AArch64/swifterror.ll
The file was modifiedllvm/test/CodeGen/X86/pr32484.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
The file was modifiedllvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
The file was modifiedllvm/test/CodeGen/X86/pr32345.ll
The file was modifiedllvm/test/DebugInfo/Mips/delay-slot.ll
The file was modifiedllvm/test/CodeGen/X86/pr32284.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-call-cleanup.ll
The file was modifiedllvm/test/CodeGen/X86/sink-local-value.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/ARM/swifterror.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
The file was modifiedllvm/test/CodeGen/X86/inreg.ll
The file was modifiedllvm/test/CodeGen/X86/pr32340.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was modifiedllvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-vararg.ll
Commit ac2224c02282039f41294842396cbbe47ea29a23 by i
[ELF] --exclude-libs: localize defined libcall symbols referenced by lto.tmp

Fixes PR48681: after LTO, lto.tmp may reference a libcall symbol not in an IR
symbol table of any bitcode file. If such a symbol is defined in an archive
matched by a --exclude-libs, we don't correctly localize the symbol.

Add another `excludeLibs` after `compileBitcodeFiles` to localize such libcall
symbols. Unfortunately we have keep the existing one for D43126.

Using VER_NDX_LOCAL is an implementation detail of `--exclude-libs`, it does not
necessarily tie to the "localize" behavior.  `local:` patterns in a version
script can be omitted.
The `symbol ... has undefined version ...` error should not be exempted.
Ideally we should error as GNU ld does. https://issuetracker.google.com/issues/73020933

Reviewed By: psmith

Differential Revision: https://reviews.llvm.org/D94280
The file was modifiedlld/ELF/Driver.cpp
The file was addedlld/test/ELF/lto/exclude-libs-libcall.ll
Commit 171771e0780fd5d028a24f8650a11299478df266 by paulsson
[SystemZ]  Minor NFC fix in SchedModels.

The unused LRMux opcode was removed by 8f8c381, but a regexp still matched
for it in the scheduler files which is now removed.

Review: Ulrich Weigand
The file was modifiedllvm/lib/Target/SystemZ/SystemZScheduleZ196.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZScheduleZ15.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZScheduleZ13.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZScheduleZ14.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
Commit 1f9c29228cecfde9e993cd2818d9cd3119189163 by paul.robinson
[FastISel] NFC: Clean up unnecessary bookkeeping

Now that we flush the local value map for every instruction, we don't
need any extra flushes for specific cases.  Also, LastFlushPoint is
not used for anything.  Follow-ups to #c161665 (D91734).

This reapplies #3fd39d3.

Differential Revision: https://reviews.llvm.org/D92338
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was modifiedllvm/include/llvm/CodeGen/FastISel.h
Commit 072714b961980af720440bf286f7cc4a1746e929 by llvm-dev
[X86] Regenerate vector-constrained-fp-intrinsics.ll tests

Adding missing libcall PLT qualifier
The file was modifiedllvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
Commit 35c9baa11e4be6ae570674eec2de8bd928639b18 by Artem Dergachev
[attributes]  Add a facility for enforcing a Trusted Computing Base.

Introduce a function attribute 'enforce_tcb' that prevents the function
from calling other functions without the same attribute. This allows
isolating code that's considered to be somehow privileged so that it could not
use its privileges to exhibit arbitrary behavior.

Introduce an on-by-default warning '-Wtcb-enforcement' that warns
about violations of the above rule.

Introduce a function attribute 'enforce_tcb_leaf' that suppresses
the new warning within the function it is attached to. Such leaf functions
may implement common functionality between the trusted and the untrusted code
but they require extra careful audit with respect to their capabilities.

Fixes after a revert in 419ef38a50293c58078f830517f5e305068dbee6:
Fix a test.
Add workaround for GCC bug (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67274).
Attribute the patch appropriately!

Differential Revision: https://reviews.llvm.org/D91898
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/Misc/pragma-attribute-supported-attributes-list.test
The file was modifiedclang/include/clang/Basic/Attr.td
The file was addedclang/test/Sema/attr-enforce-tcb-errors.cpp
The file was addedclang/test/Sema/attr-enforce-tcb.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was addedclang/test/Sema/attr-enforce-tcb.c
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit a90214760d0414912953e77b5b314be2b8e7df77 by kparzysz
[Hexagon] Custom-widen SETCC's operands

The result cannot be widened, unfortunately, because widening vNi1
would depend on the context in which it appears (i.e. the type alone
is not sufficient to tell if it needs to be widened).
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.h
The file was addedllvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll
Commit bcec0f27a2c37b64d5e8b84bbbfa563edae6affe by Joseph.Nash
[AMDGPU] Deduplicate VOP tablegen asm & ins

VOP3 and VOP DPP subroutines to generate input
operands and asm strings were essentially copy
pasted several times. They are deduplicated to
reduce the maintenance burden and allow faster
development.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D94102

Change-Id: I76225eed3c33239d9573351e0c8a0abfad0146ea
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 74628c43053b482f35f0f1e6b4eac743fbe425e5 by zinenko
[mlir] Add Python bindings for AffineExpr

This adds the Python bindings for AffineExpr and a couple of utility functions
to the C API. AffineExpr is a top-level context-owned object and is modeled
similarly to attributes and types. It is required, e.g., to build layout maps
of the built-in memref type.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94225
The file was modifiedmlir/include/mlir-c/AffineExpr.h
The file was modifiedmlir/include/mlir-c/Bindings/Python/Interop.h
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/lib/CAPI/IR/AffineExpr.cpp
The file was addedmlir/test/Bindings/Python/ir_affine_expr.py
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
The file was modifiedmlir/lib/Bindings/Python/IRModules.h
Commit e79bd0b4f25e68130a2ac273d6508ea322028b61 by zinenko
[mlir] More Python bindings for AffineMap

Now that the bindings for AffineExpr have been added, add more bindings for
constructing and inspecting AffineMap that consists of AffineExprs.

Depends On D94225

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94297
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
The file was modifiedmlir/include/mlir-c/AffineExpr.h
The file was modifiedmlir/lib/CAPI/IR/AffineMap.cpp
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/test/Bindings/Python/ir_affine_map.py
The file was modifiedmlir/include/mlir-c/AffineMap.h
Commit 547e3eef14a8e75a867dfcc6b45cd1f0547d4e07 by zinenko
[mlir] Expose MemRef layout in Python bindings

This wasn't possible before because there was no support for affine expressions
as maps. Now that this support is available, provide the mechanism for
constructing maps with a layout and inspecting it.

Rework the `get` method on MemRefType in Python to avoid needing an explicit
memory space or layout map. Remove the `get_num_maps`, it is too low-level,
using the length of the now-avaiable pseudo-list of layout maps is more
pythonic.

Depends On D94297

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94302
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
The file was modifiedmlir/test/Bindings/Python/ir_types.py
The file was modifiedmlir/lib/CAPI/IR/BuiltinTypes.cpp
The file was modifiedmlir/include/mlir-c/BuiltinTypes.h
Commit 47567ca5faca147bcc28bcbbaa6bf448354bb5d4 by clementval
[flang][openxx][NFC] Remove duplicated function to check required clauses

Remove duplicated function to check for required clauses on a directive. This was
still there from the merging of OpenACC and OpenMP common semantic checks and it can now be
removed so we use only one function.

Reviewed By: sameeranjoshi

Differential Revision: https://reviews.llvm.org/D93575
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
The file was modifiedflang/lib/Semantics/check-directive-structure.h
The file was modifiedflang/test/Semantics/omp-device-constructs.f90
Commit d8c6d24359f17c55a8966231ef74e8f4b03ad282 by tmsriram
-funique-internal-linkage-names appends a hex md5hash suffix to the symbol name which is not demangler friendly, convert it to decimal.

Please see D93747 for more context which tries to make linkage names of internal
linkage functions to be the uniqueified names. This causes a problem with gdb
because breaking using the demangled function name will not work if the new
uniqueified name cannot be demangled. The problem is the generated suffix which
is a mix of integers and letters which do not demangle. The demangler accepts
either all numbers or all letters. This patch simply converts the hash to decimal.

There is no loss of uniqueness by doing this as the precision is maintained.
The symbol names get longer by a few characters though.

Differential Revision: https://reviews.llvm.org/D94154
The file was modifiedclang/test/CodeGen/unique-internal-linkage-names.cpp
The file was modifiedllvm/test/Transforms/UniqueInternalLinkageNames/unique_symbol_names.ll
The file was modifiedllvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
Commit 43a830ed94180f72533263bb1c40af29510c017a by schmeise
Introduce new quiet mode and new option handling for -print-changed.
Summary:
Introduce a new mode of operation for -print-changed that only reports
after a pass changes the IR with all of the other messages suppressed (ie,
no initial IR and no messages about ignored, filtered or non-modifying
passes).

The option processing for -print-changed is changed to take an optional
string indicating options for print-changed. Initially, the only option
supported is quiet (as described above). This new quiet mode is specified
with -print-changed=quiet while -print-changed will continue to function
in the same way. It is intended that there will be more options in the
future.

Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: aeubanks (Arthur Eubanks)
Differential Revision: https://reviews.llvm.org/D92589
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp
The file was modifiedllvm/include/llvm/Passes/StandardInstrumentations.h
The file was modifiedllvm/test/Other/change-printer.ll
Commit 5464baaae8c19997c5b0b76930d2b5ee13f68dfa by rnk
Fix minor build issue (NFC)

Change [x86] Fix tile register spill issue was causing problems for our build
using gcc-5.4.1

The problem was caused by this line:

for (const MachineInstr &MI : make_range(MIS.begin(), MI))

where MI was previously defined as a MachineBasicBlock iterator.

Differential Revision: https://reviews.llvm.org/D94415
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp
Commit 1027a22ccd72bb127253cf7d27f528712fa21fa0 by Abhina.Sreeskantharajan
[SystemZ][z/OS] Fix Permission denied pattern matching

On z/OS, the error message "EDC5111I Permission denied." is not matched correctly in lit tests. This patch updates the check expression to match successfully.

Reviewed By: fanbo-meng

Differential Revision: https://reviews.llvm.org/D94432
The file was modifiedllvm/test/tools/llvm-elfabi/fail-file-write.test
Commit 195728c75aa41d80254175c5d7ac2f881333b139 by csigg
[mlir] Add structural conversion to async dialect lowering.

Lowering of async dialect uses a fixed type converter and therefore does not support lowering non-standard types.

This revision adds a structural conversion so that non-standard types in `!async.value`s can be lowered to LLVM before lowering the async dialect itself.

Reviewed By: ezhulenev

Differential Revision: https://reviews.llvm.org/D94404
The file was modifiedmlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
The file was modifiedmlir/include/mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h
Commit 37b41bd0879e8ed1a07a6fc401a2b56dcd6f124c by fraser
[RISCV] Add scalable vector fcmp ISel patterns

Original patch by @rogfer01.

All ordered comparisons except ONE are supported natively, and all
unordered comparisons except UNE are expanded into sequences involving
explicit NaN checks and mask arithmetic.

Additionally, we expand GT,OGT,GE,OGE to their swapped-operand versions, and
pattern-match those back to the "original", swapping operands once more. This
way we catch both operations and both "vf" and "fv" forms with fewer patterns.

Also add support for floating-point splat_vector, with an optimization for
splatting fpimm0.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94242
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was addedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
Commit 30a7d430e869bb0d8c61ef9999a04f56e4dd2377 by marek.kurdej
[libc++] Turn off auto-formatting of generated files. NFC.

This adds `// clang-format off` in the auto-generated file to avoid lint warnings.

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D94410
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/numbers.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/type_traits.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/list.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/numeric.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/concepts.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/thread.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/unordered_map.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/bit.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/semaphore.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/variant.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/regex.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/vector.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/complex.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/algorithm.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/deque.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/string.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/scoped_allocator.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/span.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/memory.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/map.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/utility.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/barrier.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/optional.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/forward_list.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/mutex.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/iomanip.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/ostream.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/any.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/new.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/atomic.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/cmath.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/filesystem.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/limits.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/shared_mutex.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/exception.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/locale.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/execution.version.pass.cpp
The file was modifiedlibcxx/utils/generate_feature_test_macro_components.py
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/string_view.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/functional.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/array.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/latch.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/set.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/chrono.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/compare.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/istream.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/iterator.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/unordered_set.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/cstddef.version.pass.cpp
Commit 72f1f084670ed66362ecb7c4079ee372665ce842 by Tony.Tye
[NFC][AMDGPU] Clarify memory model support for volatile

Reorder the AMDGPUUage description of the memory model code sequences
for volatile so clear that it applies independent of the nontemporal
setting.

Differential Revision: https://reviews.llvm.org/D94358
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit 207417730134931c7d5bf82e0b16c7757ad05e05 by riddleriver
[mlir][ODS] Add a C++ abstraction for OpBuilders

This removes the need for OpDefinitionsGen to use raw tablegen API, and will also
simplify adding builders to TypeDefs as well.

Differential Revision: https://reviews.llvm.org/D94273
The file was modifiedmlir/include/mlir/TableGen/Operator.h
The file was modifiedmlir/lib/TableGen/CMakeLists.txt
The file was addedmlir/lib/TableGen/Builder.cpp
The file was addedmlir/include/mlir/TableGen/Builder.h
The file was modifiedmlir/lib/TableGen/Operator.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Commit 948be58258dd81d56b1057657193f7dcf6dfa9bd by riddleriver
[mlir][TypeDefGen] Add support for adding builders when generating a TypeDef

This allows for specifying additional get/getChecked methods that should be generated on the type, and acts similarly to how OpBuilders work. TypeBuilders have two additional components though:
* InferredContextParam
  - Bit indicating that the context parameter of a get method is inferred from one of the builder parameters
* checkedBody
  - A code block representing the body of the equivalent getChecked method.

Differential Revision: https://reviews.llvm.org/D94274
The file was modifiedmlir/lib/TableGen/TypeDef.cpp
The file was modifiedmlir/tools/mlir-tblgen/TypeDefGen.cpp
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/test/lib/Dialect/Test/TestTypes.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestTypeDefs.td
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/include/mlir/TableGen/TypeDef.h
The file was modifiedmlir/test/mlir-tblgen/typedefs.td
The file was modifiedmlir/include/mlir/Dialect/ArmSVE/ArmSVE.td
Commit d79642b3db1d74524f41d37f78385950158787a4 by riddleriver
[mlir][IR][NFC] Move the definitions of Complex/Function/Integer/Opaque/TupleType to ODS

The type tablegen backend now has enough support to represent these types well enough, so we can now move them to be declaratively defined.

Differential Revision: https://reviews.llvm.org/D94275
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/lib/IR/MLIRContext.cpp
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.h
The file was modifiedmlir/lib/IR/TypeDetail.h
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.td
Commit d3ff24cbf87224b23a0c99c74ed50744711909b2 by n.james93
[ADT] Add makeIntrusiveRefCnt helper function

Works like std::make_unique but for IntrusiveRefCntPtr objects.
See https://lists.llvm.org/pipermail/llvm-dev/2021-January/147729.html

Reviewed By: dblaikie, MaskRay

Differential Revision: https://reviews.llvm.org/D94440
The file was modifiedllvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp
The file was modifiedllvm/include/llvm/ADT/IntrusiveRefCntPtr.h
Commit 8ad998a6115a8cd59a18ebdd5ec65329e42050e7 by Abhina.Sreeskantharajan
[tools] Mark output of tools as text if it is really text

This is a continuation of https://reviews.llvm.org/D67696. The following tools also need to set the OF_Text flag correctly.

  -   llvm-profdata
  -   llvm-link

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D94313
The file was modifiedllvm/tools/llvm-link/llvm-link.cpp
The file was modifiedllvm/tools/llvm-profdata/llvm-profdata.cpp
The file was modifiedllvm/test/tools/llvm-profdata/csprof-dump.test
The file was modifiedllvm/test/tools/llvm-profdata/instr-remap.test
Commit 05e90cefeb4bc5613b2cadedc2b8e2ecb2ed20ed by mtrofin
[NFC] Disallow unused prefixes under llvm/test/CodeGen

This patch finishes addressing unused prefixes under CodeGen: 2
remaining tests fixed, and then undo-ing the lit.local.cfg changes under
various subdirs and moving the policy under CodeGen.

Differential Revision: https://reviews.llvm.org/D94430
The file was modifiedllvm/test/CodeGen/NVPTX/f16-instructions.ll
The file was modifiedllvm/test/CodeGen/PowerPC/lit.local.cfg
The file was modifiedllvm/test/CodeGen/AMDGPU/lit.local.cfg
The file was modifiedllvm/test/CodeGen/ARM/speculation-hardening-sls.ll
The file was modifiedllvm/test/CodeGen/X86/lit.local.cfg
The file was addedllvm/test/CodeGen/lit.local.cfg
Commit c1ae378205db72cd80a52b85b8474077d1aa5b15 by thomasraoux
[mlir][vector] Add side-effect information to different load/store ops

Differential Revision: https://reviews.llvm.org/D94434
The file was modifiedmlir/test/Dialect/Vector/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
Commit 53c866c286a7ca52bd09c7661d4c532ce5c0def8 by stellaraccident
Enable python bindings for tensor, shape and linalg dialects.

* We've got significant missing features in order to use most of these effectively (i.e. custom builders, region-based builders).
* We presently also lack a mechanism for actually registering these dialects but they can be use with contexts that allow unregistered dialects for further prototyping.

Differential Revision: https://reviews.llvm.org/D94368
The file was addedmlir/lib/Bindings/Python/ShapeOps.td
The file was modifiedmlir/cmake/modules/AddMLIRPythonExtension.cmake
The file was addedmlir/lib/Bindings/Python/LinalgOps.td
The file was addedmlir/lib/Bindings/Python/TensorOps.td
The file was modifiedmlir/test/Bindings/Python/CMakeLists.txt
The file was modifiedmlir/lib/Bindings/Python/CMakeLists.txt
Commit cceb1bfcbbc4ee2e9cc56b76a4acc4cd52968791 by stellaraccident
[mlir][CAPI] Introduce standard source layout for mlir-c dialect registration.

* Registers a small set of sample dialects.
* NFC with respect to existing C-API symbols but some headers have been moved down a level to the Dialect/ sub-directory.
* Adds an additional entry point per dialect that is needed for dynamic discovery/loading.
* See discussion: https://llvm.discourse.group/t/dialects-and-the-c-api/2306/16

Differential Revision: https://reviews.llvm.org/D94370
The file was addedmlir/include/mlir-c/Dialect/Tensor.h
The file was addedmlir/lib/CAPI/Dialect/CMakeLists.txt
The file was addedmlir/lib/CAPI/Dialect/Standard.cpp
The file was addedmlir/lib/CAPI/Dialect/Linalg.cpp
The file was addedmlir/lib/CAPI/Dialect/Shape.cpp
The file was addedmlir/lib/CAPI/Dialect/Tensor.cpp
The file was modifiedmlir/test/CAPI/ir.c
The file was addedmlir/include/mlir-c/Dialect/Linalg.h
The file was removedmlir/lib/CAPI/Standard/CMakeLists.txt
The file was addedmlir/include/mlir-c/Dialect/SCF.h
The file was addedmlir/include/mlir-c/Dialect/Shape.h
The file was addedmlir/include/mlir-c/Dialect/Standard.h
The file was modifiedmlir/lib/CAPI/CMakeLists.txt
The file was modifiedmlir/include/mlir-c/Registration.h
The file was removedmlir/include/mlir-c/StandardDialect.h
The file was removedmlir/lib/CAPI/Standard/StandardDialect.cpp
The file was addedmlir/include/mlir/CAPI/Registration.h
The file was addedmlir/lib/CAPI/Dialect/SCF.cpp
Commit 110775809ad114e190132290657a86b2c292a878 by joker.eph
Revert "[mlir][linalg] Support parsing attributes in named op spec"

This reverts commit df86f15f0c53c395dac5a14aba08745bc12b9b9b.

The gcc-5 build was broken by this change:

  mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp:1275:77:   required from here
  /usr/include/c++/5/ext/new_allocator.h:120:4: error: no matching function for call to 'std::pair<const std::__cxx11::basic_string<char>, {anonymous}::TCParser::RegisteredAttr>::pair(llvm::StringRef&, {anonymous}::TCParser::RegisteredAttr'
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
Commit 288f3fc5dfee0c51fc00fe10a985f93c505073eb by spatel
[InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test

This is a more basic pattern that we should handle before trying to solve:
https://llvm.org/PR48640

There might be a better way to think about this because the pre-condition
that I came up with (number of sign bits in the compare constant) misses a
potential transform for each of ugt and ult as commented on in the test file.

Tried to model this is in Alive:
https://rise4fun.com/Alive/juX1
...but I couldn't get the ComputeNumSignBits() pre-condition to work as
expected, so replaced with leading 0/1 preconditions instead.

  Name: ugt
  Pre: countLeadingZeros(C2) <= C1 && countLeadingOnes(C2) <= C1
  %a = ashr %x, C1
  %r = icmp ugt i8 %a, C2
    =>
  %r = icmp slt i8 %x, 0

  Name: ult
  Pre: countLeadingZeros(C2) <= C1 && countLeadingOnes(C2) <= C1
  %a = ashr %x, C1
  %r = icmp ult i4 %a, C2
    =>
  %r = icmp sgt i4 %x, -1

Also approximated in Alive2:
https://alive2.llvm.org/ce/z/u5hCcz
https://alive2.llvm.org/ce/z/__szVL

Differential Revision: https://reviews.llvm.org/D94014
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/Transforms/InstCombine/icmp-shr.ll
Commit 32c073acb320db3b22ca76b1e21dd688a70b50e8 by bjorn.a.pettersson
[GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT

Before this patch there was generic mapping from vector_extract
to G_EXTRACT_VECTOR_ELT added in SelectionDAGCompat.td. That
mapping is now replaced by a mapping from extractelt instead.

The reasoning is that vector_extract is marked as deprecated,
so it is assumed that a majority of targets will use extractelt
and not vector_extract (and that the long term solution for all
targets would be to use extractelt).

Targets like AArch64 that still use vector_extract can add an
additional mapping from the deprecated vector_extract as target
specific tablegen definitions. Such a mapping is added for AArch64
in this patch to avoid breaking tests.

When adding the extractelt => G_EXTRACT_VECTOR_ELT mapping we
triggered some new code paths in GlobalISelEmitter, ending up in
an assert when trying to import a pattern containing EXTRACT_SUBREG
for ARM. Therefore this patch also adds a "failedImport" warning
for that situation (instead of hitting the assert).

Differential Revision: https://reviews.llvm.org/D93416
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
Commit aefeb5f136e7b72b251ce2881cb39a1fe8f0d76a by sivachandra
[libc][NFC] Make __support/common.h an in tree header.

It was previously a generated header. It can easily converted to a
generated header if required in future.

Reviewed By: michaelrj

Differential Revision: https://reviews.llvm.org/D94445
The file was modifiedlibc/src/__support/CMakeLists.txt
The file was addedlibc/src/__support/common.h
The file was removedlibc/src/__support/common.h.def
Commit 9b222b108a2e37eb45d3156ec8554d148d658a8a by richard
[c++20] Don't consider string literal operator templates for numeric
literals.

A literal interpretation of the standard wording allows this, but it was
never intended that string literal operator templates would be used for
anything other than user-defined string literals.
The file was modifiedclang/lib/Sema/SemaLookup.cpp
The file was modifiedclang/test/SemaCXX/cxx2a-user-defined-literals.cpp
Commit f4cec703ec8452f9d8b04fae171ba459adf38123 by i
Add an assert to CGDebugInfo::getTypeOrNull
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
Commit 7989684a2e4a496201ff41d31cede764487ca80f by fraser
[RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns

Original patch by @rogfer01.

This patch adds ISel patterns for the above operations to the
corresponding vector/vector and vector/scalar RVV instructions, as well
as extra patterns to match operand-swapped scalar/vector vfrsub and
vfrdiv.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94408
The file was addedllvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll
Commit 046612d29d7894783e8fcecbc62ebd6b4a78499f by ajcbik
[mlir][vector] verify memref of vector memory ops

This ensures the memref base + indices expression is well-formed

Reviewed By: ThomasRaoux, ftynse

Differential Revision: https://reviews.llvm.org/D94441
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
Commit a808d89d355c98d7475795e13271beb90e9436cb by nikita.ppv
[PredicateInfo] Add test for one unknown condition in and/or (NFC)

Test the case where one part of and/or is an icmp, while the other
one is an arbitrary value.
The file was modifiedllvm/test/Transforms/Util/PredicateInfo/testandor.ll
Commit 00f773cf424699d8eb31591fdc95e0ca18b2682c by nikita.ppv
[SCCP] Fix misclassified conditions in test (NFC)
The file was modifiedllvm/test/Transforms/SCCP/conditions-ranges.ll
Commit b88c8f1aab527f1aebe612ab6c50a418bff88584 by i
CGDebugInfo: Delete unused parameters
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedclang/lib/CodeGen/CGDebugInfo.h
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
Commit 32bcfcda4e28375e5a85268d2acfabcfcc011abf by hoy
Rename debug linkage name with -funique-internal-linkage-names

Functions that are renamed under -funique-internal-linkage-names have their debug linkage name updated as well.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D93747
The file was modifiedllvm/include/llvm/IR/DebugInfoMetadata.h
The file was addedllvm/test/Transforms/UniqueInternalLinkageNames/unique-internal-linkage-names.ll
The file was removedllvm/test/Transforms/UniqueLinkageNames/unique-internal-linkage-names.ll
The file was modifiedllvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
Commit a81c68ae6be58efa24e2573e155d5ef20260399b by tianshilei1992
[OpenMP] Take elf_common.c as a interface library

For now `elf_common.c` is taken as a common part included into
different plugin implementations directly via
`#include "../../common/elf_common.c"`, which is not a best practice. Since it
is simple enough such that we don't need to create a real library for it, we just
take it as a interface library so that other targets can link it directly. Another
advantage of this method is, we don't need to add the folder into header search
path which can potentially pollute the search path.

VE and AMD platforms have not been tested because I don't have target machines.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D94443
The file was addedopenmp/libomptarget/plugins/common/elf_common/CMakeLists.txt
The file was modifiedopenmp/libomptarget/plugins/CMakeLists.txt
The file was modifiedopenmp/libomptarget/plugins/generic-elf-64bit/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/ve/CMakeLists.txt
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/cuda/src/rtl.cpp
The file was addedopenmp/libomptarget/plugins/common/elf_common/elf_common.h
The file was modifiedopenmp/libomptarget/plugins/ve/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/CMakeLists.txt
The file was removedopenmp/libomptarget/plugins/common/elf_common.c
The file was modifiedopenmp/libomptarget/plugins/cuda/CMakeLists.txt
The file was addedopenmp/libomptarget/plugins/common/CMakeLists.txt
Commit 9ecc991c559663bd4e3e06a18ba708e0e29c891b by fraser
[RISCV] Add scalable vector vselect ISel patterns

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94294
The file was addedllvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
Commit 0a23fbd28c7509f2f980946091e6055bf27164d2 by ndesaulniers
clang: Always pass PowerPC endian information to GNU as

When building a 64-bit big endian PowerPC Linux kernel with a 64-bit
little endian PowerPC target, the 32-bit vDSO errors:

```
$ make ARCH=powerpc CC=clang CROSS_COMPILE=powerpc64le-linux-gnu- \
       pseries_defconfig arch/powerpc/kernel/vdso32/
ld.lld: error: arch/powerpc/kernel/vdso32/sigtramp.o is incompatible with elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/gettimeofday.o is incompatible with elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/datapage.o is incompatible with elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/cacheflush.o is incompatible with elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/note.o is incompatible with elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/getcpu.o is incompatible with elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/vgettimeofday.o is incompatible with elf32-powerpc
...
```

This happens because the endian information is missing from the call to
the assembler, even though it was explicitly passed to clang. See the
below example.

```
$ echo | clang --target=powerpc64le-linux-gnu \
               --prefix=/usr/bin/powerpc64le-linux-gnu- \
               -no-integrated-as -m32 -mbig-endian -### -x c -c -
".../clang-12" "-cc1" "-triple" "powerpc-unknown-linux-gnu" ...
...
  "/usr/bin/powerpc64le-linux-gnu-as" "-a32" "-mppc" "-many" "-o" "-.o" "/tmp/--e69e28.s"
```

clang sets the right target with -m32 and -mbig-endian but -mbig-endian
does not make it to the assembler, resulting in a 32-bit little endian
binary. This differs from the little endian targets, which always pass
-mlittle-endian.

```
$ echo | clang --target=powerpc64-linux-gnu \
               --prefix=/usr/bin/powerpc64-linux-gnu- \
               -no-integrated-as -m32 -mlittle-endian -### -x c -c -
".../clang-12" "-cc1" "-triple" "powerpcle-unknown-linux-gnu" ...
...
"/usr/bin/powerpc64-linux-gnu-as" "-a32" "-mppc" "-mlittle-endian" "-many" "-o" "-.o" "/tmp/--405dbd.s"
```

Do the same thing for the big endian targets so that there is no more
error. This matches GCC's behavior, where -mbig and -mlittle are always
passed along to GNU as.

```
$ echo | powerpc64-linux-gcc -### -x c -c -
...
.../powerpc64-linux/bin/as -a64 -mpower4 -many -mbig -o -.o /tmp/ccVn7NAm.s
...

$ echo | powerpc64le-linux-gcc -### -x c -c -
...
.../powerpc64le-linux/bin/as -a64 -mpower8 -many -mlittle -o -.o /tmp/ccPN9ato.s
...
```

Reviewed By: nickdesaulniers, MaskRay

Differential Revision: https://reviews.llvm.org/D94442
The file was modifiedclang/test/Driver/ppc-features.cpp
The file was modifiedclang/lib/Driver/ToolChains/Gnu.cpp
Commit 762ffc95550c32606e771b630fcab2e521873419 by joker.eph
Update syntax for tensor and memref types to match parser.

Based on the comments in lib/Parser/TypeParser.cpp on the
parseMemRefType and parseTensorType functions.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94262
The file was modifiedmlir/lib/Parser/TypeParser.cpp
The file was modifiedmlir/docs/LangRef.md
Commit 278a3ea1b27089dbc7060e02f612c8a3bf137bb2 by craig.topper
[RISCV] Use vmv.v.i vd, 0 instead of vmv.v.x vd, x0 for llvm.riscv.vfmv.v.f with 0.0

This matches what we use for integer 0. It's also consistent with
the scalar 'mv' pseudo that uses addi rather than add with x0.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit c22bc5f1f8b295674aa3a62dced8a39ad3d2aa02 by lebedev.ri
[SimplifyCFG] SwitchToLookupTable(): don't insert a DomTree edge that already exists

SI is the terminator of BB, so the edge we are adding obviously already existed.

Indeed, this change does not have a test coverage change.
This failure has been exposed in an existing test coverage
by a follow-up patch that switches to lazy domtreeupdater mode,
and removes domtree verification from
SimplifyCFGOpt::simplifyOnce()/SimplifyCFGOpt::run(),
IOW it does not appear feasible to add dedicated test coverage here.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit c0de0a1b72c08783141c430b583e04e5107ebc0a by lebedev.ri
[SimplifyCFG] SimplifyBranchOnICmpChain(): don't insert a DomTree edge that already exists

BB was already always branching to EdgeBB, there is no edge to add.

Indeed, this change does not have a test coverage change.
This failure has been exposed in an existing test coverage
by a follow-up patch that switches to lazy domtreeupdater mode,
and removes domtree verification from
SimplifyCFGOpt::simplifyOnce()/SimplifyCFGOpt::run(),
IOW it does not appear feasible to add dedicated test coverage here.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit f9ba34770638389ee9b251f6ab801c7411601c77 by lebedev.ri
[SimplifyCFG] FoldValueComparisonIntoPredecessors(): don't insert a DomTree edge if it already exists

When we are adding edges to the terminator and potentially turning it
into a switch (if it wasn't already), it is possible that the
case we're adding will share it's destination with one of the
preexisting cases, in which case there is no domtree edge to add.

Indeed, this change does not have a test coverage change.
This failure has been exposed in an existing test coverage
by a follow-up patch that switches to lazy domtreeupdater mode,
and removes domtree verification from
SimplifyCFGOpt::simplifyOnce()/SimplifyCFGOpt::run(),
IOW it does not appear feasible to add dedicated test coverage here.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit 90a92f8b4d783cb08443a22f0dd2fa3adcb43807 by lebedev.ri
[NFCI][Utils/Local] removeUnreachableBlocks(): cleanup support for lazy DomTreeUpdater

When DomTreeUpdater is in lazy update mode, the blocks
that were scheduled to be removed, won't be removed
until the updates are flushed, e.g. by asking
DomTreeUpdater for a up-to-date DomTree.

From the function's current code, it is pretty evident
that the support for the lazy mode is an afterthought,
see e.g. how we roll-back NumRemoved statistic..

So instead of considering all the unreachable blocks
as the blocks-to-be-removed, simply additionally skip
all the blocks that are already scheduled to be removed
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 81afeacd379f160495718438d6dd5e9b848a169d by lebedev.ri
[SimplifyCFGPass] mergeEmptyReturnBlocks(): skip blocks scheduled for removal as per DomTreeUpdater

Thus supporting lazy DomTreeUpdater mode,
where the domtree updates (and thus block removals)
aren't applied immediately, but are delayed
until last possible moment.
The file was modifiedllvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
Commit ec8a6c11db4102ec249ce90084b3f615c5de15e5 by lebedev.ri
[SimplifyCFGPass] iterativelySimplifyCFG(): support lazy DomTreeUpdater

This boils down to how we deal with early-increment iterator
over function's basic blocks: not only we need to early-increment,
after that we also need to skip all the blocks
that are scheduled for removal, as per DomTreeUpdater.
The file was modifiedllvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
Commit 5ccff5aaa68ab789834c4463ce05b05e57593b34 by Duncan P. N. Exon Smith
ADT: Fix pointer comparison UB in SmallVector

The standard requires comparisons of pointers to unrelated storage to
use `std::less`. Split out some helpers that do that and update all the
code that was comparing using `<` and friends (mostly assertions).

Differential Revision: https://reviews.llvm.org/D93777
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
Commit 7470017f2472411e8e03151b5016d612ac6648dd by evandro.menezes
[RISCV] Define the vfclass RVV intrinsics

Define the `vfclass` IR intrinsics for the respective V instructions.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Evandro Menezes <evandro.menezes@sifive.com>

Differential Revision: https://reviews.llvm.org/D94356
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll
Commit f635bcd16105a0a01eefa2c69a71cd103dedaddd by hubert.reinterpretcast
NFC: Pre-commit test: -Wpointer-sign with plain char to [un]signed char

Add tests with bad message text for `-Wpointer-sign` and run them with
both signed and unsigned versions of plain `char`.
The file was addedclang/test/Sema/incompatible-sign.cpp
The file was modifiedclang/test/Sema/incompatible-sign.c
Commit c6ffe4d76fbf6ae505c0abccaf29017414265e32 by hubert.reinterpretcast
[clang] Fix message text for `-Wpointer-sign` to account for plain char

The `-Wpointer-sign` warning text is inappropriate for describing the
incompatible pointer conversion between plain `char` and explicitly
`signed`/`unsigned` `char` (whichever plain `char` has the same range
as) and vice versa.

Specifically, in part, it reads "converts between pointers to integer
types with different sign". This patch changes that portion to read
instead as "converts between pointers to integer types where one is of
the unique plain 'char' type and the other is not" when one of the types
is plain `char`.

C17 subclause 6.5.16.1 indicates that the conversions resulting in
`-Wpointer-sign` warnings in assignment-like contexts are constraint
violations. This means that strict conformance requires a diagnostic for
the case where the message text is wrong before this patch. The lack of
an even more specialized warning group is consistent with GCC.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D93999
The file was modifiedclang/test/Sema/incompatible-sign.c
The file was modifiedclang/test/SemaObjC/objc-cf-audited-warning.m
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/Sema/incompatible-sign.cpp
Commit eefd420e0037f8fb53a07c96855985bab61bd1e9 by tstellar
[github] Move repo lockdown config into llvm-project repo

We were storing this in the .github repo and moving this into llvm-project
will allow us to delete the .github repo.
The file was added.github/lockdown.yml
Commit f75f391fc68c125f908292bd7dcd6a413cfa591b by rob.suderman
[MLIR][Linalg] Refactor transforms to use linalg::getDynOperands helper

getDynOperands behavior is commonly used in a number of passes. Refactored to
use a helper function and avoid code reuse.

Differential Revision: https://reviews.llvm.org/D94340
The file was modifiedmlir/lib/Dialect/StandardOps/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp
The file was modifiedmlir/lib/Transforms/BufferDeallocation.cpp
The file was modifiedmlir/lib/Transforms/PipelineDataTransfer.cpp
The file was addedmlir/include/mlir/Dialect/StandardOps/Utils/Utils.h
The file was addedmlir/lib/Dialect/StandardOps/Utils/Utils.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/ElementwiseToLinalg.cpp
Commit f9902514fe548346a5175a3521c61fc4819c5b8a by Jonas Devlieghere
[MC] Make getEHFrameSection const like every other getter (NFC)
The file was modifiedllvm/include/llvm/MC/MCObjectFileInfo.h
Commit ef50c07b1fad368f6a8d326b4f73dd531009dca4 by Lang Hames
[JITLink] Add a new PostAllocationPasses list.

Passes in the new PostAllocationPasses list will run immediately after memory
allocation and address assignment for defined symbols, and before
JITLinkContext::notifyResolved is called. These passes can set up state
associated with the addresses of defined symbols before any query for these
addresses completes.
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp
Commit 70474dfebcd9babf2e3af5fb002b40417fd6cf88 by marukawa
[VE][compiler-rt] Add VE as a target of crt

SX Aurora VE is an experimental target.  We upstreamed many part of
ported llvm and clang.  In order to continue this move, we need to
support libraries next, then we need to show the ability of llvm for
VE through test cases.  As a first step for that, we need to use
crt in compiler-rt.  VE has it's own crt but they are a part of
proprietary compiler.  So, we want to use crt in compiler-rt as an
alternative.

This patch enables VE as a candidate of crt in compiler-rt.

Reviewed By: phosek, compnerd

Differential Revision: https://reviews.llvm.org/D92748
The file was modifiedcompiler-rt/cmake/config-ix.cmake
Commit 9f8b25769efa409ffc3b85f1c8043d2fcb4f185e by aheejin
[WebAssembly] Ensure terminate pads are a single BB

This ensures every single terminate pad is a single BB in the form of:
```
%exn = catch $__cpp_exception
call @__clang_call_terminate(%exn)
unreachable
```

This is a preparation for HandleEHTerminatePads pass, which will be
added in a later CL and will run after CFGStackify. That pass duplicates
terminate pads with a `catch_all` instruction, and duplicating it
becomes simpler if we can ensure every terminate pad is a single BB.

Reviewed By: dschuff, tlively

Differential Revision: https://reviews.llvm.org/D94045
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/exception.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyUtilities.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
Commit 905623b64df0c865d4dddc4a60aff9751fbaa0e0 by qcolombet
[NFC][LICM] Minor improvements to debug output

Added a utility function in Value class to print block name and use
block labels for unnamed blocks.
Changed LICM to call this function in its debug output.

Patch by Xiaoqing Wu <xiaoqing_wu@apple.com>

Differential Revision: https://reviews.llvm.org/D93577
The file was modifiedllvm/lib/IR/Value.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LICM.cpp
The file was modifiedllvm/include/llvm/IR/Value.h
Commit 0871d6d51648dd2a8009ddff59936ea9e3fe871b by tianshilei1992
[OpenMP] Move memory manager to plugin and make it a common interface

The lifetime of `libomptarget` and its opened plugins are not aligned
and it's hard for `libomptarget` to determine when the plugins are destroyed.
As a result, some issues (see D94256 for details) occur on some platforms.
Actually, if we take target memory as target resources, same as other resources,
such as CUDA streams, in each plugin, then the memory manager should also be in
the plugin. Also considering some platforms may want to opt out the feature, it
makes sense to move the memory manager to plugin, make it a common interface, and
let plguin developers determine whether they need it. This is what this patch does.
CUDA plugin is taken as example to show how to integrate it. In this way, we can
also get a bonus that different thresholds can be set for different platforms.

Reviewed By: jdoerfert, JonChesterfield

Differential Revision: https://reviews.llvm.org/D94379
The file was modifiedopenmp/libomptarget/plugins/common/CMakeLists.txt
The file was addedopenmp/libomptarget/plugins/common/MemoryManager/CMakeLists.txt
The file was addedopenmp/libomptarget/plugins/common/MemoryManager/MemoryManager.h
The file was modifiedopenmp/libomptarget/plugins/cuda/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/cuda/CMakeLists.txt
The file was modifiedopenmp/libomptarget/src/CMakeLists.txt
The file was removedopenmp/libomptarget/src/MemoryManager.cpp
The file was modifiedopenmp/libomptarget/src/device.cpp
The file was modifiedopenmp/libomptarget/src/device.h
The file was removedopenmp/libomptarget/src/MemoryManager.h
Commit 89e8eb946d89f29cc76ba0a03425b7f7679aca5d by kazu
[llvm] Use llvm::find_if (NFC)
The file was modifiedllvm/lib/MC/MCSectionMachO.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/Analysis.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp
The file was modifiedllvm/tools/obj2yaml/dwarf2yaml.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp
The file was modifiedllvm/include/llvm/Analysis/LoopCacheAnalysis.h
The file was modifiedllvm/lib/IR/LegacyPassManager.cpp
Commit 8590a3e3adceff1ff1f606fa68ce4622181ecae2 by kazu
[llvm] Use *Set::contains (NFC)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
The file was modifiedllvm/tools/llvm-objcopy/MachO/MachOObjcopy.cpp
The file was modifiedllvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
The file was modifiedllvm/tools/llvm-objcopy/COFF/Object.cpp
Commit e5b4dbab041f6692b8c5286406e2566be87feac9 by kazu
[llvm] Simplify string comparisons (NFC)

Identified with readability-string-compare.
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/tools/llvm-mca/llvm-mca.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/tools/llvm-profdata/llvm-profdata.cpp
The file was modifiedllvm/lib/Option/OptTable.cpp
Commit b1c304c4946506c0d00532829fb2f91276dde0c8 by craig.topper
[CodeGen] Try to make the print of memory operand alignment a little more user friendly.

Memory operands store a base alignment that does not factor in
the effect of the offset on the alignment.

Previously the printing code only printed the base alignment if
it was different than the size. If there is an offset, the reader
would need to figure out the effective alignment themselves. This
has confused me before and someone else was recently confused on
IRC.

This patch prints the possibly offset adjusted alignment if it is
different than the size. And prints the base alignment if it is
different than the alignment. The MIR parser has been updated to
read basealign in addition to align.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D94344
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/memory-operands.mir
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
The file was modifiedllvm/test/CodeGen/X86/avoid-sfb-offset.mir
The file was modifiedllvm/test/CodeGen/X86/bug47278.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.h
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix-cc-abi.ll
The file was modifiedllvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
Commit edde2eb1d2093905a2cb6166e6a60f9cc04c2bbc by Jason Molenda
Add unconditional logging to debugserver for launch/attach processes

Debugging app launch/attach failures can be difficult because of
all of the messages logged to the console on a darwin system;
emitting specific messages around critical API calls can make it
easier to narrow the search for the console messages related to
the failure.

<rdar://problem/67220442>

Differential revision: https://reviews.llvm.org/D94357
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachTask.mm
The file was modifiedlldb/tools/debugserver/source/RNBRemote.cpp
The file was modifiedlldb/tools/debugserver/source/debugserver.cpp
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachProcess.mm
Commit f9ef3a60037bffef6bbd2227b24e5cdb322d5eb2 by craig.topper
[SelectionDAG] Make isConstantIntBuildVectorOrConstantInt and isConstantFPBuildVectorOrConstantFP methods const.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAG.h
Commit b688c5875d08c586f7b35b8f9da1493ebbf92b45 by phosek
[CMake] Split the target side of runtimes build

Previously, llvm/runtimes/CMakeLists.txt played two different roles:
1. host side which could used  to set up the build of runtimes for
   different targets in the right order;
2. target side to build the runtimes for the specified target.

This change splits llvm/runtimes/CMakeLists.txt and moves the target
side to runtimes/CMakeLists laying down the foundation for the "A vision
for building the runtimes" proposal. From the user perspective, there
shouldn't be any visible difference at the moment.

Differential Revision: https://reviews.llvm.org/D93408
The file was addedruntimes/CMakeLists.txt
The file was removedllvm/runtimes/Components.cmake.in
The file was addedruntimes/Components.cmake.in
The file was modifiedllvm/runtimes/CMakeLists.txt
Commit df74c001fa5bd4874d0d88724e6cf726ed552904 by craig.topper
[DAGCombiner] Replace static helper function isConstantFPBuildVectorOrConstantFP with the identical version in SelectionDAG. NFC
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 93ad0edf674125f19177054d8331a5e8910d3d98 by i
[ELF] Drop .rel[a].debug_gnu_pub{names,types} for --gdb-index --emit-relocs

Fixes PR48693: --emit-relocs keeps relocation sections. --gdb-index drops
.debug_gnu_pubnames and .debug_gnu_pubtypes but not their relocation sections.
This can cause a null pointer dereference in `getOutputSectionName`.

Also delete debug-gnu-pubnames.s which is covered by gdb-index.s

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D94354
The file was modifiedlld/test/ELF/gdb-index.s
The file was modifiedlld/ELF/SyntheticSections.cpp
The file was removedlld/test/ELF/debug-gnu-pubnames.s
Commit 1cc5235712f2ed847f0b593714446d440e0596ba by aheejin
[WebAssembly] Misc. refactoring in CFGStackify (NFC)

Updating `ScopeTops` is something we frequently do in CFGStackify, so
this factors it out as a function. This also makes a few utility
functions templated so that they are not dependent on input vector
types and simplifies function parameters.

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D94046
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
Commit 215ed9b33ccbe9858aeb65b357bd1111cff354be by sbergman
Adapt CastExpr::getSubExprAsWritten to ConstantExpr

Differential Revision: https://reviews.llvm.org/D87030
The file was modifiedclang/lib/AST/Expr.cpp
The file was modifiedclang/unittests/Tooling/CastExprTest.cpp
Commit c8a914db5c60dbeb5b638f30a9915855a67805f7 by sander.desmalen
[LiveDebugValues] Fix comparison operator in VarLocBasedImpl

The issue was introduced in commit rG84a1120943a651184bae507fed5d648fee381ae4
and would cause a VarLoc's StackOffset to be compared with its own, instead of
the StackOffset from the other VarLoc. This patch fixes that.
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
Commit 6a195491b6028185c7278718ac21bca309a6c4ea by sebastian.neubauer
[AMDGPU] Fix failing assert with scratch ST mode

In ST mode, flat scratch instructions have neither an sgpr nor a vgpr
for the address. This lead to an assertion when inserting hard clauses.

Differential Revision: https://reviews.llvm.org/D94406
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/memory_clause.ll
Commit 7ab803095ae58445996dc4694acb216e3a32ee64 by Jan Svoboda
[clang][cli] Remove -f[no-]trapping-math from -cc1 command line

This patch removes the -f[no-]trapping-math flags from the -cc1 command line. These flags are ignored in the command line parser and their semantics is fully handled by -ffp-exception-mode.

This patch does not remove -f[no-]trapping-math from the driver command line. The driver flags are being used and do affect compilation.

Reviewed By: dexonsmith, SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D93395
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Parser/fp-floatcontrol-syntax.cpp
The file was modifiedclang/test/CodeGen/fpconstrained.c
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/test/CodeGen/noexceptionsfpmath.c
The file was modifiedclang/test/CodeGen/fpconstrained.cpp
The file was modifiedclang/test/CodeGenCUDA/propagate-metadata.cu
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/Driver/fast-math.c
The file was modifiedclang/test/Driver/fp-model.c
Commit bd30a796fc4b51750248ccba29cd6fb1f61859f5 by zinenko
[mlir] use built-in vector types instead of LLVM dialect types when possible

Continue the convergence between LLVM dialect and built-in types by using the
built-in vector type whenever possible, that is for fixed vectors of built-in
integers and built-in floats. LLVM dialect vector type is still in use for
pointers, less frequent floating point types that do not have a built-in
equivalent, and scalable vectors. However, the top-level `LLVMVectorType` class
has been removed in favor of free functions capable of inspecting both built-in
and LLVM dialect vector types: `LLVM::getVectorElementType`,
`LLVM::getNumVectorElements` and `LLVM::getFixedVectorType`. Additional work is
necessary to design an implemented the extensions to built-in types so as to
remove the `LLVMFixedVectorType` entirely.

Note that the default output format for the built-in vectors does not have
whitespace around the `x` separator, e.g., `vector<4xf32>` as opposed to the
LLVM dialect vector type format that does, e.g., `!llvm.vec<4 x fp128>`. This
required changing the FileCheck patterns in several tests.

Reviewed By: mehdi_amini, silvas

Differential Revision: https://reviews.llvm.org/D94405
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/memory-ops-to-llvm.mlir
The file was modifiedmlir/test/Conversion/VectorToROCDL/vector-to-rocdl.mlir
The file was modifiedmlir/lib/Conversion/VectorToROCDL/VectorToROCDL.cpp
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/shift-ops-to-llvm.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/roundtrip.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
The file was modifiedmlir/test/Target/arm-neon.mlir
The file was modifiedmlir/test/Conversion/StandardToLLVM/convert-to-llvmir.mlir
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/bitwise-ops-to-llvm.mlir
The file was modifiedmlir/test/Target/llvmir-types.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
The file was modifiedmlir/test/Target/llvmir.mlir
The file was modifiedmlir/test/Target/llvmir-intrinsics.mlir
The file was modifiedmlir/test/Conversion/ArmNeonToLLVM/convert-to-llvm.mlir
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/constant-op-to-llvm.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/dialect-cast.mlir
The file was modifiedmlir/docs/Dialects/LLVM.md
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/cast-ops-to-llvm.mlir
The file was modifiedmlir/test/Target/rocdl.mlir
The file was modifiedmlir/test/Target/import.ll
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/types-invalid.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/nvvm.mlir
The file was modifiedmlir/test/Conversion/StandardToLLVM/standard-to-llvm.mlir
The file was modifiedmlir/lib/Target/LLVMIR/TypeTranslation.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/types.mlir
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/integration_test/Dialect/LLVMIR/CPU/test-vector-reductions-int.mlir
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
The file was modifiedmlir/integration_test/Dialect/LLVMIR/CPU/test-vector-reductions-fp.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/rocdl.mlir
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-reduction-to-llvm.mlir
The file was modifiedmlir/test/Target/avx512.mlir
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/comparison-ops-to-llvm.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/invalid.mlir
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/spirv-types-to-llvm.mlir
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-mask-to-llvm.mlir
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/misc-ops-to-llvm.mlir
The file was modifiedmlir/test/Target/arm-sve.mlir
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/logical-ops-to-llvm.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
The file was modifiedmlir/docs/SPIRVToLLVMDialectConversion.md
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
The file was modifiedmlir/docs/ConversionToLLVMDialect.md
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/glsl-ops-to-llvm.mlir
The file was modifiedmlir/test/Target/nvvmir.mlir
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/func-ops-to-llvm.mlir
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
Commit e8287cb2b2923af9da72fd953e2ec5495c33861a by mkazantsev
[Test] Add failing test for PR48725
The file was addedllvm/test/Transforms/LoopStrengthReduce/pr48725.ll
Commit c93b95593907c28cbcfde3d8266801587e110b42 by aheejin
[WebAssembly] Remove more unnecessary brs in CFGStackify

After placing markers, we removed some unnecessary branches, but it only
handled the simplest case. This makes more unnecessary branches to be
removed.

Reviewed By: dschuff, tlively

Differential Revision: https://reviews.llvm.org/D94047
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
Commit 9ec72cfc61ad5d87bb9e719b8b01f56e4da88a5b by grimar
[llvm-readef/obj] - Change the design structure of ELF dumper. NFCI.

This is a refactoring for design of stuff in `ELFDumper.cpp`.
The current design of ELF dumper is far from ideal.

Currently most overridden functions (inherited from `ObjDumper`) in `ELFDumper` just forward to
the functions of `ELFDumperStyle` (which can be either `GNUStyle` or `LLVMStyle`).
A concrete implementation may be in any of `ELFDumper`/`DumperStyle`/`GNUStyle`/`LLVMStyle`.

This patch reorganizes the classes by introducing `GNUStyleELFDumper`/`LLVMStyleELFDumper`
which inherit from `ELFDumper`. The implementations are moved:

`DumperStyle` -> `ELFDumper`
`GNUStyle` -> `GNUStyleELFDumper`
`LLVMStyle` -> `LLVMStyleELFDumper`

With that we can avoid having a lot of redirection calls and helper methods.
The number of code lines changes from 7142 to 6922 (reduced by ~3%) and the
code overall looks cleaner.

Differential revision: https://reviews.llvm.org/D93900
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 1e11402aa8e25d88c095a1c70fc87d2d9775186b by grimar
[llvm-readobj] - Add 'override' to fix build bots.

This should fix bots after landing D93900.

An example of error is:

/home/worker/2.0.1/lldb-x86_64-debian/llvm-project/llvm/tools/llvm-readobj/ELFDumper.cpp:883:8: warning: 'printSectionMapping' overrides a member function but is not marked 'override' [-Winconsistent-missing-override]
  void printSectionMapping() {}
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit cc91efdabee05f749cb42e45aef1b45431844ade by grimar
[llvm-readobj] - An attempt to fix BB.

This adds the `template` keyword for 'getAsArrayRef' calls.

An example of error:
/b/1/openmp-gcc-x86_64-linux-debian/llvm.src/llvm/tools/llvm-readobj/ELFDumper.cpp:4491:50: error: use 'template' keyword to treat 'getAsArrayRef' as a dependent template name
    for (const Elf_Rel &Rel : this->DynRelRegion.getAsArrayRef<Elf_Rel>())
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 4744478b99f1a99b2cdf7e4070a93086e5ae4800 by SourabhSingh.Tomar
[mlir][openmp][NFCI] Rename `continuationIP` to `continuationBlock`

Argument is a `Block` not a `point`.
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
Commit 891b4873c129e27755e90a9b8954b9f0d0e7c5a4 by grimar
[llvm-readobj] - One more attempt to fix BB.

Add `this->` for `W`, which is the member of `ObjDumper`

An example of error:
readobj/ELFDumper.cpp:738:13: error: use of undeclared identifier 'W'
    assert(&W.getOStream() == &llvm::fouts());
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit c1e08f0073e35cf17c0a0343cf7efff914dbd66d by mikhail.maltsev
[clang][AST] Get rid of an alignment hack in DeclObjC.h [NFCI]

This code currently uses a union object to increase the
alignment of the type ObjCTypeParamList. The original intent of this
trick was to be able to use the expression `this + 1` to access the
beginning of a tail-allocated array of `ObjCTypeParamDecl *` pointers.

The code has since been refactored and uses `llvm::TrailingObjects` to
manage the tail-allocated array. This template takes care of
alignment, so the hack is no longer necessary.

This patch removes the union so that the `SourceRange` class can be
used directly instead of being re-implemented with raw representations
of source locations.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D94224
The file was modifiedclang/include/clang/AST/DeclObjC.h
The file was modifiedclang/lib/AST/DeclObjC.cpp
Commit f264f9ad7df538357dfc8c5f318c5c8b0df3d99f by jay.foad
[SlotIndexes] Fix and simplify basic block splitting

Remove the InsertionPoint argument from SlotIndexes::insertMBBInMaps
because it was confusing: what does it mean to insert a new block
between two instructions, in the middle of an existing block?

Instead, support the case that MachineBasicBlock::splitAt really needs,
where the new block contains some instructions that are already in the
maps because they have been moved there from the tail of the previous
block.

In all other use cases the new block is empty.

Based on work by Carl Ritson!

Differential Revision: https://reviews.llvm.org/D94311
The file was modifiedllvm/unittests/MI/LiveIntervalTest.cpp
The file was modifiedllvm/include/llvm/CodeGen/SlotIndexes.h
The file was modifiedllvm/lib/CodeGen/MachineBasicBlock.cpp
The file was modifiedllvm/include/llvm/CodeGen/LiveIntervals.h
Commit 794e3d94d5a97e118bc2ed10f7ba1830dbb25459 by jay.foad
[AMDGPU][GlobalISel] Remove some duplicate RUN lines

Differential Revision: https://reviews.llvm.org/D86618
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
Commit 60df7c08b1f4447309c0c07fec1c8bc7267562fc by grimar
[obj2yaml,yaml2obj] - Fix issues with creating/dumping group sections.

We have the following issues related to group sections:
1) yaml2obj is unable to set the custom `sh_entsize` value, because the `EntSize`
   key is currently ignored.
2) obj2yaml is unable to dump the group section which `sh_entsize != 4`.
3) obj2yaml always dumps the "EntSize" for group sections, though
   usually we are trying to omit dumping default values when dumping keys.
   I.e. we should not print the "EntSize" key when `sh_entsize` == 4.

This patch fixes (1),(3) and adds the test case to document the behavior of (2).

Differential revision: https://reviews.llvm.org/D93854
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
The file was modifiedllvm/test/tools/obj2yaml/ELF/section-group.yaml
The file was modifiedllvm/test/tools/yaml2obj/ELF/group.yaml
Commit c15a57cc1a86bfb72f4fa0e7d265494babc3b412 by grimar
[obj2yaml] - Don't crash when an object has an empty symbol table.

Currently we crash when we have an object with SHT_SYMTAB/SHT_DYNSYM sections
of size 0.

With this patch instead of the crash we start to dump them properly.

Differential revision: https://reviews.llvm.org/D93697
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
The file was modifiedllvm/test/tools/obj2yaml/ELF/no-symtab.yaml
Commit a06aa1037c17dd3d60f5202b9877d8988e463353 by thakis
Revert "[Test] Add failing test for PR48725"

This reverts commit e8287cb2b2923af9da72fd953e2ec5495c33861a.
Test unexpectedly passes on mac, see comment 2 on PR48725.
The file was removedllvm/test/Transforms/LoopStrengthReduce/pr48725.ll
Commit ace516fb33d1f3de85f046e96efc1048b4ee8c08 by csigg
Change the LLVM_ATTRIBUTE_DEPRECATED macro to use C++14 attribute.

C++14 attributes are superior because they can be applied to functions with inline definition and the syntax is cleaner.

I intend to convert all uses and then remove the macro.

One issue that might hold back switching uses to C++14  attributes is that
clang-format does not put long attributes on separate lines and formatted code will look like:

```
template <typename T>
[[deprecated("blah blah")]] void
    foooooooooooooooooooooooooooo() {
  ...
}
```

Putting long attributes on a separate line would be prettier.
See https://stackoverflow.com/questions/45740466/clang-format-setting-to-control-c-attributes

AttributeMacros probably won't help because it can't match the custom message.
https://clang.llvm.org/docs/ClangFormatStyleOptions.html

Reviewed By: rriddle, MaskRay

Differential Revision: https://reviews.llvm.org/D94219
The file was modifiedllvm/include/llvm/Support/Compiler.h
Commit 09db958e37b3a51942827a48a4b2f453e8fb4737 by fraser
[RISCV] Improve scalable-vector shift tests (NFC)

All i8/i16 and several i32 tests were testing immediate shift amounts
which exceeded the bits in the vector elements, creating poison values.
Amend the tests to test well-behaved shift amounts.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
Commit a5212b5c91cc699052125b8a3428ffe0c123837d by llvm-dev
[X86][SSE] combineSubToSubus - remove SSE2 early-out.

SSE2 truncation codegen has improved over the past few years (mainly due to better shuffle lowering/combining and computeKnownBits) - its no longer necessary to early-out from v8i32/v8i64 truncations.

This was noticed while looking at completing PR40111 and moving combineSubToSubus to DAGCombine entirely.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
Commit c4944a6f53f6d1876e76563599f5f149328e7f8f by bjorn.a.pettersson
[Fixed Point] Add codegen for conversion between fixed-point and floating point.

The patch adds the required methods to FixedPointBuilder
for converting between fixed-point and floating point,
and uses them from Clang.

This depends on D54749.

Reviewed By: leonardchan

Differential Revision: https://reviews.llvm.org/D86632
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was modifiedclang/test/Frontend/fixed_point_conversions.c
The file was addedclang/test/Frontend/fixed_point_conversions_half.c
The file was modifiedllvm/include/llvm/IR/FixedPointBuilder.h
The file was modifiedclang/test/Frontend/fixed_point_compound.c
Commit 7e44208115b35ad34cc10259e9c375abbd636ef5 by llvm-dev
[X86][SSE] combineSubToSubus - add v16i32 handling on pre-AVX512BW targets.

v16i32 -> v16i16/v8i16 truncation is now good enough using PACKSS/PACKUS + shuffle combining that its no longer necessary to early-out on pre-AVX512BW targets.

This was noticed while looking at completing PR40111 and moving combineSubToSubus to DAGCombine entirely.
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2ed914cb7e9c0737bdf60a0b1fd48b6499973325 by llvm-dev
[X86][SSE] getFauxShuffleMask - handle PACKSS(SRAI(),SRAI()) shuffle patterns.

We can't easily treat ASHR a faux shuffle, but if it was just feeding a PACKSS then it was likely being used as sign-extension for a truncation, so just peek through and adjust the mask accordingly.
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 80f078548868d0dd3d74ab8a1deb8aa46870cdf3 by nicolas.vasilache
[mlir][Linalg] NFC - Refactor fusion APIs

This revision uniformizes fusion APIs to allow passing OpOperand, OpResult and adds a finer level of control fusion.

Differential Revision: https://reviews.llvm.org/D94493
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/test/lib/Transforms/TestLinalgFusionTransforms.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
Commit a6759477129c98820a56231d2f3fd27e5fe31ab3 by Paul C. Anagnostopoulos
[TableGen] Improve error message for semicolon after braced body.

Add a test for this message.

Differential Revision: https://reviews.llvm.org/D94412
The file was modifiedllvm/lib/TableGen/TGParser.cpp
The file was addedllvm/test/TableGen/spurious-semi.td
Commit 0bd9a1369112f7d0a8a3b94a050fd5ed37037e9b by clementval
[mlir][openacc] Use TableGen information for default enum

Use TableGen and information in ACC.td for the Default enum in the OpenACC dialect.
This patch generalize what was done for OpenMP for directives.

Follow up patch after D93576

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D93710
The file was addedmlir/test/mlir-tblgen/directive-common.td
The file was modifiedmlir/tools/mlir-tblgen/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
The file was removedmlir/tools/mlir-tblgen/OpenMPCommonGen.cpp
The file was modifiedmlir/include/mlir/Dialect/OpenACC/CMakeLists.txt
The file was addedmlir/tools/mlir-tblgen/DirectiveCommonGen.cpp
The file was removedmlir/test/mlir-tblgen/openmp-common.td
The file was modifiedllvm/include/llvm/Frontend/OpenACC/ACC.td
Commit 07605ea1f3c94e0a23450f5c9ab3902862d7ff03 by bjorn.a.pettersson
[X86] Improved lowering for saturating float to int.

Adapted from D54696 by @nikic.

This patch improves lowering of saturating float to
int conversions, FP_TO_[SU]INT_SAT, for X86.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D86079
The file was modifiedllvm/test/CodeGen/X86/fptoui-sat-scalar.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/fptosi-sat-scalar.ll
Commit 24faa87075ac1b4e4d7f7336271b1ba72ffcc2c0 by marukawa
[VE] Update VELIntrinsic tests

Update comment and style of regression tests for VELIntrinsic

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D94490
The file was modifiedllvm/test/CodeGen/VE/VELIntrinsics/vld.ll
The file was modifiedllvm/test/CodeGen/VE/VELIntrinsics/vand.ll
Commit 2f7ec77e3cdb9d874e0b6a73d3d7a6fe02c0125d by antiagainst
[mlir][spirv] NFC: place ops in the proper file for their categories

This commit moves dangling ops in the main ops.td file to the proper
file matching their categories. This makes ops.td as purely including
all category files.

Differential Revision: https://reviews.llvm.org/D94413
The file was addedmlir/test/Dialect/SPIRV/IR/barrier-ops.mlir
The file was modifiedmlir/test/Dialect/SPIRV/IR/group-ops.mlir
The file was modifiedmlir/test/Dialect/SPIRV/IR/structure-ops.mlir
The file was modifiedmlir/test/Dialect/SPIRV/IR/bit-ops.mlir
The file was addedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
The file was addedmlir/test/Dialect/SPIRV/IR/cast-ops.mlir
The file was addedmlir/test/Dialect/SPIRV/IR/memory-ops.mlir
The file was addedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td
The file was addedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
The file was addedmlir/test/Dialect/SPIRV/IR/misc-ops.mlir
The file was addedmlir/test/Target/SPIRV/barrier-ops.mlir
The file was removedmlir/test/Dialect/SPIRV/IR/ops.mlir
The file was removedmlir/test/Target/SPIRV/barrier.mlir
The file was modifiedmlir/test/Dialect/SPIRV/IR/logical-ops.mlir
Commit dd07d60ec33969ae4f1e37500bb852563e142dfb by bjorn.a.pettersson
[SLP] Add test case showing a bug when dealing with padded types

We shouldn't vectorize stores of non-packed types (i.e. types that
has padding between consecutive variables in a scalar layout,
but being packed in a vector layout).

The problem was detected as a miscompile in a downstream test case.

This is a pre-commit of a test case for the fix in D94446.
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/bad_types.ll
Commit 3f7b4ce96065eea66bf4344973173e76ec1a4255 by nemanja.i.ibm
[PowerPC] Add support for embedded devices with EFPU2

PowerPC cores like e200z759n3 [1] using an efpu2 only support single precision
hardware floating point instructions. The single precision instructions efs*
and evfs* are identical to the spe float instructions while efd* and evfd*
instructions trigger a not implemented exception.

This patch introduces a new command line option -mefpu2 which leads to
single-hardware / double-software code generation.

[1] Core reference:
  https://www.nxp.com/files-static/32bit/doc/ref_manual/e200z759CRM.pdf

Differential revision: https://reviews.llvm.org/D92935
The file was modifiedclang/docs/ClangCommandLineReference.rst
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
The file was modifiedclang/test/Driver/ppc-features.cpp
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/spe.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
Commit 4086072f8a9200216088c435c9aa90a2d8ed74a5 by antiagainst
Reland "[mlir][linalg] Support parsing attributes in named op spec"

With this, now we can specify a list of attributes on named ops
generated from the spec. The format is defined as

```
attr-id ::= bare-id (`?`)?
attr-typedef ::= type (`[` `]`)?
attr-def ::= attr-id `:` attr-typedef

tc-attr-def ::= `attr` `(` attr-def-list `)`
tc-def ::= `def` bare-id
  `(`tensor-def-list`)` `->` `(` tensor-def-list`)`
  (tc-attr-def)?
```

For example,

```
ods_def<SomeCppOp>
def some_op(...) -> (...)
attr(
  f32_attr: f32,
  i32_attr: i32,
  array_attr : f32[],
  optional_attr? : f32
)
```

where `?` means optional attribute and `[]` means array type.

Reviewed By: hanchung, nicolasvasilache

Differential Revision: https://reviews.llvm.org/D94240
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
Commit 4fa01f72de6cc48a44afe057c04803711160c92d by zinenko
[mlir][CAPI] Fix inline function declaration

Add `static` keyword, otherwise build fail with linker error for some cases.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D94496
The file was modifiedmlir/include/mlir-c/AffineExpr.h
Commit 9667d15e7496e6d8c313251f22ac157dbbd0c1c2 by zinenko
[mlir] Fix for LIT tests

Add `MLIR_SPIRV_CPU_RUNNER_ENABLED` to `llvm_canonicalize_cmake_booleans`.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94407
The file was modifiedmlir/test/CMakeLists.txt
Commit 1f1250151f222ba391d05dcc173f4b6c65d05ca2 by marek.kurdej
[libc++] [C++2b] [P1048] Add is_scoped_enum and is_scoped_enum_v.

* https://wg21.link/p1048

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D94409
The file was modifiedlibcxx/docs/FeatureTestMacroTable.rst
The file was addedlibcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/is_scoped_enum.pass.cpp
The file was modifiedlibcxx/utils/generate_feature_test_macro_components.py
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp
The file was modifiedlibcxx/include/version
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/type_traits.version.pass.cpp
The file was modifiedlibcxx/docs/Cxx2bStatusPaperStatus.csv
Commit 8349fa0fdd3a372f88ea53de6c906d987c1f4fec by antiagainst
[mlir][spirv] NFC: split deserialization into multiple source files

This avoids large source files and gives a better structure. It also
allows leveraging compilation parallelism.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D94360
The file was addedmlir/lib/Target/SPIRV/Deserialization/Deserialization.cpp
The file was addedmlir/lib/Target/SPIRV/Deserialization/CMakeLists.txt
The file was addedmlir/lib/Target/SPIRV/Serialization/CMakeLists.txt
The file was removedmlir/lib/Target/SPIRV/Deserialization.cpp
The file was addedmlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp
The file was addedmlir/lib/Target/SPIRV/Deserialization/Deserializer.h
The file was addedmlir/lib/Target/SPIRV/CMakeLists.txt
The file was addedmlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
The file was modifiedmlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
The file was modifiedmlir/lib/Target/CMakeLists.txt
The file was addedmlir/lib/Target/SPIRV/Serialization/Serialization.cpp
The file was removedmlir/lib/Target/SPIRV/Serialization.cpp
Commit 93b54b7c6733fcb11fd6536499e73872d7452ffb by Jinsong Ji
[PowerPC][NFCI] PassSubtarget to ASMWriter

Subtarget feature bits are needed to change instprinter's behavior based
on feature bits.

Most of the other popular targets were updated back in 2015,
in https://reviews.llvm.org/rGb46d0234a6969
we should update it too.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D94449
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
Commit 67a339e96839cdecb5efad0e2731ab20a4ee458e by jurahul
[MLIR] Disallow `sym_visibility`, `sym_name` and `type` attributes in the parsed attribute dictionary.

Differential Revision: https://reviews.llvm.org/D94200
The file was modifiedmlir/lib/IR/FunctionImplementation.cpp
The file was modifiedmlir/test/IR/core-ops.mlir
The file was modifiedmlir/test/IR/invalid-func-op.mlir
The file was modifiedmlir/test/Dialect/Tosa/inlining.mlir
Commit 85aaa3e310c23ec8a375b7a2e2fceee5a72441ef by llvm-dev
[X86] Regenerate sdiv_fix_sat.ll + udiv_fix_sat.ll tests

Adding missing libcall PLT qualifiers
The file was modifiedllvm/test/CodeGen/X86/sdiv_fix_sat.ll
The file was modifiedllvm/test/CodeGen/X86/udiv_fix_sat.ll
Commit dd955771240289fbcba5fa1312cb8c78f20cd78f by Akira
Fix typo in diagnostic message

rdar://66684531
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
Commit a4931d4fe38d6feef53f97f3dcc7792bfcb06c84 by llvm-dev
[AMDGPU] Regenerate umax crash test
The file was modifiedllvm/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll
Commit 3d9c51d111d0c8480d10fc48fb621bac1d080449 by cullen.rhodes
[SVE][NFC] Regenerate a few CodeGen tests

Regenerated using llvm/utils/update_llc_test_checks.py as part of
D94504, committing separately to reduce the diff for D94504.
The file was modifiedllvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
Commit 348471575d9c24bbfb124ca5eac1589de075da88 by aaron
Add -ansi option to CompileOnly group

-ansi is documented as being the "same as -std=c89", but there are
differences when passing it to a link.

Adding -ansi to said group makes sense since it's supposed to be an
alias for -std=c89 and resolves this inconsistency.
The file was modifiedclang/include/clang/Driver/Options.td
Commit b117d17d264f448e0b037a62f5a48ec9aedd886c by smeenai
[doc] Place sha256 in lld/README.md into backticks

Reviewed By: smeenai

Differential Revision: https://reviews.llvm.org/D93984
The file was modifiedlld/README.md
Commit ef3800e82169c674219501d9ac09ef12b28e6359 by aaron
Return false from __has_declspec_attribute() if not explicitly enabled

Currently, projects can check for __has_declspec_attribute() and use
it accordingly, but the check for __has_declspec_attribute will return
true even if declspec attributes are not enabled for the target.

This changes Clang to instead return false when declspec attributes are
not supported for the target.
The file was modifiedclang/lib/Lex/PPMacroExpansion.cpp
Commit 5aefc8dc4d14ad04259ab8ae0b2e0da2596d66f7 by mgorny
[llvm] [cmake] Remove obsolete /usr/local hack for *BSD

Remove the hack adding /usr/local paths on FreeBSD and DragonFlyBSD.
It does not seem to be necessary today, and it breaks cross builds.

Differential Revision: https://reviews.llvm.org/D94491
The file was modifiedllvm/CMakeLists.txt
Commit bb9ebf6baf7057d7f2aed90fccbac2414cf9a134 by Dávid Bolvanský
[Tests] Add tests for new InstCombine OR transformation, NFC
The file was modifiedllvm/test/Transforms/InstCombine/or.ll
Commit 0529946b5bafafd10d77b946ee9fa96f388860ef by Dávid Bolvanský
[instCombine] Add (A ^ B) | ~(A | B) -> ~(A & B)

define i32 @src(i32 %x, i32 %y) {
%0:
  %xor = xor i32 %y, %x
  %or = or i32 %y, %x
  %neg = xor i32 %or, 4294967295
  %or1 = or i32 %xor, %neg
  ret i32 %or1
}
=>
define i32 @tgt(i32 %x, i32 %y) {
%0:
  %and = and i32 %x, %y
  %neg = xor i32 %and, 4294967295
  ret i32 %neg
}
Transformation seems to be correct!

https://alive2.llvm.org/ce/z/Cvca4a
The file was modifiedllvm/test/Transforms/InstCombine/or.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 6f4d460762006af17826693abc1e7139a76aa1f2 by joshisameeran17
[Flang][openmp][openacc] Extend CheckNoBranching to handle branching provided by LabelEnforce.

`CheckNoBranching` is currently handling only illegal branching out for constructs
with `Parser::Name` in them.
Extend the same for handling illegal branching out caused by `Parser::Label` based statements.
This patch could possibly solve one of the issues(typically branching out) mentioned in D92735.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D93447
The file was modifiedflang/lib/Semantics/check-directive-structure.h
The file was modifiedflang/test/Semantics/omp-parallell01.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
Commit 03c8d6a0c4bd0016bdfd1e53e6878696fe6412ed by craig.topper
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.

If SETO/SETUO aren't legal, they'll be expanded and we'll end up
with 3 comparisons.

SETONE is equivalent to (SETOGT || SETOLT)
so if one of those operations is supported use that expansion. We
don't need both since we can commute the operands to make the other.

SETUEQ can be implemented with !(SETOGT || SETOLT) or (SETULE && SETUGE).
I've only implemented the first because it didn't look like most of the
affected targets had legal SETULE/SETUGE.

Reviewed By: frasercrmck, tlively, nemanjai

Differential Revision: https://reviews.llvm.org/D94450
The file was modifiedllvm/test/CodeGen/RISCV/float-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-f32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-f64.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-comparisons.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-fcmp.ll
The file was modifiedllvm/test/CodeGen/PowerPC/spe.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/setcc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-br-fcmp.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/test/CodeGen/RISCV/float-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
Commit 4718ec01669b01373180f4cd1256c6e2dd6f3999 by zeratul976
[clangd] Avoid recursion in TargetFinder::add()

Fixes https://github.com/clangd/clangd/issues/633

Differential Revision: https://reviews.llvm.org/D94382
The file was modifiedclang-tools-extra/clangd/FindTarget.cpp
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
The file was modifiedclang-tools-extra/clangd/FindTarget.h
Commit f748e92295515ea7b39cd687a718915b559de6ec by aeubanks
[NewPM] Run non-trivial loop unswitching under -O2/3/s/z

Fixes https://bugs.llvm.org/show_bug.cgi?id=48715.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D94448
The file was modifiedllvm/test/Transforms/LoopUnroll/opt-levels.ll
The file was addedllvm/test/Transforms/SimpleLoopUnswitch/pipeline.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit a14040bd4d902419b53cf0ad576caa0f01eccf5c by craig.topper
[RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 scalar operand.

We can use a 0 immediate to avoid needing to materialize 0 into
an FPR first.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D94459
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit 08d4a50467ecef1337f8d7d9763c7738861bd6f6 by flo
[FunctionAttrs] Precommit tests for willreturn inference.

Tests for D94502.
The file was addedllvm/test/Transforms/FunctionAttrs/willreturn.ll
Commit eef4bdbb34de2dda657668c2ab39397e61e36a0a by arthur.j.odwyer
[libc++] Add a missing `<_Compare>` template argument.

Sometimes `_Compare` is an lvalue reference type, so letting it be
deduced is pretty much always wrong. (Well, less efficient than
it could be, anyway.)

Differential Revision: https://reviews.llvm.org/D93562
The file was modifiedlibcxx/include/algorithm
Commit 79f99ba65d96a35a79911daf1b67559dd52a684d by brad
[libcxx] Port to OpenBSD

Add initial OpenBSD support.

Reviewed By: ldionne

Differential Revision: https://reviews.llvm.org/D94205
The file was modifiedlibcxx/include/__locale
The file was modifiedlibcxx/include/CMakeLists.txt
The file was addedlibcxx/include/support/openbsd/xlocale.h
The file was modifiedlibcxx/include/__config
Commit 7ecad2e4ced180b4fdebc6b7bf6d26d83b454318 by nikita.ppv
[InstSimplify] Don't fold gep p, -p to null

This is a partial fix for https://bugs.llvm.org/show_bug.cgi?id=44403.
Folding gep p, q-p to q is only legal if p and q have the same
provenance. This fold should probably be guarded by something like
getUnderlyingObject(p) == getUnderlyingObject(q).

This patch is a partial fix that removes the special handling for
gep p, 0-p, which will fold to a null pointer, which would certainly
not pass an underlying object check (unless p is also null, in which
case this would fold trivially anyway). Folding to a null pointer
is particularly problematic due to the special handling it receives
in many places, making end-to-end miscompiles more likely.

Differential Revision: https://reviews.llvm.org/D93820
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/gep.ll
Commit bdd1ad5e5c57ae0f0bf899517c540ad8a679f01a by tianshilei1992
[OpenMP] Fixed include directories for OpenMP when building OpenMP with LLVM_ENABLE_RUNTIMES

Some LLVM headers are generated by CMake. Before the installation,
LLVM's headers are distributed everywhere, some of which are in
`${LLVM_SRC_ROOT}/llvm/include/llvm`, and some are in
`${LLVM_BINARY_ROOT}/include/llvm`. After intallation, they're all in
`${LLVM_INSTALLATION_ROOT}/include/llvm`.

OpenMP now depends on LLVM headers. Some headers depend on headers generated
by CMake. When building OpenMP along with LLVM, a.k.a via `LLVM_ENABLE_RUNTIMES`,
we need to tell OpenMP where it can find those headers, especially those still
have not been copied/installed.

Reviewed By: jdoerfert, jhuber6

Differential Revision: https://reviews.llvm.org/D94534
The file was modifiedopenmp/libomptarget/src/CMakeLists.txt
The file was modifiedopenmp/libomptarget/CMakeLists.txt
The file was modifiedopenmp/libomptarget/plugins/amdgpu/CMakeLists.txt
The file was modifiedopenmp/CMakeLists.txt
Commit 33e2494bea653a845cb0502cc6d3cecdf2b47750 by jonathanchesterfield
[libomptarget][amdgpu][nfc] Fix build on centos

[libomptarget][amdgpu][nfc] Fix build on centos

rtl.cpp replaced 224 with a #define from elf.h, but that
doesn't work on a centos 7 build machine with an old elf.h

Reviewed By: ronlieb

Differential Revision: https://reviews.llvm.org/D94528
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
Commit e5f51fdd650c6d20c81fedb8e856e9858aa10991 by david.truby
[clang][aarch64] Precondition isHomogeneousAggregate on isCXX14Aggregate

MSVC on WoA64 includes isCXX14Aggregate in its definition. This is de-facto
specification on that platform, so match msvc's behaviour.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=47611

Co-authored-by: Peter Waller <peter.waller@arm.com>

Differential Revision: https://reviews.llvm.org/D92751
The file was modifiedclang/lib/CodeGen/MicrosoftCXXABI.cpp
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedclang/test/CodeGenCXX/homogeneous-aggregates.cpp
The file was modifiedclang/lib/CodeGen/CGCXXABI.h
The file was modifiedllvm/test/CodeGen/AArch64/arm64-windows-calls.ll
Commit 6cd44b204c6c6f2e915270af6792f247c4c23abc by flo
[FunctionAttrs] Derive willreturn for fns with readonly` & `mustprogress`.

Similar to D94125, derive `willreturn` for functions that are `readonly` and
`mustprogress` in FunctionAttrs.

To quote the reasoning from D94125:

    Since D86233 we have `mustprogress` which, in combination with
    `readonly`, implies `willreturn`. The idea is that every side-effect
    has to be modeled as a "write". Consequently, `readonly` means there
    is no side-effect, and `mustprogress` guarantees that we cannot "loop"
    forever without side-effect.

Reviewed By: jdoerfert, nikic

Differential Revision: https://reviews.llvm.org/D94502
The file was modifiedllvm/include/llvm/IR/Function.h
The file was modifiedllvm/test/Transforms/FunctionAttrs/willreturn.ll
The file was modifiedllvm/lib/Transforms/IPO/FunctionAttrs.cpp
Commit e53bbd99516fc7b612df1ae08d48288d0b8784ea by zequanwu
[IR] move nomerge attribute from function declaration/definition to callsites

Move nomerge attribute from function declaration/definition to callsites to
allow virtual function calls attach the attribute.

Differential Revision: https://reviews.llvm.org/D94537
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/test/CodeGen/attr-nomerge.cpp
The file was modifiedclang/lib/CodeGen/CGCall.cpp
Commit 922a5b894114defb5302e514973de8c9cd23af6a by yitzhakm
[clang-tidy] Add test for Transformer-based checks with diagnostics.

Adds a test that checks the diagnostic output of the tidy.

Differential Revision: https://reviews.llvm.org/D94453
The file was modifiedclang-tools-extra/unittests/clang-tidy/TransformerClangTidyCheckTest.cpp
Commit d49974f9c98ebce5a679eced9f27add138b881fa by nikita.ppv
[InstCombine] Regenerate test checks (NFC)
The file was modifiedllvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll
The file was modifiedllvm/test/Transforms/InstCombine/range-check.ll
The file was modifiedllvm/test/Transforms/InstCombine/2007-03-13-CompareMerge.ll
The file was modifiedllvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll
The file was modifiedllvm/test/Transforms/InstCombine/2007-05-10-icmp-or.ll
The file was modifiedllvm/test/Transforms/InstCombine/2008-01-13-AndCmpCmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/2012-02-28-ICmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
The file was modifiedllvm/test/Transforms/InstCombine/2008-06-21-CompareMiscomp.ll
The file was modifiedllvm/test/Transforms/InstCombine/2007-11-15-CompareMiscomp.ll
The file was modifiedllvm/test/Transforms/InstCombine/2008-08-05-And.ll
Commit 9f61fbd75ae1757d77988b37562de4d6583579aa by listmail
[LV] Relax assumption that LCSSA implies single entry

This relates to the ongoing effort to support vectorization of multiple exit loops (see D93317).

The previous code assumed that LCSSA phis were always single entry before the vectorizer ran. This was correct, but only because the vectorizer allowed only a single exiting edge. There's nothing in the definition of LCSSA which requires single entry phis.

A common case where this comes up is with a loop with multiple exiting blocks which all reach a common exit block. (e.g. see the test updates)

Differential Revision: https://reviews.llvm.org/D93725
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-form.ll
Commit f706486eaf07020b11f2088274c757e4070fe6d1 by sunil.srivastava
Fix for crash in __builtin_return_address in template context.

The check for argument value needs to be guarded by !isValueDependent().

Differential Revision: https://reviews.llvm.org/D94438
The file was modifiedclang/test/Sema/builtin-returnaddress.c
The file was modifiedclang/lib/Sema/SemaChecking.cpp
Commit fb063c933f0062db7fee622f7a43a6a5e560672d by nikita.ppv
[InstCombine] Duplicate tests for logical and/or (NFC)

This replicates existing and/or tests to also test variants using
select. This should help us get a more accurate view on which
optimizations we're missing if we disable the select -> and/or
fold.
The file was modifiedllvm/test/Transforms/InstCombine/sign-test-and-or.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmp-min-max.ll
The file was modifiedllvm/test/Transforms/InstCombine/bit-checks.ll
The file was modifiedllvm/test/Transforms/InstCombine/2012-02-28-ICmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/logical-select.ll
The file was modifiedllvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
The file was modifiedllvm/test/Transforms/InstCombine/or-fcmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll
The file was modifiedllvm/test/Transforms/InstCombine/2008-08-05-And.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp-custom-dl.ll
The file was modifiedllvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll
The file was modifiedllvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
The file was modifiedllvm/test/Transforms/InstCombine/and2.ll
The file was modifiedllvm/test/Transforms/InstCombine/merge-icmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/2008-06-21-CompareMiscomp.ll
The file was modifiedllvm/test/Transforms/InstCombine/range-check.ll
The file was modifiedllvm/test/Transforms/InstCombine/2007-05-10-icmp-or.ll
The file was modifiedllvm/test/Transforms/InstCombine/or.ll
The file was modifiedllvm/test/Transforms/InstCombine/ispow2.ll
The file was modifiedllvm/test/Transforms/InstCombine/set.ll
The file was modifiedllvm/test/Transforms/InstCombine/fold-bin-operand.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
The file was modifiedllvm/test/Transforms/InstCombine/signed-truncation-check.ll
The file was modifiedllvm/test/Transforms/InstCombine/zext-or-icmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/select.ll
The file was modifiedllvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll
The file was modifiedllvm/test/Transforms/InstCombine/freeze.ll
The file was modifiedllvm/test/Transforms/InstCombine/objsize-noverify.ll
The file was modifiedllvm/test/Transforms/InstCombine/umul-sign-check.ll
The file was modifiedllvm/test/Transforms/InstCombine/2007-03-13-CompareMerge.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-fcmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/and.ll
The file was modifiedllvm/test/Transforms/InstCombine/widenable-conditions.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-imm-canon.ll
The file was modifiedllvm/test/Transforms/InstCombine/2007-11-15-CompareMiscomp.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp-logical.ll
The file was modifiedllvm/test/Transforms/InstCombine/canonicalize-clamp-with-select-of-constant-threshold-pattern.ll
The file was modifiedllvm/test/Transforms/InstCombine/prevent-cmp-merge.ll
The file was modifiedllvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-crash-noverify.ll
The file was modifiedllvm/test/Transforms/InstCombine/dont-distribute-phi.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmps.ll
The file was modifiedllvm/test/Transforms/InstCombine/2008-01-13-AndCmpCmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/assume.ll
The file was modifiedllvm/test/Transforms/InstCombine/demorgan.ll
The file was modifiedllvm/test/Transforms/InstCombine/onehot_merge.ll
The file was modifiedllvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll
Commit caafdf07bbccbe89219539e2b56043c2a98358f1 by listmail
[LV] Weaken spuriously strong assert in LoopVersioning

LoopVectorize uses some utilities on LoopVersioning, but doesn't actually use it for, you know, versioning.  As a result, the precondition LoopVersioning expects is too strong for this user.  At the moment, LoopVectorize supports any loop with a unique exit block, so check the same precondition here.

Really, the whole class structure here is a mess.  We should separate the actual versioning from the metadata updates, but that's a bigger problem.
The file was modifiedllvm/lib/Transforms/Utils/LoopVersioning.cpp
Commit 46507a96fc13146f73e5915a008055c5a59191c2 by spatel
[SLP] reduce code duplication while matching reductions; NFC
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 554be30a42802d66807f93e4671a518c1c04e0f8 by spatel
[SLP] reduce code duplication in processing reductions; NFC
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 92fb5c49e8aa53ac97fa2fb1a891a4d7ccfd75c5 by spatel
[SLP] rename variable to improve readability; NFC

The OperationData in the 2nd block (visiting the operands)
is completely independent of the 1st block.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 9e7895a8682ce3ad98c006955d573d5f2fded4f6 by spatel
[SLP] reduce code duplication while processing reductions; NFC
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 7583ae48a3c37a78e57106e4feff6045aaa45584 by craig.topper
[RISCV] Add double test cases to vfmerge-rv32.ll. NFC
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll
Commit e15f3ddcae65525176d1f152effb88cd3c6441a3 by nikita.ppv
[InstCombine] Add tests for logical and/or poison implication (NFC)

These tests cover some cases where we can fold select to and/or
based on poison implication logic.
The file was modifiedllvm/test/Transforms/InstCombine/select-and-or.ll
Commit 71ed4b6ce57d8843ef705af8f98305976a8f107a by selliott
[RISCV] Legalize select when Zbt extension available

The custom expansion of select operations in the RISC-V backend
interferes with the matching of cmov instructions. Legalizing
select when the Zbt extension is available solves that problem.

Reviewed By: lenary, craig.topper

Differential Revision: https://reviews.llvm.org/D93767
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbbp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbt.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbs.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64Zbt.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbb.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
Commit 23390e7a131a67fd70e26692fc83f62860dd1095 by nikita.ppv
[InstCombine] Handle logical and/or in assume optimization

assume(a && b) can be converted to assume(a); assume(b) even if
the condition is logical. Same for assume(!(a || b)).
The file was modifiedllvm/test/Transforms/InstCombine/assume.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit 7fd18508134112edb93852c16923a74bfff99cd2 by zinenko
[mlir] Update LLVM dialect type documentation

Recent commits reconfigured LLVM dialect types to use built-in types whenever
possible. Update the documentation accordingly.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94485
The file was modifiedmlir/docs/Dialects/LLVM.md
Commit 2a49b7c64a33566cf5db1a5b4042d6037ccc7cf5 by modimo
[Inliner] Change inline remark format and update ReplayInlineAdvisor to use it

This change modifies the source location formatting from:
LineNumber.Discriminator
to:
LineNumber:ColumnNumber.Discriminator

The motivation here is to enhance location information for inline replay that currently exists for the SampleProfile inliner. This will be leveraged further in inline replay for the CGSCC inliner in the related diff.

The ReplayInlineAdvisor is also modified to read the new format and now takes into account the callee for greater accuracy.

Testing:
ninja check-llvm

Reviewed By: mtrofin

Differential Revision: https://reviews.llvm.org/D94333
The file was modifiedllvm/include/llvm/Analysis/InlineAdvisor.h
The file was modifiedllvm/lib/Analysis/InlineAdvisor.cpp
The file was modifiedllvm/lib/Analysis/ReplayInlineAdvisor.cpp
The file was modifiedclang/test/Frontend/optimization-remark-with-hotness-new-pm.c
The file was modifiedllvm/include/llvm/Analysis/ReplayInlineAdvisor.h
The file was modifiedllvm/test/Transforms/Inline/optimization-remarks-passed-yaml.ll
The file was modifiedllvm/test/Transforms/SampleProfile/remarks-hotness.ll
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
The file was modifiedllvm/test/Transforms/SampleProfile/Inputs/inline-replay.txt
The file was modifiedclang/test/Frontend/optimization-remark-with-hotness.c
The file was modifiedllvm/test/Transforms/SampleProfile/remarks.ll
The file was modifiedllvm/test/Transforms/SampleProfile/inline-replay.ll
Commit 68ff52ffead2ba25cca442778ab19286000daad7 by tianshilei1992
[OpenMP] Fixed the link error that cannot find static data member

Constant static data member can be defined in the class without another
define after the class in C++17. Although it is C++17, Clang can still handle it
even w/o the flag for C++17. Unluckily, GCC cannot handle that.

Reviewed By: jhuber6

Differential Revision: https://reviews.llvm.org/D94541
The file was modifiedopenmp/libomptarget/plugins/common/MemoryManager/MemoryManager.h
Commit d1fa7afc7aefd822698fe86431d8184b1e8b6683 by martin
[AArch64] [Windows] Properly add :lo12: reloc specifiers when generating assembly

This makes sure that assembly output actually can be assembled.

Set the correct MCExpr relocations specifier VK_PAGEOFF - and also
set VK_PAGE consistently even though it's not visible in the assembly
output.

Differential Revision: https://reviews.llvm.org/D94365
The file was modifiedllvm/test/CodeGen/AArch64/stack-protector-target.ll
The file was modifiedllvm/test/CodeGen/AArch64/win_cst_pool.ll
The file was modifiedllvm/test/CodeGen/AArch64/cfguard-checks.ll
The file was modifiedllvm/test/CodeGen/AArch64/win-tls.ll
The file was modifiedllvm/test/CodeGen/AArch64/windows-extern-weak.ll
The file was modifiedllvm/test/CodeGen/AArch64/dllimport.ll
The file was modifiedllvm/test/CodeGen/AArch64/mingw-refptr.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64MCInstLower.cpp
Commit 02f1d28ed6b8f33445dae3beed8b6cc8dada4312 by martin
[libcxx] Avoid overflows in the windows __libcpp_steady_clock_now()

As freq.QuadValue can be in the range of 10000000 to 19200000,
the multiplication before division makes the calculation overflow
and wrap to negative values every 16-30 minutes.

Instead count the whole seconds separately before adding the
scaled fractional seconds.

Add a testcase for steady_clock to check that the values returned for
now() compare as bigger than the zero time origin; this
corresponds to a testcase in Qt [1] [2] (that failed spuriously
due to this).

[1] https://bugreports.qt.io/browse/QTBUG-89539
[2] https://code.qt.io/cgit/qt/qtbase.git/tree/tests/auto/corelib/kernel/qdeadlinetimer/tst_qdeadlinetimer.cpp?id=f8de5e54022b8b7471131b7ad55c83b69b2684c0#n569

Differential Revision: https://reviews.llvm.org/D93456
The file was modifiedlibcxx/test/std/utilities/time/time.clock/time.clock.steady/now.pass.cpp
The file was modifiedlibcxx/src/chrono.cpp
Commit 01f1273fe2f0c246f17162de24a8b6e11bad23a8 by tianshilei1992
[OpenMP] Fixed a typo in openmp/CMakeLists.txt
The file was modifiedopenmp/CMakeLists.txt
Commit 3d397091591fca4aa16153bba22f031218bee47d by Matthew.Arsenault
AMDGPU: Remove wrapper only call limitation

This seems to only have overridden cold handling, which we probably
shouldn't do. As far as I can tell the wrapper library functions are
still inlined as appropriate.
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInline.cpp
Commit cf45731f0eaead79e1ac501b397e330df41ec152 by i
[Driver] Fix assertion failure when -fprofile-generate -fcs-profile-generate are used together

If conflicting `-fprofile-generate -fcs-profile-generate` are used together,
there is currently an assertion failure. Fix the failure.

Also add some driver tests.

Reviewed By: xur

Differential Revision: https://reviews.llvm.org/D94463
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was addedclang/test/Driver/fcs-profile-generate.c
Commit 55f2eeebc96e7522e49e19074cbfbe4e7f074b5b by mtrofin
[NFC] Disallow unused prefixes in MC/AMDGPU

1 out of 2 patches.

Differential Revision: https://reviews.llvm.org/D94553
The file was modifiedllvm/test/MC/AMDGPU/buf-fmt-d16-unpacked.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_vopc.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-metadata-kernel-args-v3.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-metadata-kernel-code-props.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_vopcx.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_dpp8.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-metadata-kernel-debug-props.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_vop1.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_sop.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-wave-size.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_smem.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_ds.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-metadata-kernel-attrs.s
The file was modifiedllvm/test/MC/AMDGPU/regression/bug28538.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-metadata-kernel-code-props-v3.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_dpp16.s
The file was modifiedllvm/test/MC/AMDGPU/regression/bug28165.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-metadata-kernel-args.s
The file was modifiedllvm/test/MC/AMDGPU/add-sub-no-carry.s
The file was modifiedllvm/test/MC/AMDGPU/regression/bug28413.s
The file was modifiedllvm/test/MC/AMDGPU/ds.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
The file was modifiedllvm/test/MC/AMDGPU/regression/bug28168.s
The file was modifiedllvm/test/MC/AMDGPU/flat-global.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_vop2.s
The file was modifiedllvm/test/MC/AMDGPU/ds-gfx9.s
The file was modifiedllvm/test/MC/AMDGPU/flat-gfx10.s
The file was modifiedllvm/test/MC/AMDGPU/flat-scratch-instructions.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_flat.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-metadata-kernel-attrs-v3.s
The file was modifiedllvm/test/MC/AMDGPU/buf-fmt-d16-packed.s
Commit a7130d85e4b9e47b18a89eac3d47fd8c19d449c1 by n.james93
[ADT][NFC] Use empty base optimisation in BumpPtrAllocatorImpl

Most uses of this class just use the default MallocAllocator.
As this contains no fields, we can use the empty base optimisation for BumpPtrAllocatorImpl and save 8 bytes of padding for most use cases.

This prevents using a class that is marked as `final` as the `AllocatorT` template argument.
In one must use an allocator that has been marked as `final`, the simplest way around this is a proxy class.
The class should have all the methods that `AllocaterBase` expects and should forward the calls to your own allocator instance.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D94439
The file was modifiedllvm/include/llvm/Support/Allocator.h
Commit 1730b0f66adaea6ed65d441dc2032013dd3c3664 by craig.topper
[RISCV] Remove '.mask' from vcompress intrinsic name. NFC

It has a mask argument, but isn't a masked instruction. It doesn't
use the mask policy of or the v0.t syntax.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
Commit 6166b91e83716fbe930b2dc4e2a2217c52ee31a7 by llvm
[ELF][NFCI] small cleanup to OutputSections.h

OutputSections.h used to close the lld::elf namespace only to
immediately open it again. This change merges both parts into
one.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D94538
The file was modifiedlld/ELF/OutputSections.h
Commit 175288a1afef2b6976455aab5ce51c66d28f8bca by hoy
Add sample-profile-suffix-elision-policy attribute with -funique-internal-linkage-names.

Adding sample-profile-suffix-elision-policy attribute to functions whose linkage names are uniquefied so that their unique name suffix won't be trimmed when applying AutoFDO profiles.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D94455
The file was modifiedllvm/test/Transforms/UniqueInternalLinkageNames/unique-internal-linkage-names.ll
The file was modifiedllvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
Commit ddcb0aae8b0dd87414105d264d1ee9eac9567476 by Jessica Paquette
[MIPatternMatch] Add matcher for G_PTR_ADD

Add a matcher which recognizes G_PTR_ADD and add a test.

Differential Revision: https://reviews.llvm.org/D94348
The file was modifiedllvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
Commit 8f5ec4593754a58a4feb835a9d44d59c655bd0d1 by julian.lettner
[Sanitizer][Darwin] Fix test for macOS 11+ point releases

This test wrongly asserted that the minor version is always 0 when
running on macOS 11 and above.
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_mac_test.cpp
Commit 585612355cdf836b434a5331b1263e961135a1ab by mtrofin
[NFC] Disallow unused prefixes under MC/AMDGPU

This patches remaining tests, and patches lit.local.cfg to block future
such cases (until we flip FileCheck's flag)

Differential Revision: https://reviews.llvm.org/D94556
The file was modifiedllvm/test/MC/AMDGPU/vop1.s
The file was modifiedllvm/test/MC/AMDGPU/smrd.s
The file was modifiedllvm/test/MC/AMDGPU/vop_dpp.s
The file was modifiedllvm/test/MC/AMDGPU/smem.s
The file was modifiedllvm/test/MC/AMDGPU/vop3-gfx9.s
The file was modifiedllvm/test/MC/AMDGPU/xdl-insts-err.s
The file was modifiedllvm/test/MC/AMDGPU/literal16.s
The file was modifiedllvm/test/MC/AMDGPU/mtbuf-gfx10.s
The file was modifiedllvm/test/MC/AMDGPU/sop2.s
The file was modifiedllvm/test/MC/AMDGPU/sopk.s
The file was modifiedllvm/test/MC/AMDGPU/sopk-err.s
The file was modifiedllvm/test/MC/AMDGPU/sopp-err.s
The file was modifiedllvm/test/MC/AMDGPU/isa-version-pal.s
The file was modifiedllvm/test/MC/AMDGPU/mubuf.s
The file was modifiedllvm/test/MC/AMDGPU/isa-version-hsa.s
The file was modifiedllvm/test/MC/AMDGPU/vintrp-err.s
The file was modifiedllvm/test/MC/AMDGPU/literals.s
The file was modifiedllvm/test/MC/AMDGPU/mubuf-gfx9.s
The file was modifiedllvm/test/MC/AMDGPU/sop1-err.s
The file was modifiedllvm/test/MC/AMDGPU/lit.local.cfg
The file was modifiedllvm/test/MC/AMDGPU/vintrp.s
The file was modifiedllvm/test/MC/AMDGPU/reg-syntax-extra.s
The file was modifiedllvm/test/MC/AMDGPU/vop3-convert.s
The file was modifiedllvm/test/MC/AMDGPU/vop_sdwa.s
The file was modifiedllvm/test/MC/AMDGPU/sopp.s
The file was modifiedllvm/test/MC/AMDGPU/out-of-range-registers.s
The file was modifiedllvm/test/MC/AMDGPU/sopc.s
The file was modifiedllvm/test/MC/AMDGPU/isa-version-unk.s
The file was modifiedllvm/test/MC/AMDGPU/mtbuf.s
The file was modifiedllvm/test/MC/AMDGPU/vop_dpp_expr.s
The file was modifiedllvm/test/MC/AMDGPU/sop1.s
Commit 0d88d7d82bc44b211a8187650a06c6cd3492186a by dblaikie
Delete unused function (was breaking the -Werror build)
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
Commit 314e29ed2b78c69111635ecab94541b94c9e4c67 by Joseph.Nash
[AMDGPU] Add _e64 suffix to VOP3 Insts

Previously, instructions which could be
expressed as VOP3 in addition to another
encoding had a _e64 suffix on the tablegen
record name, while those
only available as VOP3 did not. With this
patch, all VOP3s will have the _e64 suffix.
The assembly does not change, only  the mir.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D94341

Change-Id: Ia8ec8890d47f8f94bbbdac43745b4e9dd2b03423
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-build-spill.mir
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/hazard-pass-ordering.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/mai-hazards.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/stale-livevar-in-twoaddr-pass.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fold_16bit_imm.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/regbank-reassign.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
The file was modifiedllvm/unittests/MI/LiveIntervalTest.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/v_swap_b32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/schedule-barrier.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SISchedule.td
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr.mir
Commit 04edcc02638bc70772baa50a74e582bb8e029872 by michaelrj
[libc] add isascii and toascii implementations

adding both at once since these are trivial functions.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D94558
The file was modifiedlibc/config/linux/aarch64/entrypoints.txt
The file was modifiedlibc/spec/gnu_ext.td
The file was addedlibc/src/ctype/toascii.h
The file was addedlibc/src/ctype/isascii.cpp
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt
The file was addedlibc/src/ctype/isascii.h
The file was modifiedlibc/src/ctype/CMakeLists.txt
The file was modifiedlibc/test/src/ctype/CMakeLists.txt
The file was modifiedlibc/spec/posix.td
The file was addedlibc/test/src/ctype/toascii_test.cpp
The file was addedlibc/test/src/ctype/isascii_test.cpp
The file was addedlibc/src/ctype/toascii.cpp
Commit 0c8466c0015eb8e4061b177e125e588b2138cc8a by sivachandra
[libc][NFC] Use more specific comparison macros in LdExpTest.h.
The file was modifiedlibc/test/src/math/LdExpTest.h
Commit 76643c48cdddfa220680f1ab4a83829bd83faa7a by aqjune
[LangRef] State that a nocapture pointer cannot be returned

This is a small patch stating that a nocapture pointer cannot be returned.

Discussed in D93189.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D94386
The file was modifiedllvm/docs/LangRef.rst
Commit 25eb7b08ba77a0b7c9c938490444bb8b5121233c by aqjune
[DAGCombiner] Fold BRCOND(FREEZE(COND)) to BRCOND(COND)

This patch resolves the suboptimal codegen described in http://llvm.org/pr47873 .
When CodeGenPrepare lowers select into a conditional branch, a freeze instruction is inserted.
It is then translated to `BRCOND(FREEZE(SETCC))` in SelDag.
The `FREEZE` in the middle of `SETCC` and `BRCOND` was causing a suboptimal code generation however.
This patch adds `BRCOND(FREEZE(cond))` -> `BRCOND(cond)` fold to DAGCombiner to remove the `FREEZE`.

To make this optimization sound, `BRCOND(UNDEF)` simply should nondeterministically jump to the branch or not, rather than raising UB.
It wasn't clear what happens when the condition was undef according to the comments in ISDOpcodes.h, however.
I updated the comments of `BRCOND` to make it explicit (as well as `BR_CC`, which is also a conditional branch instruction).

Note that it diverges from the semantics of `br` instruction in IR, which is explicitly UB.
Since the UB semantics was necessary to explain optimizations that use branching conditions, and SelDag doesn't seem to have such optimization, I think this divergence is okay.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D92015
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/test/CodeGen/X86/select-prof-codegen.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 82655c151450e0103a3aa60725639da607f9220c by jianzhouzh
[MSan] Tweak CopyOrigin

There could be some mis-alignments when copying origins not aligned.

I believe inaligned memcpy is rare so the cases do not matter too much
in practice.

1) About the change at line 50

Let dst be (void*)5,
then d=5, beg=4
so we need to write 3 (4+4-5) bytes from 5 to 7.

2) About the change around line 77.

Let dst be (void*)5,
because of lines 50-55, the bytes from 5-7 were already writen.
So the aligned copy is from 8.

Reviewed-by: eugenis
Differential Revision: https://reviews.llvm.org/D94552
The file was modifiedcompiler-rt/lib/msan/msan_poisoning.cpp
Commit 25b3921f2fcd8fb3241c2f79e488f25a6374b99f by thakis
[gn build] (manually) port 79f99ba65d96
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit c0f3ea8a08ca9a9ec473f6e9072ccf30dad5def8 by zhanghb97
[mlir][Python] Add checking process before create an AffineMap from a permutation.

An invalid permutation will trigger a C++ assertion when attempting to create an AffineMap from the permutation.
This patch adds an `isPermutation` function to check the given permutation before creating the AffineMap.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94492
The file was modifiedmlir/test/Bindings/Python/ir_affine_map.py
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
Commit 055644cc459eb204613ac788b73c51d5dab2fcbb by yuanke.luo
[X86][AMX] Prohibit pointer cast on load.

The load/store instruction will be transformed to amx intrinsics in the
pass of AMX type lowering. Prohibiting the pointer cast make that pass
happy.

Differential Revision: https://reviews.llvm.org/D94372
The file was addedllvm/test/Transforms/InstCombine/X86/x86-amx-load-store.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
Commit 5c7dcd7aead7b33ba065b98ab3573278feb42228 by Yuanfang Chen
[Coroutine] Update promise object's final layout index

promise is a header field but it is not guaranteed that it would be the third
field of the frame due to `performOptimizedStructLayout`.

Reviewed By: lxfind

Differential Revision: https://reviews.llvm.org/D94137
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was addedllvm/test/Transforms/Coroutines/coro-spill-promise.ll
Commit 6529d7c5a45b1b9588e512013b02f891d71bc134 by rnk
[PDB] Defer relocating .debug$S until commit time and parallelize it

This is a pretty classic optimization. Instead of processing symbol
records and copying them to temporary storage, do a first pass to
measure how large the module symbol stream will be, and then copy the
data into place in the PDB file. This requires defering relocation until
much later, which accounts for most of the complexity in this patch.

This patch avoids copying the contents of all live .debug$S sections
into heap memory, which is worth about 20% of private memory usage when
making PDBs. However, this is not an unmitigated performance win,
because it can be faster to read dense, temporary, heap data than it is
to iterate symbol records in object file backed memory a second time.

Results on release chrome.dll:
peak mem: 5164.89MB -> 4072.19MB (-1,092.7MB, -21.2%)
wall-j1:  0m30.844s -> 0m32.094s (slightly slower)
wall-j3:  0m20.968s -> 0m20.312s (slightly faster)
wall-j8:  0m19.062s -> 0m17.672s (meaningfully faster)

I gathered similar numbers for a debug, component build of content.dll
in Chrome, and the performance impact of this change was in the noise.
The memory usage reduction was visible and similar.

Because of the new parallelism in the PDB commit phase, more cores makes
the new approach faster. I'm assuming that most C++ developer machines
these days are at least quad core, so I think this is a win.

Differential Revision: https://reviews.llvm.org/D94267
The file was modifiedlld/COFF/Chunks.cpp
The file was modifiedllvm/lib/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.cpp
The file was modifiedllvm/include/llvm/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.h
The file was modifiedlld/COFF/Chunks.h
The file was modifiedlld/COFF/PDB.cpp
The file was modifiedllvm/lib/DebugInfo/PDB/Native/DbiStreamBuilder.cpp
Commit 6f0f0220380f83e8f3bf9832ffa795e9965fda2d by hansang.bae
[OpenMP] Update allocator trait key/value definitions

Use new definitions introduced in 5.1 specification.

Differential Revision: https://reviews.llvm.org/D94277
The file was modifiedopenmp/runtime/src/include/omp_lib.f90.var
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/include/omp_lib.h.var
The file was modifiedopenmp/runtime/src/kmp_alloc.cpp
The file was modifiedopenmp/runtime/src/include/omp.h.var
Commit acea470c167fc40990d9a0f06d625a34d8a4a146 by thakis
[gn build] Reorganize libcxx/include/BUILD.gn a bit

- Merge 6706342f48bea80 -- no more libcxx_needs_site_config, we now
  always need it
- Since it was always off in practice, write_config bitrot. Unbitrot
  it so that it works
- Remove copy step and let concat step write to final location
  immediately -- and fix copy destination directory

As a side effect, libcxx/include/BUILD.gn now has only a single
sources list, which means the cmake sync script should be able to
automatically sync additions and removals of .h files. On the flipside,
this means this file now must be updated after most changes to
libcxx/include/__config_site.in, and looking through the last few months
of changes this looks like it's going to be a wash.
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit 0066a09579ca90f60cb1947691e5a441f9f57a5d by smeenai
[libc++] Give extern templates default visibility on gcc

Contrary to the current visibility macro documentation, it appears that
gcc does handle visibility attribute on extern templates correctly, e.g.
https://godbolt.org/g/EejuV7. We need this so that extern template
instantiations of classes not marked _LIBCPP_TEMPLATE_VIS (e.g.
__vector_base_common) are correctly exported with gcc when building with
hidden visibility.

Reviewed By: ldionne

Differential Revision: https://reviews.llvm.org/D35388
The file was modifiedlibcxx/include/__config
The file was modifiedlibcxx/docs/DesignDocs/VisibilityMacros.rst
Commit bba3a82b56c0874757f2c1423bbdff08e2a88967 by hansang.bae
[OpenMP] Use persistent memory for omp_large_cap_mem

This change enables volatile use of persistent memory for omp_large_cap_mem*
on supported systems. It depends on libmemkind's support for persistent memory,
and requirements/details can be found at the following url.

https://pmem.io/2020/01/20/memkind-dax-kmem.html

Differential Revision: https://reviews.llvm.org/D94353
The file was modifiedopenmp/runtime/src/kmp_alloc.cpp
Commit 914e2f5a02f4f896eec9a00f536d1118bf1d9961 by kai.wang
[NFC] Use generic name for scalable vector stack ID.

Differential Revision: https://reviews.llvm.org/D94471
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-localstackalloc.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/include/llvm/CodeGen/MIRYamlMapping.h
The file was modifiedllvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-alloca-stackid.ll
The file was modifiedllvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
The file was modifiedllvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
The file was modifiedllvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
The file was modifiedllvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/framelayout-sve.mir
The file was modifiedllvm/test/CodeGen/AArch64/spillfill-sve.mir
Commit e5553b9a6ab9f02f382a31cc5117b52c3bfaf77a by Jonas Devlieghere
[dsymutil] Warn on timestmap mismatch between object file and debug map

Add a warning when the timestmap doesn't match between the object file
and the debug map entry. We were already emitting such warnings for
archive members and swift interface files. This patch also unifies the
warning across all three.

rdar://65614640

Differential revision: https://reviews.llvm.org/D94536
The file was modifiedllvm/tools/dsymutil/BinaryHolder.h
The file was modifiedllvm/test/tools/dsymutil/debug-map-parsing.test
The file was modifiedllvm/tools/dsymutil/BinaryHolder.cpp
The file was addedllvm/test/tools/dsymutil/Inputs/basic.macho.x86_64.o
The file was modifiedllvm/test/tools/dsymutil/X86/swift-ast-x86_64.test
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.cpp
Commit cd8a80de96080da33d0a7d5d5821120ddcfc4ece by Lang Hames
[Orc] Add a unit test for asynchronous definition generation.
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/Core.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
Commit f454c9f102a7f0df9d2802e30538192d4fe2f97a by serguei.katkov
[InlineSpiller] Re-tie operands if folding failed

InlineSpiller::foldMemoryOperand unties registers before an attempt to fold and
does not restore tied-ness in case of failure.

I do not have a particular test for demo of invalid behavior.
This is something of clean-up.
It is better to keep the behavior correct in case some time in future it happens.

Reviewers: reames, dantrushin
Reviewed By: dantrushin, reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D94389
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp
Commit 8a47d875b071823455931bbc119ca1e455559176 by Jonas Devlieghere
[dsymutil] Copy eh_frame content into the dSYM companion file.

Copy over the __eh_frame from the binary into the dSYM. This helps
kernel developers that are working with only dSYMs (i.e. no binaries)
when debugging a core file. This only kicks in when the __eh_frame
exists in the linked binary. Most of the time ld64 will remove the
section in favor of compact unwind info. When it is emitted, it's
generally small enough and should not bloat the dSYM.

rdar://69774935

Differential revision: https://reviews.llvm.org/D94460
The file was addedllvm/test/tools/dsymutil/Inputs/private/tmp/eh_frame/eh_frame.o
The file was modifiedllvm/tools/dsymutil/MachOUtils.cpp
The file was addedllvm/test/tools/dsymutil/X86/eh_frame.test
The file was addedllvm/test/tools/dsymutil/Inputs/private/tmp/eh_frame/eh_frame.out
Commit 84e0b14a0a419f26d0a2f7389e06aa8e36569808 by jonathanchesterfield
[libomptarget][nvptx] Include omp_data.cu in bitcode deviceRTL

[libomptarget][nvptx] Include omp_data.cu in bitcode deviceRTL

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D94565
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/CMakeLists.txt
Commit ad735badb69f389dd52e3ccef93694a0724e1293 by Jonas Devlieghere
[dsymutil] s/dwarfdump/llvm-dwarfdump/ in test
The file was modifiedllvm/test/tools/dsymutil/X86/eh_frame.test
Commit 35e4998f0c9a2f50567f5d2953db266c32fb1a25 by Jonas Devlieghere
[dsymutil] Fix spurious space in REQUIRES: line

This test is incorrectly running on non-darwin hosts.
The file was modifiedllvm/test/tools/dsymutil/X86/eh_frame.test
Commit 790c75c16373d37846c8433a69efd9b0d5e4ad12 by carl.ritson
[AMDGPU] Add SI_EARLY_TERMINATE_SCC0 for early terminating shader

Add pseudo instruction to allow early termination of pixel shader
anywhere based on the value of SCC.  The intention is to use this
when a mask of live lanes is updated, e.g. live lanes in WQM pass.
This facilitates early termination of shaders even when EXEC is
incomplete, e.g. in non-uniform control flow.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D88777
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertSkips.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/early-term.mir
Commit 157efd84abf812c1689ba6a9ecb4da2b87dde756 by serguei.katkov
[Statepoint Lowering] Add an option to allow use gc values in regs for landing pad

Default value is not changed, so it is NFC actually.

The option allows to use gc values on registers in landing pads.

Reviewers: reames, dantrushin
Reviewed By: reames, dantrushin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D94469
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
Commit fba9805ba3491db03ad538ea2db2f225f57ff98e by serguei.katkov
[Verifier] Extend statepoint verifier to cover more constants

Also old mir tests are updated to meet last changes in STATEPOINT format.

Reviewers: reames, dantrushin
Reviewed By: reames, dantrushin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D94482
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/test/CodeGen/X86/statepoint-fixup-call.mir
The file was modifiedllvm/include/llvm/CodeGen/StackMaps.h
The file was modifiedllvm/test/CodeGen/X86/non-value-mem-operand.mir
The file was modifiedllvm/lib/CodeGen/StackMaps.cpp
The file was modifiedllvm/test/CodeGen/X86/statepoint-fixup-copy-prop-neg.mir
Commit 12fc9ca3a4037a26d4bc0ac98213c846ad96e51b by kazu
[llvm] Remove redundant string initialization (NFC)

Identified with readability-redundant-string-init.
The file was modifiedllvm/lib/Analysis/CallPrinter.cpp
The file was modifiedllvm/lib/Analysis/ConstraintSystem.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/utils/TableGen/CodeGenMapTable.cpp
The file was modifiedllvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
The file was modifiedllvm/lib/Target/Mips/MipsRegisterBankInfo.h
The file was modifiedllvm/tools/llvm-ifs/llvm-ifs.cpp
The file was modifiedllvm/utils/TableGen/RISCVCompressInstEmitter.cpp
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
The file was modifiedllvm/utils/TableGen/CodeGenInstruction.cpp
The file was modifiedllvm/include/llvm/LTO/Config.h
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
Commit 2c2d489b78c43072b65f3d8c88c91def4c69f320 by kazu
[CodeGen] Remove unused function isRegLiveInExitBlocks (NFC)

The last use was removed on Jan 17, 2020 in commit
42350cd893a9cf6c199b17441dc2ba526c7cca71.
The file was modifiedllvm/lib/CodeGen/MachineLoopUtils.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineLoopUtils.h
Commit 8a20e2b3d3e149f9e40dc34673fce7953d985c24 by kazu
[llvm] Use Optional::getValueOr (NFC)
The file was modifiedllvm/lib/Target/ARC/ARCTargetMachine.cpp
The file was modifiedllvm/lib/Transforms/Utils/InlineFunction.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/lib/Target/BPF/BPFTargetMachine.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiTargetMachine.cpp
The file was modifiedllvm/lib/Target/VE/VETargetMachine.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcTargetMachine.cpp
The file was modifiedllvm/lib/Target/CSKY/CSKYTargetMachine.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreTargetMachine.cpp
The file was modifiedllvm/lib/Analysis/InlineAdvisor.cpp
The file was modifiedllvm/lib/Target/AVR/AVRTargetMachine.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
Commit f1d5cbbdee5526bc86eac0a5652b115d9bc158e5 by Jonas Devlieghere
[dsymutil] Add preliminary support for DWARF 5.

Currently dsymutil will silently fail when processing binaries with
Dwarf 5 debug info. This patch adds rudimentary support for Dwarf 5 in
dsymutil.

- Recognize relocations in the debug_addr section.
- Recognize (a subset of) Dwarf 5 form values.
- Emits valid Dwarf 5 compile unit header chains.

To simplify things (and avoid having to emit indexed sections) I decided
to emit the relocated addresses directly in the debug info section.

- DW_FORM_strx gets relocated and rewritten to DW_FORM_strp
- DW_FORM_addrx gets relocated and rewritten to DW_FORM_addr

Obviously there's a lot of work left, but this should be a step in the
right direction.

rdar://62345491

Differential revision: https://reviews.llvm.org/D94323
The file was modifiedllvm/lib/DWARFLinker/DWARFLinkerCompileUnit.cpp
The file was modifiedllvm/lib/DWARFLinker/DWARFStreamer.cpp
The file was addedllvm/test/tools/dsymutil/X86/dwarf5.test
The file was modifiedllvm/include/llvm/DWARFLinker/DWARFLinker.h
The file was modifiedllvm/lib/DWARFLinker/DWARFLinker.cpp
The file was addedllvm/test/tools/dsymutil/Inputs/private/tmp/dwarf5/dwarf5.out
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.cpp
The file was modifiedllvm/include/llvm/DWARFLinker/DWARFLinkerCompileUnit.h
The file was addedllvm/test/tools/dsymutil/Inputs/private/tmp/dwarf5/dwarf5.o
The file was modifiedllvm/include/llvm/DWARFLinker/DWARFStreamer.h
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.h
Commit 0b99385e151c7cb674d6d29acfe92680f7148434 by jianzhouzh
[MSan] Partially revert some changes from D94552

Because of line 55, actually aligned_beg always equals to beg.
The file was modifiedcompiler-rt/lib/msan/msan_poisoning.cpp
Commit 8f8c207b8f2e69be652ef7afa30a92312bbb2bf0 by serguei.katkov
[Verifier] Add tied-ness verification to statepoint intsruction

Reviewers: reames, dantrushin
Reviewed By: reames, dantrushin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D94483
The file was addedllvm/test/MachineVerifier/verifier-statepoint.mir
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
Commit 3aeb30d1a68a76616c699587e07a7d8880c29d1c by david.green
[ARM] Additional tests for different interleaving patterns. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-shuffleext.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vcvt.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vmovnstore.ll
Commit 141906fa149ffaa37bb5b65e9890ab1f0f3effd5 by grimar
[llvm-readelf/obj] - Add support of multiple SHT_SYMTAB_SHNDX sections.

Currently we don't support multiple SHT_SYMTAB_SHNDX sections
and the DT_SYMTAB_SHNDX tag currently.

This patch implements it and fixes the
https://bugs.llvm.org/show_bug.cgi?id=43991.

I had to introduce the `struct DataRegion` to ELF.h,
it is used to represent a region that might have no known size.
It is needed, because we don't know the size of the extended
section indices table when it is located via DT_SYMTAB_SHNDX.
In this case we still want to validate that we don't read
past the end of the file.

Differential revision: https://reviews.llvm.org/D92923
The file was modifiedllvm/test/tools/obj2yaml/ELF/sht-symtab-shndx.yaml
The file was modifiedllvm/test/Object/invalid.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-plt.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/section-symbols.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/dynamic-tags.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/symbol-shndx.test
The file was modifiedllvm/include/llvm/Object/ELF.h
The file was modifiedllvm/test/tools/yaml2obj/ELF/sht-symtab-shndx.yaml
The file was modifiedllvm/unittests/Object/ELFTest.cpp
The file was addedllvm/test/tools/llvm-readobj/ELF/symtab-shndx.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/dyn-symbols.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-got.test
Commit c29ca8551afff316976c2befcd65eeef53798499 by david.green
[ARM] Update isVMOVNOriginalMask to handle single input shuffle vectors

The isVMOVNOriginalMask was previously only checking for two input
shuffles that could be better expanded as vmovn nodes. This expands that
to single input shuffles that will later be legalized to multiple
vectors.

Differential Revision: https://reviews.llvm.org/D94189
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vmovnstore.ll
Commit 6d3098e7ff968ad7d3033d7751af05a1fcd2ed9b by grimar
[obj2yaml,yaml2obj] - Refine how we set/dump the sh_entsize field.

This reuses the code from yaml2obj (moves it to ELFYAML.h).
With it we can set the `sh_entsize` in a single place in `obj2yaml`.

Note that it also fixes a bug of `yaml2obj`: we do not
set the `sh_entsize` field for the `SHT_ARM_EXIDX` section properly.

Differential revision: https://reviews.llvm.org/D93858
The file was modifiedllvm/test/Object/obj2yaml.test
The file was modifiedllvm/test/tools/obj2yaml/ELF/mips-abi-flags.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
The file was modifiedllvm/test/tools/obj2yaml/ELF/versym-section.yaml
The file was modifiedllvm/include/llvm/ObjectYAML/ELFYAML.h
The file was modifiedllvm/test/tools/obj2yaml/ELF/call-graph-profile-section.yaml
The file was modifiedllvm/test/tools/obj2yaml/ELF/sht-symtab-shndx.yaml
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
The file was modifiedllvm/test/tools/yaml2obj/ELF/arm-exidx-section.yaml
Commit cbea6737d5130724c7c8cf8ee4ccf1c3dd099450 by andrzej.warzynski
[clang][driver] Restore the original help text for `-I`

The help text for `-I` was recently expanded in [1]. The expanded
version focuses on explaining the semantics of `-I` in Clang. We are now
in the process of adding support for `-I` in Flang and this new
description is incompatible with the semantics of `-I` in Flang. This
was brought up in this review:
  * https://reviews.llvm.org/D93453

This patch reverts the original change in Options.td. This way the help
text for `-I` remains generic enough so that it applies to both Clang
and Flang.

The expanded description of `-I` from [1] is moved to the
`DocBrief` field for `-I`. This field is prioritised over the help text
when generating ClangCommandLineReference.rst, so the user facing
documentation for Clang retains the expanded description:
  * https://clang.llvm.org/docs/ClangCommandLineReference.html
`DocBrief` fields are currently not used in Flang.

As requested in the reviews, the help text and the expanded description
are slightly refined.

[1] Commit: 8dd4e3ceb804a58bcf25e6856fc6fde5e1995a66

Differential Revision: https://reviews.llvm.org/D94169
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/docs/ClangCommandLineReference.rst
Commit f638c2eb4ee6d0a0bd0e80cd305ad93e382db8f5 by flo
[LTO] Replace anonymous namespace with static functions (NFC).

Only class declarations should be inside anonymous namespaces
(https://llvm.org/docs/CodingStandards.html#anonymous-namespaces)

Instead of using a anonymous namespace, just mark the functions in it as
static (some of them already were).

This simplifies the diff for D94486.
The file was modifiedllvm/lib/LTO/LTOBackend.cpp
Commit 4cd48535eca06245c89a9158844bb177c6f8eb63 by david.sherwood
[NFC][InstructionCost] Use InstructionCost in Transforms/Scalar/RewriteStatepointsForGC.cpp

In places where we calculate costs using TTI.getXXXCost() interfaces
I have changed the code to use InstructionCost instead of unsigned.
The change is non functional since InstructionCost behaves in the
same way as an integer for valid costs. Currently the getXXXCost()
functions used in this file do not return invalid costs.

See this patch for the introduction of the type: https://reviews.llvm.org/D91174
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html

Differential revision: https://reviews.llvm.org/D94484
The file was modifiedllvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
Commit 3122c66aee7b709046753873c4e94db73742b3de by joe.ellis
[AArch64][SVE] Remove chains of unnecessary SVE reinterpret intrinsics

This commit extends SVEIntrinsicOpts::optimizeConvertFromSVBool to
identify and remove longer chains of redundant SVE reintepret
intrinsics. For example, the following chain of redundant SVE
reinterprets is now recognised as redundant:

    %a = <vscale x 2 x i1>
    %1 = <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool(<vscale x 2 x i1> %a)
    %2 = <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool(<vscale x 16 x i1> %1)
    %3 = <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool(<vscale x 4 x i1> %2)
    %4 = <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool(<vscale x 16 x i1> %3)
    %5 = <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool(<vscale x 4 x i1> %4)
    %6 = <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool(<vscale x 16 x i1> %5)
    ret <vscale x 2 x i1> %6

and will be replaced with:

    ret <vscale x 2 x i1> %a

Eliminating these can sometimes mean emitting fewer unnecessary
loads/stores when lowering to assembly.

Differential Revision: https://reviews.llvm.org/D94074
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsic-opts-reinterpret.ll
The file was modifiedllvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
Commit 0f59d099571d3d803b54e2ce06aa94babb9b26db by llvm-dev
[X86][AVX] combineVectorSignBitsTruncation - limit AVX512 truncations to 128-bits (PR48727)

rG73a44f437bf1 result in 256-bit packss/packus ops with additional shuffles that shuffle combining can sometimes try to convert back into a truncation.
The file was addedllvm/test/CodeGen/X86/pr48727.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-pack-256.ll
Commit ad85e3967067154a579f7989ce0e736f8cd56be9 by cullen.rhodes
[SVE] Add ISel pattern for addvl

Reviewed By: cameron.mcinally

Differential Revision: https://reviews.llvm.org/D94504
The file was modifiedllvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-gep.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
The file was modifiedllvm/test/CodeGen/AArch64/split-vector-insert.ll
Commit 1854594b80b444dc21b830b51e53e05d38fc7d60 by matthew.malcomson
Hwasan InitPrctl check for error using internal_iserror

When adding this function in https://reviews.llvm.org/D68794 I did not
notice that internal_prctl has the API of the syscall to prctl rather
than the API of the glibc (posix) wrapper.

This means that the error return value is not necessarily -1 and that
errno is not set by the call.

For InitPrctl this means that the checks do not catch running on a
kernel *without* the required ABI (not caught since I only tested this
function correctly enables the ABI when it exists).
This commit updates the two calls which check for an error condition to
use `internal_iserror`.  That function sets a provided integer to an
equivalent errno value and returns a boolean to indicate success or not.

Tested by running on a kernel that has this ABI and on one that does
not.  Verified that running on the kernel without this ABI the current
code prints the provided error message and does not attempt to run the
program.  Verified that running on the kernel with this ABI the current
code does not print an error message and turns on the ABI.
All tests done on an AArch64 Linux machine.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D94425
The file was modifiedcompiler-rt/lib/hwasan/hwasan_linux.cpp
Commit ceb9379a90f5a320d19f5694ef00b4d1164fa7d6 by n.james93
[ADT] Fix join_impl using the wrong size when calculating total length

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D83305
The file was modifiedllvm/include/llvm/ADT/StringExtras.h
Commit ada96fa62179d2addd6c85a02381f1353fe7a2d1 by flo
[LTO] Add test to ensure objc-arc-contract is executed.

This test adds additional test coverage for upcoming refactorings.
The file was addedllvm/test/LTO/X86/objc-arc-contract.ll
Commit af1bb4bc823f823df9869d354f639ee86b83d747 by n.james93
Fix build errors after ceb9379a9

For some reason some builds dont like the arrow operator access. using the deref then access should fix the issue.

/home/buildbots/ppc64le-flang-mlir-rhel-test/ppc64le-flang-rhel-clang-build/llvm-project/llvm/include/llvm/ADT/iterator.h:171:34: error: taking the address of a temporary object of type 'llvm::StringRef' [-Waddress-of-temporary]
  PointerT operator->() { return &static_cast<DerivedT *>(this)->operator*(); }
                                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/buildbots/ppc64le-flang-mlir-rhel-test/ppc64le-flang-rhel-clang-build/llvm-project/llvm/include/llvm/ADT/StringExtras.h:387:13: note: in instantiation of member function 'llvm::iterator_facade_base<llvm::mapped_iterator<mlir::tblgen::TypeParameter *, (lambda at /home/buildbots/ppc64le-flang-mlir-rhel-test/ppc64le-flang-rhel-clang-build/llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:414:19), llvm::StringRef>, std::random_access_iterator_tag, llvm::StringRef, long, llvm::StringRef *, llvm::StringRef &>::operator->' requested here
    Len += I->size();
The file was modifiedllvm/include/llvm/ADT/StringExtras.h
Commit c6e341c89957db31432baffb72ee015f37d8c48d by dave
Revert "[dsymutil] Warn on timestmap mismatch between object file and debug map"

This reverts commit e5553b9a6ab9f02f382a31cc5117b52c3bfaf77a.

Tests are not allowed to modify the source. Please figure out a way to
use %t rather than dynamically modifying the inputs.
The file was modifiedllvm/test/tools/dsymutil/X86/swift-ast-x86_64.test
The file was modifiedllvm/tools/dsymutil/BinaryHolder.h
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.cpp
The file was removedllvm/test/tools/dsymutil/Inputs/basic.macho.x86_64.o
The file was modifiedllvm/test/tools/dsymutil/debug-map-parsing.test
The file was modifiedllvm/tools/dsymutil/BinaryHolder.cpp
Commit 2170e0ee60db638175a8c57230d46fbaafa06d4c by kerry.mclaughlin
[SVE][CodeGen] CTLZ, CTTZ & CTPOP operations (predicates)

Canonicalise the following operations in getNode() for predicate types:
- CTLZ(Pred)  -> bitwise_NOT(Pred)
- CTTZ(Pred)  -> bitwise_NOT(Pred)
- CTPOP(Pred) -> Pred

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D94428
The file was addedllvm/test/CodeGen/AArch64/sve-bit-counting-pred.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit f8cece18630575dccd62ba6a12f21acf5fd38c26 by markus.lavin
[ValueTracking] Fix one s/dyn_cast/dyn_cast_or_null/

Handle if Constant::getAggregateElement() returns nullptr in
canCreateUndefOrPoison().

Differential Revision: https://reviews.llvm.org/D94494
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit 704831fe1f1f02e41ab7440a6f6c2c390ec183b1 by thakis
Revert "Hwasan InitPrctl check for error using internal_iserror"

This reverts commit 1854594b80b444dc21b830b51e53e05d38fc7d60.
See https://reviews.llvm.org/D94425#2495621
The file was modifiedcompiler-rt/lib/hwasan/hwasan_linux.cpp
Commit d307d892ade9384a5d8b40ddb6a9c0b2dffbdb81 by Dávid Bolvanský
[Tests] Added test for memcpy loop idiom recognization
The file was addedllvm/test/Transforms/LoopIdiom/memcpy.ll
Commit 0a0ee7f5a5af0f5dae65452f649ab665e787e7d6 by llvm-dev
[X86] canonicalizeShuffleMaskWithHorizOp - minor refactor to support multiple src ops. NFCI.

canonicalizeShuffleMaskWithHorizOp currently only supports shuffles with 1 or 2 sources, but PR41813 will require us to support higher numbers of sources.

This patch just generalizes the initial setup stages to ensure all src ops are the same type and opcode and then will continue to early out if we have more than 2 sources.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit ab577807165c45abfbadc117125ec7275cdcc0cf by gchatelet
[libc] Refresh benchmark progress bar when needed.
The file was modifiedlibc/benchmarks/LibcMemoryBenchmarkMain.cpp
Commit 7c77b536efdd953d6d97bffbd9ca320c517b26d7 by sven.vanhaastregt
[OpenCL] Improve OpenCL operator tests

Extend testing of increment/decrement operators and make sure these
operators are tested in only one dedicated test file.

Rename logical-ops.cl to operators.cl, as it was already containing
more than just logical operators.

Add testing for the remainder operator on floating point types.
The file was addedclang/test/SemaOpenCL/operators.cl
The file was modifiedclang/test/SemaOpenCL/invalid-vector-literals.cl
The file was removedclang/test/SemaOpenCL/logical-ops.cl
The file was modifiedclang/test/SemaOpenCL/vector_inc_dec_ops.cl
Commit b7b1e8c37a920fcf2755a99fbf78cc570cf76c60 by flo
[X86] Add tests for rv_marker lowering.

Precommit tests for D94597.
The file was addedllvm/test/CodeGen/X86/call-rv-marker.ll
Commit 3bc7555ffac0a803e44c4b1462e0c4c5eee865ea by antiagainst
[mlir][linalg] Use attributes in named ops' indexing maps

This commit adds support for parsing attribute uses in indexing
maps. These attribute uses are represented as affine symbols in
the resultant indexing maps because we can only know their
concrete value (which are coming from op attributes and are
constants) for specific op instances. The `indxing_maps()`
calls are synthesized to read these attributes and create affine
constants to replace the placeholder affine symbols and simplify.

Depends on D94240

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D94335
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/docs/Dialects/Linalg.md
Commit 90164ba957a2532daef6515d7114af69eca025a7 by sam.mccall
[clangd] Split out a base class for delegating GlobalCompilationDatabases. NFC

This prepares for adding another delegatable method (blockUntilIdle) to GCDB.
The file was modifiedclang-tools-extra/clangd/GlobalCompilationDatabase.h
The file was modifiedclang-tools-extra/clangd/QueryDriverDatabase.cpp
The file was modifiedclang-tools-extra/clangd/GlobalCompilationDatabase.cpp
Commit dda60035e9f0769c8907cdf6561489e0435c2275 by nicholas.guy
[AArch64] Attempt to sink mul operands

Following on from D91255, this patch is responsible for sinking relevant mul
operands to the same block so that umull/smull instructions can be correctly
generated by the mul combine implemented in the aforementioned patch.

Differential revision: https://reviews.llvm.org/D91271
The file was addedllvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit d55d592a921f1cd6a922bff0000f6662f8722d9c by Matthew.Arsenault
GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper

This fixes double printing of insertion debug messages in the
legalizer.

Try to cleanup usage of observers. Currently the use of observers is
pretty hard to follow and it's not clear what is responsible for
them. Observers are referenced in 3 places:

1. In the MachineFunction
2. In the MachineIRBuilder
3. In the LegalizerHelper

The observers in the MachineFunction and MachineIRBuilder are both
called only on insertions, and are redundant with each other. The
source of the double printing was the same observer was added to both
the MachineFunction, and the MachineIRBuilder. One of these references
needs to be removed. Arguably observers in general should be fully
removed from one or the other, but it may be useful to have a local
observer in the MachineIRBuilder that is not added to the function's
observers. Alternatively, the wrapper observer could manage a local
observer in one place.

The LegalizerHelper only ever calls the observer on changing/changed
instructions, and never insertions. Logically these are two different
types of observers, for changes and for insertions.

Additionally, some places used the GISelObserverWrapper when they only
needed a single observer they could use directly.

Setting the observer in the LegalizerHelper constructor is not
flexible enough if the LegalizerHelper is constructed anywhere outside
the one used by the legalizer. AMDGPU calls the LegalizerHelper in
RegBankSelect, and needs to use a local observer to apply the regbank
to newly created instructions. Currently it accomplishes this by
constructing a local MachineIRBuilder. I'm trying to move the
MachineIRBuilder to be owned/maintained by the RegBankSelect pass
itself, but the locally constructed LegalizerHelper would reset the
observer.

Mips also has a special case use of the LegalizationArtifactCombiner
in applyMappingImpl; I think we do need to run the artifact combiner
during RegBankSelect, but in a more consistent way outside of
applyMappingImpl.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was modifiedllvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
Commit 350c0552c66bf0ca6907b6aa8cede425dedde516 by kai.wang
[NFC][RISCV] Add double type in RISC-V V CodeGen test cases for RV32.

Differential Revision: https://reviews.llvm.org/D94584
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
Commit 4e8e888905a4258932dcb593a5531a6329cc821a by muhammad.asif.manzoor
[AArch64][GlobalISel] Add support for FCONSTANT of FP128 type

Add support for G_FCONSTANT of FP128 (Quadruple precision) type.
It replaces the constant by emitting a load with a constant pool entry.

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D94437
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-fp128-fconstant.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Commit 07b6aeb5685fa6474cbeae797ebc5ea1f17da0f7 by sbc
[lld][WebAssembly] Fix for TLS + --relocatable

When running in `-r/--relocatable` we output relocations but the
new TLS relocations type was missing from `ObjFile::calcNewAddend`
causing this combination of inputs/flags to crash the linker.

Also avoid creating tls variables in relocatable mode.  These variables
are only needed when linking final executables.

Fixes: https://github.com/emscripten-core/emscripten/issues/12934
Fixes: PR48506

Differential Revision: https://reviews.llvm.org/D93554
The file was modifiedlld/wasm/Driver.cpp
The file was modifiedlld/test/wasm/tls-no-shared.s
The file was modifiedlld/test/wasm/tls.s
The file was modifiedlld/wasm/Writer.cpp
The file was modifiedlld/wasm/InputFiles.cpp
Commit f0abe2aeaca76a24b1e17295ab797068c057a15d by Xiangling.Liao
[Frontend] Add pragma align natural and sort out pragma pack stack effect

- Implemente the natural align for XL on AIX
- Sort out pragma pack stack effect
- Add -fxl-pragma-stack option to enable XL on AIX pragma stack effect

Differential Revision: https://reviews.llvm.org/D87702
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/Sema/SemaAttr.cpp
The file was addedclang/test/Layout/aix-power-natural-interaction.cpp
The file was addedclang/test/Driver/aix-pragma-pack.c
The file was addedclang/test/PCH/aix-pragma-pack.c
The file was modifiedclang/include/clang/Serialization/ASTWriter.h
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was modifiedclang/include/clang/Serialization/ASTReader.h
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/test/Layout/aix-double-struct-member.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/lib/Parse/ParsePragma.cpp
The file was addedclang/test/Sema/aix-pragma-pack-and-align.c
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/lib/Serialization/ASTWriter.cpp
The file was modifiedclang/lib/AST/RecordLayoutBuilder.cpp
Commit a957634942a48c963a8ed99b1bb90f7b985a3602 by jhuber6
[OpenMP] Add documentation for error messages and release notes

Add extra information to the runtime page describing the error messages and add information to the release notes for clang 12.0

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D94562
The file was modifiedopenmp/docs/ReleaseNotes.rst
The file was modifiedopenmp/docs/design/Runtimes.rst
Commit 4fe17ada55ade9b77e18521dae0985cb4a88f6c4 by nawrin.sultana
[OpenMP] Fix hierarchical barrier

Hierarchical barrier is an experimental barrier algorithm that uses aspects
of machine hierarchy to define the barrier tree structure. This patch fixes
offset calculation in hierarchical barrier. The offset is used to store info
on a flag about sleeping threads waiting on a location stored in the flag.
This commit also fixes a potential deadlock in hierarchical barrier when
using infinite blocktime by adjusting the offset value of leaf kids so that
it matches the value of leaf state. It also adds testing of default barriers
with infinite blocktime, and also tests hierarchical barrier algorithm with
both default and infinite blocktime.

Patch by Terry Wilmarth and Nawrin Sultana.

Differential Revision: https://reviews.llvm.org/D94241
The file was modifiedopenmp/runtime/test/barrier/omp_barrier.c
The file was modifiedopenmp/runtime/src/kmp_barrier.cpp
Commit 66d5994bd38a9be4a0c05de2b69f88b64e6845ce by sam.mccall
[clangd] Explicitly avoid background-indexing the same file twice.

This used to implicitly never happen due to only discovering each CDB
once.

We may want to carefully support reindexing one day, but we need to do
it carefully (tricky tradeoffs) and it would need further support in
background indexer.

Making this explicit here rather than just turning off rebroadcast in
background index for a few reasons:
- allows *new* files in the same CDB to be indexed
- relying on bugs-at-a-distance cancelling each other out is bound to bite us
- gets us closer to actually supporting reindexing, which requires similar tracking

Differential Revision: https://reviews.llvm.org/D94503
The file was modifiedclang-tools-extra/clangd/index/Background.cpp
The file was modifiedclang-tools-extra/clangd/index/Background.h
The file was modifiedclang-tools-extra/clangd/index/BackgroundQueue.cpp
The file was modifiedclang-tools-extra/clangd/unittests/BackgroundIndexTests.cpp
Commit 466acd694861138997d668a3f9cb29aa87bd316e by sam.mccall
[clangd] Avoid reallocating buffers for each message read:

- reuse std::string we read messages into
- when reading line-wise, use SmallVector<128> and read in chunks of 128
   (this affects headers, which are short, and tests, which don't matter)

Differential Revision: https://reviews.llvm.org/D93653
The file was modifiedclang-tools-extra/clangd/JSONTransport.cpp
Commit e433ca28ec923929efe4f6babb8d33b4e6673ac1 by spatel
[SLP] add reduction test for FMF; NFC
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
Commit 17863614da1efbe61e91c9f6f08ad80cdd257bb4 by nikita.ppv
[InstCombine] Fold select -> and/or using impliesPoison

We can fold a ? b : false to a & b if is_poison(b) implies that
is_poison(a), at which point we're able to reuse all the usual fold
on ands. In particular, this covers the very common case of
icmp X, C && icmp X, C'. The same applies to ors.

This currently only has an effect if the
-instcombine-unsafe-select-transform=0 option is set.

Differential Revision: https://reviews.llvm.org/D94550
The file was modifiedllvm/test/Transforms/InstCombine/select-and-or.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit a4f386688239b06e09f28fd31f93bf761aa9c76f by usx
[clangd] Remove "decision-forest-base" experimental flag.

The value of this flag can only be fine tuned by using A/B testing on large
user base.
We do not expect individual users to use and fine tune this flag.

Differential Revision: https://reviews.llvm.org/D94513
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp
Commit 0bbc6a6bb643af69baaf85f7f380dbcfe1f5ad54 by sam.mccall
[clangd] Remove some old CodeCompletion options that are never (un)set.  NFC
The file was modifiedclang-tools-extra/clangd/CodeComplete.h
The file was modifiedclang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
The file was modifiedclang-tools-extra/clangd/CodeComplete.cpp
Commit 05b1a15f703c3e01f4123424700bc37188af8af1 by andrew.litteken
[IROutliner] Adapting to hoisted bitcasts in CodeExtractor

In commit 700d2417d8281ea56dfd7ac72d1a1473d03d2d59 the CodeExtractor
was updated so that bitcasts that have lifetime markers that beginning
outside of the region are deduplicated outside the region and are not
used as an output.  This caused a discrepancy in the IROutliner, where
in these cases there were arguments added to the aggregate function
that were not needed causing assertion errors.

The IROutliner queries the CodeExtractor twice to determine the inputs
and outputs, before and after `findAllocas` is called with the same
ValueSet for the outputs causing the duplication. This has been fixed
with a dummy ValueSet for the first call.

However, the additional bitcasts prevent us from using the same
similarity relationships that were previously defined by the
IR Similarity Analysis Pass. In these cases, we check whether the
initial version of the region being analyzed for outlining is still the
same as it was previously.  If it is not, i.e. because of the additional
bitcast instructions from the CodeExtractor, we discard the region.

Reviewers: yroux

Differential Revision: https://reviews.llvm.org/D94303
The file was modifiedllvm/lib/Transforms/IPO/IROutliner.cpp
The file was addedllvm/test/Transforms/IROutliner/outlining-bitcasts.ll
Commit 48d2068fb738302b9fba91c9bf8e4b051c3909eb by Jonas Devlieghere
[dsymutil] Warn on timestmap mismatch between object file and debug map

This re-lands e5553b9a6ab9 with two small fixes to the tests:

- Don't touch the source directory in debug-map-parsing.test but
   instead copy everything over in a temporary directory in
   timestamp-mismatch.test.
- Don't redirect stderr to stdout to avoid the output getting
   intertwined in extern-alias.test.
The file was modifiedllvm/test/tools/dsymutil/debug-map-parsing.test
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.cpp
The file was addedllvm/test/tools/dsymutil/X86/timestamp-mismatch.test
The file was modifiedllvm/tools/dsymutil/BinaryHolder.cpp
The file was modifiedllvm/test/tools/dsymutil/X86/swift-ast-x86_64.test
The file was modifiedllvm/test/tools/dsymutil/ARM/extern-alias.test
The file was modifiedllvm/tools/dsymutil/BinaryHolder.h
Commit cbbfc8258615bc971a54c6287abe33c4215d2eac by llvm-dev
[X86][SSE] canonicalizeShuffleMaskWithHorizOp - simplify shuffle(HOP(HOP(X,Y),HOP(Z,W))) style chains.

See if we can remove the shuffle by resorting a HOP chain so that the HOP args are pre-shuffled.

This initial version just handles (the most common) v4i32/v4f32 hadd/hsub reduction patterns - future work can extend this to v8i16 types plus PACK chains (2f64 HADD/HSUB should already be handled in the half-lane combine code later on).
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
Commit efb6e45d2be8e3e0843bdc4c2766e6910083c08e by llvm-dev
[X86][AVX] Add test for another 'reverse HADD' pattern mentioned in PR41813
The file was modifiedllvm/test/CodeGen/X86/haddsub-4.ll
Commit 993c488ed2b347011d9d71990af38a82aaf5bdf5 by llvm-dev
[DAG] visitVECTOR_SHUFFLE - use all_of to check for all-undef shuffle mask. NFCI.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 60fda8ebb6dc4e2ac1cc181c0ab8019c4309cb22 by samuel.tebbs
[ARM] Add a pass that re-arranges blocks when there is a backwards WLS branch

Blocks can be laid out such that a t2WhileLoopStart branches backwards. This is forbidden by the architecture and so it fails to be converted into a low-overhead loop. This new pass checks for these cases and moves the target block, fixing any fall-through that would then be broken.

Differential Revision: https://reviews.llvm.org/D92385
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was addedllvm/lib/Target/ARM/ARMBlockPlacement.cpp
The file was modifiedllvm/lib/Target/ARM/CMakeLists.txt
The file was modifiedllvm/lib/Target/ARM/ARM.h
The file was addedllvm/test/CodeGen/Thumb2/block-placement.mir
Commit 14f322f074b933af1e26bf6288b88ec2e7c3a551 by llvmgnsyncbot
[gn build] Port 60fda8ebb6d
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn
Commit a50bb84ec0c2d47a2a7403ad29842ca48cd6b828 by pklausler
[flang] Fix classification of shape inquiries in specification exprs

In some contexts, including the motivating case of determining whether
the expressions that define the shape of a variable are "constant expressions"
in the sense of the Fortran standard, expression rewriting via Fold()
is not necessary, and should not be required.  The inquiry intrinsics LBOUND,
UBOUND, and SIZE work correctly now in specification expressions and are
classified correctly as being constant expressions (or not).  Getting this right
led to a fair amount of API clean-up as a consequence, including the
folding of shapes and TypeAndShape objects, and new APIs for shapes
that do not fold for those cases where folding isn't needed.  Further,
the symbol-testing predicate APIs in Evaluate/tools.h now all resolve any
associations of their symbols and work transparently on use-, host-, and
construct-association symbols; the tools used to resolve those associations have
been defined and documented more precisely, and their clients adjusted as needed.

Differential Revision: https://reviews.llvm.org/D94561
The file was modifiedflang/include/flang/Evaluate/tools.h
The file was modifiedflang/lib/Evaluate/shape.cpp
The file was modifiedflang/test/Semantics/data04.f90
The file was modifiedflang/include/flang/Evaluate/shape.h
The file was modifiedflang/include/flang/Evaluate/fold.h
The file was modifiedflang/lib/Semantics/check-declarations.cpp
The file was modifiedflang/include/flang/Semantics/tools.h
The file was modifiedflang/lib/Evaluate/tools.cpp
The file was modifiedflang/lib/Semantics/check-do-forall.cpp
The file was modifiedflang/lib/Semantics/semantics.cpp
The file was modifiedflang/include/flang/Evaluate/type.h
The file was modifiedflang/lib/Semantics/resolve-names.cpp
The file was modifiedflang/lib/Evaluate/fold.cpp
The file was modifiedflang/lib/Semantics/tools.cpp
The file was modifiedflang/lib/Evaluate/characteristics.cpp
The file was modifiedflang/include/flang/Evaluate/characteristics.h
The file was modifiedflang/lib/Evaluate/check-expression.cpp
The file was modifiedflang/test/Semantics/shape.f90
The file was modifiedflang/lib/Evaluate/intrinsics.cpp
The file was modifiedflang/lib/Semantics/check-call.cpp
The file was modifiedflang/test/Semantics/resolve44.f90
Commit a2e6506c47b1ab8cb085aa485fd0abf980a47a05 by kparzysz
[Hexagon] Improve legalizing of ISD::SETCC result
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
Commit 123674a816742254debdfcc978026b8107b502d8 by spatel
[SLP] simplify type check for reductions

This is NFC-intended. The 'valid' call allows int/FP/pointers
for other parts of SLP. The difference here is that we can't
reduce pointers.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 166e5c335cbe9f8144a7822ca655dc3352ec9e56 by pklausler
[flang] Do not create HostAssoc symbols in derived type scopes

When needed due to a specification expression in a derived type,
the host association symbols should be created in the surrounding
subprogram's scope instead.

Differential Revision: https://reviews.llvm.org/D94567
The file was modifiedflang/lib/Semantics/resolve-names.cpp
Commit b3154d11bc6dee59e581b731b7561f1ebab3aed6 by wlei
[CSSPGO][llvm-profgen] Pseudo probe decoding and disassembling

This change implements pseudo probe decoding and disassembling for llvm-profgen/CSSPGO. Please see https://groups.google.com/g/llvm-dev/c/1p1rdYbL93s and https://reviews.llvm.org/D89707 for more context about CSSPGO and llvm-profgen.

**ELF section format**
Please see the encoding patch(https://reviews.llvm.org/D91878) for more details of the format, just copy the example here:

Two section(`.pseudo_probe_desc` and  `.pseudoprobe` ) is emitted in ELF to support pseudo probe.
The format of `.pseudo_probe_desc` section looks like:

```
.section   .pseudo_probe_desc,"",@progbits
.quad   6309742469962978389  // Func GUID
.quad   4294967295           // Func Hash
.byte   9                    // Length of func name
.ascii  "_Z5funcAi"          // Func name
.quad   7102633082150537521
.quad   138828622701
.byte   12
.ascii  "_Z8funcLeafi"
.quad   446061515086924981
.quad   4294967295
.byte   9
.ascii  "_Z5funcBi"
.quad   -2016976694713209516
.quad   72617220756
.byte   7
.ascii  "_Z3fibi"
```

For each `.pseudoprobe` section, the encoded binary data consists of a single function record corresponding to an outlined function (i.e, a function with a code entry in the `.text` section). A function record has the following format :

```
FUNCTION BODY (one for each outlined function present in the text section)
    GUID (uint64)
        GUID of the function
    NPROBES (ULEB128)
        Number of probes originating from this function.
    NUM_INLINED_FUNCTIONS (ULEB128)
        Number of callees inlined into this function, aka number of
        first-level inlinees
    PROBE RECORDS
        A list of NPROBES entries. Each entry contains:
          INDEX (ULEB128)
          TYPE (uint4)
            0 - block probe, 1 - indirect call, 2 - direct call
          ATTRIBUTE (uint3)
            reserved
          ADDRESS_TYPE (uint1)
            0 - code address, 1 - address delta
          CODE_ADDRESS (uint64 or ULEB128)
            code address or address delta, depending on ADDRESS_TYPE
    INLINED FUNCTION RECORDS
        A list of NUM_INLINED_FUNCTIONS entries describing each of the inlined
        callees.  Each record contains:
          INLINE SITE
            GUID of the inlinee (uint64)
            ID of the callsite probe (ULEB128)
          FUNCTION BODY
            A FUNCTION BODY entry describing the inlined function.
```

**Disassembling**
A switch `--show-pseudo-probe` is added to use along with `--show-disassembly` to print disassembly code with pseudo probe directives.

For example:
```
00000000002011a0 <foo2>:
  2011a0: 50                    push   rax
  2011a1: 85 ff                 test   edi,edi
  [Probe]:  FUNC: foo2  Index: 1  Type: Block
  2011a3: 74 02                 je     2011a7 <foo2+0x7>
  [Probe]:  FUNC: foo2  Index: 3  Type: Block
  [Probe]:  FUNC: foo2  Index: 4  Type: Block
  [Probe]:  FUNC: foo   Index: 1  Type: Block  Inlined: @ foo2:6
  2011a5: 58                    pop    rax
  2011a6: c3                    ret
  [Probe]:  FUNC: foo2  Index: 2  Type: Block
  2011a7: bf 01 00 00 00        mov    edi,0x1
  [Probe]:  FUNC: foo2  Index: 5  Type: IndirectCall
  2011ac: ff d6                 call   rsi
  [Probe]:  FUNC: foo2  Index: 4  Type: Block
  2011ae: 58                    pop    rax
  2011af: c3                    ret
```

**Implementation**
- `PseudoProbeDecoder` is added in ProfiledBinary as an infra for the decoding. It decoded the two section and generate two map: `GUIDProbeFunctionMap` stores all the `PseudoProbeFunction` which is the abstraction of a general function. `AddressProbesMap` stores all the pseudo probe info indexed by its address.
- All the inline info is encoded into binary as a trie(`PseudoProbeInlineTree`) and will be constructed from the decoding. Each pseudo probe can get its inline context(`getInlineContext`) by traversing its inline tree node backwards.

Test Plan:
ninja & ninja check-llvm

Differential Revision: https://reviews.llvm.org/D92334
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
The file was addedllvm/tools/llvm-profgen/PseudoProbe.h
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.cpp
The file was addedllvm/tools/llvm-profgen/PseudoProbe.cpp
The file was addedllvm/test/tools/llvm-profgen/Inputs/inline-cs-pseudoprobe.perfbin
The file was addedllvm/test/tools/llvm-profgen/pseudoprobe-decoding.test
The file was modifiedllvm/tools/llvm-profgen/CMakeLists.txt
Commit 414930b91bfd4196c457120932a1dbaf26db711d by wlei
[CSSPGO][llvm-profgen] Refactor to unify hashable interface for trace sample and context-sensitive counter

As we plan to support both CSSPGO and AutoFDO for llvm-profgen, we will have different kinds of perf sample and different kinds of sample counter(cs/non-cs, with/without pseudo probe) which both need to do aggregation in hash map.  This change implements the hashable interface(`Hashable`) and the unified base class for them to have better extensibility and reusability.

Currently perf trace sample and sample counter with context implemented this `Hashable` and  the class hierarchy is like:

```
| Hashable
           | PerfSample
                          | HybridSample
                          | LBRSample
           | ContextKey
                          | StringBasedCtxKey
                          | ProbeBasedCtxKey
                          | CallsiteBasedCtxKey
           | ...
```

- Class specifying `Hashable` should implement `getHashCode` and `isEqual`. Here we make `getHashCode` a non-virtual function to avoid vtable overhead, so derived class should calculate and assign the base class's HashCode manually. This also provides the flexibility for calculating the hash code incrementally(like rolling hash) during frame stack unwinding
- `isEqual` is a virtual function, which will have perf overhead. In the future, if we redesign a better hash function, then we can just skip this or switch to non-virtual function.
- Added `PerfSample` and `ContextKey` as base class for perf sample and counter context key, leveraging llvm-style RTTI for this.
- Added `StringBasedCtxKey` class extending  `ContextKey` to use string as context id.
- Refactor `AggregationCounter` to take all kinds of `PerfSample` as key
- Refactor `ContextSampleCounter` to take all kinds of `ContextKey` as key
- Other refactoring work:
- Create a wrapper class `SampleCounter` to wrap `RangeCounter` and `BranchCounter`
- Hoist `ContextId` and `FunctionProfile` out of `populateFunctionBodySamples` and `populateFunctionBoundarySamples` to reuse them in ProfileGenerator

Differential Revision: https://reviews.llvm.org/D92584
The file was modifiedllvm/tools/llvm-profgen/PerfReader.cpp
The file was modifiedllvm/tools/llvm-profgen/PerfReader.h
The file was modifiedllvm/tools/llvm-profgen/ProfileGenerator.h
The file was modifiedllvm/tools/llvm-profgen/ProfileGenerator.cpp
Commit c681400b25a66ae56b74cc1f11ffdc15190a65b8 by wlei
[CSSPGO][llvm-profgen] Virtual unwinding with pseudo probe

This change extends virtual unwinder to support pseudo probe in llvm-profgen. Please refer https://groups.google.com/g/llvm-dev/c/1p1rdYbL93s and https://reviews.llvm.org/D89707 for more context about CSSPGO and llvm-profgen.

**Implementation**

- Added `ProbeBasedCtxKey` derived from `ContextKey` for sample counter aggregation. As we need string splitting to infer the profile for callee function, string based context introduces more string handling overhead, here we just use probe pointer based context.
- For linear unwinding, as inline context is encoded in each pseudo probe, we don't need to go through each instruction to extract range sharing same inliner. So just record the range for the context.
- For probe based context, we should ignore the top frame probe since it will be extracted from the address range. we defer the extraction in `ProfileGeneration`.
- Added `PseudoProbeProfileGenerator` for pseudo probe based profile generation.
- Some helper function to get pseduo probe info(call probe, inline context) from profiled binary.
- Added regression test for unwinder's output

The pseudo probe based profile generation will be in the upcoming patch.

Test Plan:

ninja & ninja check-llvm

Differential Revision: https://reviews.llvm.org/D92896
The file was modifiedllvm/tools/llvm-profgen/ProfileGenerator.h
The file was modifiedllvm/test/tools/llvm-profgen/Inputs/inline-cs-noprobe.perfscript
The file was addedllvm/test/tools/llvm-profgen/Inputs/noinline-cs-pseudoprobe.perfbin
The file was modifiedllvm/tools/llvm-profgen/PseudoProbe.cpp
The file was modifiedllvm/tools/llvm-profgen/PerfReader.h
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
The file was modifiedllvm/tools/llvm-profgen/PseudoProbe.h
The file was addedllvm/test/tools/llvm-profgen/Inputs/noinline-cs-pseudoprobe.perfscript
The file was addedllvm/test/tools/llvm-profgen/Inputs/inline-cs-pseudoprobe.perfscript
The file was addedllvm/test/tools/llvm-profgen/inline-cs-pseudoprobe.test
The file was modifiedllvm/test/tools/llvm-profgen/Inputs/noinline-cs-noprobe.perfscript
The file was modifiedllvm/tools/llvm-profgen/PerfReader.cpp
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.cpp
The file was addedllvm/test/tools/llvm-profgen/noinline-cs-pseudoprobe.test
The file was modifiedllvm/tools/llvm-profgen/ProfileGenerator.cpp
Commit 33a8466531e68698dc735a0a8dcb97eb41b35ba6 by wlei
[NFC] fix missing SectionName declaration
The file was modifiedllvm/tools/llvm-profgen/PseudoProbe.h
Commit 3bd620d4504915615b8368b20eb9e5c34f3fb779 by tpopp
[mlir] Correct 2 places that result in corrupted conversion rollbacks

This corrects the last 2 issues caught by tests when causing dialect
conversion rollbacks to occur.

Differential Revision: https://reviews.llvm.org/D94623
The file was modifiedmlir/lib/Transforms/Utils/DialectConversion.cpp
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Commit e7a371f9fd0076c187f4cd1a9c7546867faeb19b by alexandre.ganea
[LLD][COFF] Avoid std::vector resizes during type merging

Consistently saves approx. 0.6 sec (out of 18 sec) on a large output (400 MB EXE, 2 GB PDB).

Differential Revision: https://reviews.llvm.org/D94555
The file was modifiedlld/COFF/DebugTypes.cpp
Commit bb72adcaee7db0877e1cecb29d414003bf19ce02 by jeroen.dobbelaere
[NFC] Use correct ssa.copy spelling when referring to the intrinsic

Split out from D91250. Fixes wrong ssa_copy naming.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D94310
The file was modifiedllvm/docs/LangRef.rst
Commit f4f158b2f89e16ee7068d6292d2d46457d6932bb by ajcbik
[mlir][sparse] add vectorization strategies to sparse compiler

Similar to the parallelization strategies, the vectorization strategies
provide control on what loops should be vectorize. Unlike the parallel
strategies, only innermost loops are considered, but including reductions,
with the control of vectorizing dense loops only or dense and sparse loops.

The vectorized loops are always controlled by a vector mask to avoid
overrunning the iterations, but subsequent vector operation folding removes
redundant masks and replaces the operations with more efficient counterparts.
Similarly, we will rely on subsequent loop optimizations to further optimize
masking, e.g. using an unconditional full vector loop and scalar cleanup loop.

The current strategy already demonstrates a nice interaction between the
sparse compiler and all prior optimizations that went into the vector dialect.

Ongoing discussion at:
https://llvm.discourse.group/t/mlir-support-for-sparse-tensors/2020/10

Reviewed By: penpornk

Differential Revision: https://reviews.llvm.org/D94551
The file was addedmlir/test/Dialect/Linalg/sparse_vector.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
The file was modifiedmlir/test/lib/Transforms/TestSparsification.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
Commit 01c3135850d15c8dce9374eec26dc2d555a87b7f by flo
[LTO] Add test for freestanding LTO option.

This patch adds a test for the -lto-freestanding option, similar to
llvm/test/ThinLTO/X86/tli-nobuiltin.ll.
The file was addedllvm/test/LTO/X86/tli-nobuiltin.ll
Commit 18278ff1aac47d9bffa0231c74277ffc89def13e by tkeith
[flang] Fix accessibility of USEd name in .mod file

If a module specifies default private accessibility, names that have
been use-associated are private by default. This was not reflected in
.mod files.

Differential Revision: https://reviews.llvm.org/D94602
The file was modifiedflang/lib/Semantics/mod-file.cpp
The file was modifiedflang/test/Semantics/modfile03.f90
Commit 4cfccd51335139871cad03ac451a2d27ebfe7761 by michaelrj
[libc][NFC] add macro for fuchsia to switch test backend to zxtest

This moves utils/UnitTest/Test.[h/cpp] to LibcTest.[h/cpp] and adds a
new Test.h that acts as a switcher so that Fuchsia can use the zxtest
backend for running our tests as part of their build.

FuchsiaTest.h is for including fuchsia's zxtest library and anything
else needed to make the tests work under fuchsia (currently just
undefining the isascii macro for the test).

Downstream users, please fix your build instead of reverting.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D94625
The file was modifiedlibc/utils/UnitTest/Test.h
The file was addedlibc/utils/UnitTest/LibcTest.cpp
The file was addedlibc/utils/UnitTest/FuchsiaTest.h
The file was modifiedlibc/utils/UnitTest/CMakeLists.txt
The file was addedlibc/utils/UnitTest/LibcTest.h
The file was removedlibc/utils/UnitTest/Test.cpp
Commit fb98a1be43645c87fff089c4cc9555ca2400268c by kazu
Fix the warnings on unused variables (NFC)
The file was modifiedclang-tools-extra/clangd/AST.cpp
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was modifiedlld/MachO/InputSection.cpp
Commit f711cb9a8ad9fe80dd9f1844dbe15c0e7edb1450 by nikita.ppv
[FuncAttrs] Add additional willreturn tests (NFC)
The file was modifiedllvm/test/Transforms/FunctionAttrs/willreturn.ll
Commit 6077d55381a6aa3e947ef7abdc36a7515c598c8a by flo
[DSE] Add tests with stores of existing values.

This patch pre-commits test cases with dead stores of
existing values for D90328. It also updates a few tests that had such
stores by accident, to preserve the original spirit of those tests.
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-loops.ll
The file was addedllvm/test/Transforms/DeadStoreElimination/MSSA/stores-of-existing-values.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-simple.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-memoryphis.ll
Commit ea8034ec35a9e3d6784d7e6f50617af3d87f6a9f by michaelrj
[libc][NFC] change isblank and iscntrl from implicit casting

isblank and iscntrl were casting an int to a char implicitly and this
was throwing errors under Fuchsia. I've added a static cast to resolve
this issue.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D94634
The file was modifiedlibc/src/ctype/isblank.cpp
The file was modifiedlibc/src/ctype/iscntrl.cpp
Commit 74a42aedfe14938e01d128456c76cede2ccbc26c by i
[test] Add Clang side tests for -fdebug-info-for-profiling

There is currently a driver test but no test for its effect on linkageName & pass pipeline.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D94381
The file was addedclang/test/CodeGenCXX/fdebug-info-for-profiling.cpp
Commit 35debdfcaca10203a67ef3821d272a72d70e0490 by wlei
[NFC] Fix build break by a initializer list converting error
The file was modifiedllvm/tools/llvm-profgen/PseudoProbe.cpp
Commit 82c4153e66fa284729da86a8d6c302d4b8cec86c by jiancai
Revert "[AsmParser] make .ascii support spaces as separators"

This reverts commit e0963ae274be5b071d1e1b00f5e4e019483c09e9. The change
breaks some GDB tests. Revert it while we investigate.
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedllvm/test/MC/AsmParser/directive_ascii.s
Commit 39e6d242378a0b645abbdfc6c02de5ef8dcfb9ed by aeubanks
[NewPM] Only non-trivially loop unswitch at -O3 and for non-optsize functions

This matches the legacy pipeline/pass.

Reviewed By: asbirlea, SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D94559
The file was modifiedllvm/test/Transforms/SimpleLoopUnswitch/ARM/nontrivial-unswitch-cost.ll
The file was modifiedllvm/test/Transforms/SimpleLoopUnswitch/pipeline.ll
The file was modifiedllvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit 7ec8f43659861be42f9d600422678196849b6e90 by craig.topper
[SPARC] Fix fp128 load/stores

The generated code for the split fp128 load/stores was missing a small yet important adjustment to the pointer metadata being fed into `getStore` and `getLoad`, making it out of sync with the effective memory address.
This problem often resulted in instructions being scheduled in the wrong order.

I also took this chance to clean up some "wrong" uses of `getAlignment` as done in D77687.

Thanks @jrtc27 for finding the problem and providing a patch.

Patch by LemonBoy and Jessica Clarke(jrtc27)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94345
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.cpp
The file was addedllvm/test/CodeGen/SPARC/fp128-split.ll
Commit 854f0984f0b7ab9a9a541a4bcda7ea173e4113d3 by dblaikie
Fix llvm::Optional build breaks in MSVC using std::is_trivially_copyable

Current code breaks this version of MSVC due to a mismatch between `std::is_trivially_copyable` and `llvm::is_trivially_copyable` for `std::pair` instantiations.  Hence I was attempting to use `std::is_trivially_copyable` to set `llvm::is_trivially_copyable<T>::value`.

I spent some time root causing an `llvm::Optional` build error on MSVC 16.8.3 related to the change described above:

```
62>C:\src\ocg_llvm\llvm-project\llvm\include\llvm/ADT/BreadthFirstIterator.h(96,12): error C2280: 'llvm::Optional<std::pair<std::pair<unsigned int,llvm::Graph<4>::NodeSubset> *,llvm::Optional<llvm::Graph<4>::ChildIterator>>> &llvm::Optional<std::pair<std::pair<unsigned int,llvm::Graph<4>::NodeSubset> *,llvm::Optional<llvm::Graph<4>::ChildIterator>>>::operator =(const llvm::Optional<std::pair<std::pair<unsigned int,llvm::Graph<4>::NodeSubset> *,llvm::Optional<llvm::Graph<4>::ChildIterator>>> &)': attempting to reference a deleted function (compiling source file C:\src\ocg_llvm\llvm-project\llvm\unittests\ADT\BreadthFirstIteratorTest.cpp)
...
```
The "trivial" specialization of `optional_detail::OptionalStorage` assumes that the value type is trivially copy constructible and trivially copy assignable. The specialization is invoked based on a check of `is_trivially_copyable` alone, which does not imply both `is_trivially_copy_assignable` and `is_trivially_copy_constructible` are true.

[[ https://en.cppreference.com/w/cpp/named_req/TriviallyCopyable | According to the spec ]], a deleted assignment operator does not make `is_trivially_copyable` false. So I think all these properties need to be checked explicitly in order to specialize `OptionalStorage` to the "trivial" version:
```
/// Storage for any type.
template <typename T, bool = std::is_trivially_copy_constructible<T>::value
                          && std::is_trivially_copy_assignable<T>::value>
class OptionalStorage {
```
Above fixed my build break in MSVC, but I think we need to explicitly check `is_trivially_copy_constructible` too since it might be possible the copy constructor is deleted.  Also would be ideal to move over to `std::is_trivially_copyable` instead of the `llvm` namespace verson.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D93510
The file was modifiedllvm/unittests/ADT/OptionalTest.cpp
The file was modifiedllvm/include/llvm/ADT/Optional.h
Commit 86341247c4a2ffa4328945b03e7a05b1c51c3889 by wmi
[NFC] Rename ThinLTOPhase to ThinOrFullLTOPhase and move it from PassBuilder.h
to Pass.h.

In some compiler passes like SampleProfileLoaderPass, we want to know which
LTO/ThinLTO phase the pass is in. Currently the phase is represented in enum
class PassBuilder::ThinLTOPhase, so it is only available in PassBuilder and
it also cannot represent phase in full LTO. The patch extends it to include
full LTO phases and move it from PassBuilder.h to Pass.h, then it is much
easier for PassBuilder to communiate with each pass about current LTO phase.

Differential Revision: https://reviews.llvm.org/D94613
The file was modifiedllvm/include/llvm/Passes/PassBuilder.h
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/include/llvm/Transforms/IPO/SampleProfile.h
The file was modifiedpolly/lib/Support/RegisterPasses.cpp
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
The file was modifiedllvm/include/llvm/Pass.h
Commit ddd03842c3472fedf164274c479272089c426ee5 by paulsson
[SystemZ]  Clear Available set in SystemZPostRASchedStrategy::initialize().

This needs to be done in order to not crash with -misched-cutoff.

Fixes https://bugs.llvm.org/show_bug.cgi?id=45928

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D94383
The file was addedllvm/test/CodeGen/SystemZ/misched-cutoff.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
Commit c82deed6764cbc63966374baf9721331901ca958 by rprichard
[libunwind] Unwind through aarch64/Linux sigreturn frame

An AArch64 sigreturn trampoline frame can't currently be described
in a DWARF .eh_frame section, because the AArch64 DWARF spec currently
doesn't define a constant for the PC register. (PC and LR may need to
be restored to different values.)

Instead, use the same technique as libgcc or github.com/libunwind and
detect the sigreturn frame by looking for the sigreturn instructions:

    mov x8, #0x8b
    svc #0x0

If a sigreturn frame is detected, libunwind restores all the GPRs by
assuming that sp points at an rt_sigframe Linux kernel struct. This
behavior is a fallback mode that is only used if there is no ordinary
unwind info for sigreturn.

If libunwind can't find unwind info for a PC, it assumes that the PC is
readable, and would crash if it isn't. This could happen if:
- The PC points at a function compiled without unwind info, and which
   is part of an execute-only mapping (e.g. using -Wl,--execute-only).
- The PC is invalid and happens to point to unreadable or unmapped
   memory.

In the tests, ignore a failed dladdr call so that the tests can run on
user-mode qemu for AArch64, which uses a stack-allocated trampoline
instead of a vDSO.

Reviewed By: danielkiss, compnerd, #libunwind

Differential Revision: https://reviews.llvm.org/D90898
The file was modifiedlibunwind/include/__libunwind_config.h
The file was modifiedlibunwind/src/UnwindCursor.hpp
The file was modifiedlibunwind/test/signal_unwind.pass.cpp
The file was modifiedlibunwind/test/unwind_leaffunction.pass.cpp
Commit 3de92ca78cd4e180920acc077452f87c44c7d935 by psteinfeld
[flang] Add tests for procedure arguments with implicit interfaces

It's possible to declare an external procedure and then pass it as an
actual argument to a subprogram expecting a procedure argument.  I added
tests for this and added an error message to distinguish passing an
actual argument with an implicit interface from passing an argument with
a mismatched explicit interface.

Differential Revision: https://reviews.llvm.org/D94505
The file was modifiedflang/lib/Semantics/check-call.cpp
The file was modifiedflang/test/Semantics/call09.f90
Commit dfc1901d513e1c5b9472d9b3403ca991b3d4a232 by craig.topper
[RISCV] Custom lower ISD::VSCALE.

This patch custom lowers ISD::VSCALE into a csrr vlenb followed
by a shift right by 3 followed by a multiply by the scale amount.

I've added computeKnownBits support to indicate that the csrr vlenb
always produces 3 trailng bits of 0s so the shift right is "exact".
This allows the shift and multiply sequence to be nicely optimized
into a single shift or removed completely when the scale amount is
a power of 2.

The non power of 2 case multiplying by 24 is still producing
suboptimal code. We could remove the right shift and use a
multiply by 3. Hopefully we can improve DAG combine to fix that
since it's not unique to this sequence.

This replaces D94144.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D94249
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit cd4c55c97402246099ae865a66517a36af5c3a7c by richard
Fix grammar in diagnostic for wrong arity in a structured binding.
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaCXX/cxx1z-decomposition.cpp
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
Commit 336ab2d51dfdd5ca09c2a9c506453db4fe653584 by alexandre.ganea
[Support] On Windows, take the affinity mask into account

The number of hardware threads available to a ThreadPool can be limited if setting an affinity mask.
For example:

> start /B /AFFINITY 0xF lld-link.exe ...

Would let LLD only use 4 hyper-threads.

Previously, there was an outstanding issue on Windows Server 2019 on dual-CPU machines, which was preventing from using both CPU sockets. In normal conditions, when no affinity mask was set, ProcessorGroup::AllThreads was different from ProcessorGroup::UsableThreads. The previous code in llvm/lib/Support/Windows/Threading.inc L201 was improperly assuming those two values to be equal, and consequently was limiting the execution to only one CPU socket.

Differential Revision: https://reviews.llvm.org/D92419
The file was modifiedllvm/include/llvm/Support/Program.h
The file was modifiedllvm/lib/Support/Program.cpp
The file was modifiedllvm/lib/Support/Windows/Program.inc
The file was modifiedllvm/lib/Support/Windows/Threading.inc
The file was modifiedllvm/unittests/Support/ThreadPool.cpp
The file was modifiedllvm/lib/Support/Unix/Program.inc
Commit ff40fb07ad6309131c2448ca00572a078c7a2d59 by esme.yi
[PowerPC] Try to fold sqrt/sdiv test results with the branch.

Summary: The patch tries to fold sqrt/sdiv test node, i.g FTSQRT, XVTDIVDP, and the branch, i.e br_cc if they meet these patterns:
(br_cc seteq, (truncateToi1 SWTestOp), 0) -> (BCC PRED_NU, SWTestOp)
(br_cc seteq, (and SWTestOp, 2), 0) -> (BCC PRED_NE, SWTestOp)
(br_cc seteq, (and SWTestOp, 4), 0) -> (BCC PRED_LE, SWTestOp)
(br_cc seteq, (and SWTestOp, 8), 0) -> (BCC PRED_GE, SWTestOp)
(br_cc setne, (truncateToi1 SWTestOp), 0) -> (BCC PRED_UN, SWTestOp)
(br_cc setne, (and SWTestOp, 2), 0) -> (BCC PRED_EQ, SWTestOp)
(br_cc setne, (and SWTestOp, 4), 0) -> (BCC PRED_GT, SWTestOp)
(br_cc setne, (and SWTestOp, 8), 0) -> (BCC PRED_LT, SWTestOp)

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D94054
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/PowerPC/fold_swtest_br.ll
Commit eec856848ccc481b2704ebf64d725e635a3d7dca by alexandre.ganea
Revert "[Support] On Windows, take the affinity mask into account"

This reverts commit 336ab2d51dfdd5ca09c2a9c506453db4fe653584.
The file was modifiedllvm/include/llvm/Support/Program.h
The file was modifiedllvm/lib/Support/Program.cpp
The file was modifiedllvm/lib/Support/Unix/Program.inc
The file was modifiedllvm/lib/Support/Windows/Program.inc
The file was modifiedllvm/lib/Support/Windows/Threading.inc
The file was modifiedllvm/unittests/Support/ThreadPool.cpp
Commit 9abac60309006db00eca0af406c2e16bef26807c by Duncan P. N. Exon Smith
ADT: Fix reference invalidation in SmallVector::push_back and single-element insert

For small enough, trivially copyable `T`, take the argument by value in
`SmallVector::push_back` and copy it when forwarding to
`SmallVector::insert_one_impl`. Otherwise, when growing, update the
argument appropriately.

Differential Revision: https://reviews.llvm.org/D93779
The file was modifiedllvm/unittests/ADT/SmallVectorTest.cpp
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
Commit b196dc6607233d6235846b4a1bde70a6e0cc8512 by aeubanks
[NFC] Remove unused entry in PassRegistry.def
The file was modifiedllvm/lib/Passes/PassRegistry.def
Commit 56d1ffb927d03958a7a31442596df749264a7792 by Duncan P. N. Exon Smith
Revert "ADT: Fix reference invalidation in SmallVector::push_back and single-element insert"

This reverts commit 9abac60309006db00eca0af406c2e16bef26807c since there
are some bot errors on Windows:
http://lab.llvm.org:8011/#/builders/127/builds/4489

```
FAILED: lib/Support/CMakeFiles/LLVMSupport.dir/IntervalMap.cpp.obj
C:\PROGRA~2\MIB055~1\2017\PROFES~1\VC\Tools\MSVC\1416~1.270\bin\Hostx64\x64\cl.exe  /nologo /TP -DGTEST_HAS_RTTI=0 -DUNICODE -D_CRT_NONSTDC_NO_DEPRECATE -D_CRT_NONSTDC_NO_WARNINGS -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS -D_HAS_EXCEPTIONS=0 -D_SCL_SECURE_NO_DEPRECATE -D_SCL_SECURE_NO_WARNINGS -D_UNICODE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib\Support -IC:\b\slave\sanitizer-windows\llvm-project\llvm\lib\Support -Iinclude -IC:\b\slave\sanitizer-windows\llvm-project\llvm\include /DWIN32 /D_WINDOWS   /Zc:inline /Zc:__cplusplus /Zi /Zc:strictStrings /Oi /Zc:rvalueCast /bigobj /W4 -wd4141 -wd4146 -wd4244 -wd4267 -wd4291 -wd4351 -wd4456 -wd4457 -wd4458 -wd4459 -wd4503 -wd4624 -wd4722 -wd4100 -wd4127 -wd4512 -wd4505 -wd4610 -wd4510 -wd4702 -wd4245 -wd4706 -wd4310 -wd4701 -wd4703 -wd4389 -wd4611 -wd4805 -wd4204 -wd4577 -wd4091 -wd4592 -wd4319 -wd4709 -wd4324 -w14062 -we4238 /Gw /MD /O2 /Ob2 -UNDEBUG -std:c++14  /EHs-c- /GR- /showIncludes /Folib\Support\CMakeFiles\LLVMSupport.dir\IntervalMap.cpp.obj /Fdlib\Support\CMakeFiles\LLVMSupport.dir\LLVMSupport.pdb /FS -c C:\b\slave\sanitizer-windows\llvm-project\llvm\lib\Support\IntervalMap.cpp
C:\b\slave\sanitizer-windows\llvm-project\llvm\include\llvm/ADT/SmallVector.h(746): error C2672: 'llvm::SmallVectorImpl<T>::insert_one_maybe_copy': no matching overloaded function found
        with
        [
            T=llvm::IntervalMapImpl::Path::Entry
        ]
C:\b\slave\sanitizer-windows\llvm-project\llvm\include\llvm/ADT/SmallVector.h(745): note: while compiling class template member function 'llvm::IntervalMapImpl::Path::Entry *llvm::SmallVectorImpl<T>::insert(llvm::IntervalMapImpl::Path::Entry *,T &&)'
        with
        [
            T=llvm::IntervalMapImpl::Path::Entry
        ]
C:\b\slave\sanitizer-windows\llvm-project\llvm\lib\Support\IntervalMap.cpp(22): note: see reference to function template instantiation 'llvm::IntervalMapImpl::Path::Entry *llvm::SmallVectorImpl<T>::insert(llvm::IntervalMapImpl::Path::Entry *,T &&)' being compiled
        with
        [
            T=llvm::IntervalMapImpl::Path::Entry
        ]
C:\b\slave\sanitizer-windows\llvm-project\llvm\include\llvm/ADT/SmallVector.h(1136): note: see reference to class template instantiation 'llvm::SmallVectorImpl<T>' being compiled
        with
        [
            T=llvm::IntervalMapImpl::Path::Entry
        ]
C:\b\slave\sanitizer-windows\llvm-project\llvm\include\llvm/ADT/IntervalMap.h(790): note: see reference to class template instantiation 'llvm::SmallVector<llvm::IntervalMapImpl::Path::Entry,4>' being compiled
C:\b\slave\sanitizer-windows\llvm-project\llvm\include\llvm/ADT/SmallVector.h(746): error C2783: 'llvm::IntervalMapImpl::Path::Entry *llvm::SmallVectorImpl<T>::insert_one_maybe_copy(llvm::IntervalMapImpl::Path::Entry *,ArgType &&)': could not deduce template argument for '__formal'
        with
        [
            T=llvm::IntervalMapImpl::Path::Entry
        ]
C:\b\slave\sanitizer-windows\llvm-project\llvm\include\llvm/ADT/SmallVector.h(727): note: see declaration of 'llvm::SmallVectorImpl<T>::insert_one_maybe_copy'
        with
        [
            T=llvm::IntervalMapImpl::Path::Entry
        ]
```
The file was modifiedllvm/unittests/ADT/SmallVectorTest.cpp
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
Commit 5c1c39e8d808d7d08a2c3c5ed192d543a55f685c by kazu
[llvm] Use *Set::contains (NFC)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/include/llvm/ADT/DepthFirstIterator.h
The file was modifiedllvm/lib/Analysis/IRSimilarityIdentifier.cpp
The file was modifiedllvm/include/llvm/Analysis/DivergenceAnalysis.h
The file was modifiedllvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
The file was modifiedllvm/lib/ExecutionEngine/MCJIT/MCJIT.h
The file was modifiedllvm/lib/Transforms/IPO/IROutliner.cpp
Commit 125ea20d55c554fbe14eb1f6cff7d44a720a51f5 by kazu
[llvm] Use llvm::stable_sort (NFC)
The file was modifiedllvm/utils/TableGen/RegisterInfoEmitter.cpp
The file was modifiedllvm/lib/CodeGen/SafeStackLayout.cpp
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp
The file was modifiedllvm/utils/TableGen/SearchableTableEmitter.cpp
The file was modifiedllvm/lib/Transforms/IPO/IROutliner.cpp
The file was modifiedllvm/utils/TableGen/DAGISelEmitter.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit 4c1617dac8fa13a8eac9cc4ac13a8f1fb3da512e by kazu
[llvm] Use std::any_of (NFC)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
Commit 49142991a685bd427d7e877c29c77371dfb7634c by Duncan P. N. Exon Smith
Reapply "ADT: Fix reference invalidation in SmallVector::push_back and single-element insert"

This reverts commit 56d1ffb927d03958a7a31442596df749264a7792, reapplying
9abac60309006db00eca0af406c2e16bef26807c, removing insert_one_maybe_copy
and using a helper called forward_value_param instead. This avoids use
of `std::is_same` (or any SFINAE), so I'm hoping it's more portable and
MSVC will be happier.

Original commit message follows:

For small enough, trivially copyable `T`, take the argument by value in
`SmallVector::push_back` and copy it when forwarding to
`SmallVector::insert_one_impl`. Otherwise, when growing, update the
argument appropriately.

Differential Revision: https://reviews.llvm.org/D93779
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
The file was modifiedllvm/unittests/ADT/SmallVectorTest.cpp
Commit 3043e5a5c33c4c871f4a1dfd621a8839f9a1f0b3 by Duncan P. N. Exon Smith
ADT: Fix reference invalidation in N-element SmallVector::append and insert

For small enough, trivially copyable `T`, take the parameter by-value in
`SmallVector::append` and `SmallVector::insert`.  Otherwise, when
growing, update the arugment appropriately.

Differential Revision: https://reviews.llvm.org/D93780
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
The file was modifiedllvm/unittests/ADT/SmallVectorTest.cpp
Commit 752fafda3dbf1f4885c64408a13ddb67c91ccb13 by rupprecht
[NFC] Fix -Wsometimes-uninitialized

After 49142991a685bd427d7e877c29c77371dfb7634c, clang detects that MUL may be uninitialized. Set it to nullptr to suppress this check.

Adding an assert to check that it is ultimately set fails two test cases. Since this is not a new issue, leave the assertion commented out until a code owner can fix the bug. The two failing test cases are noted in the assertion comment.
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Commit 260a856c2abcef49c7cb3bdcd999701db3e2af38 by Duncan P. N. Exon Smith
ADT: Fix reference invalidation in SmallVector::resize

For small enough, trivially copyable `T`, take the parameter by-value in
`SmallVector::resize`.  Otherwise, when growing, update the arugment
appropriately.

Differential Revision: https://reviews.llvm.org/D93781
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
The file was modifiedllvm/unittests/ADT/SmallVectorTest.cpp
Commit c224a834583ccbb3f8e8047d409ef3bf356abc01 by Duncan P. N. Exon Smith
ADT: Reduce code duplication in SmallVector::resize by using pop_back_n, NFC
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
Commit 3f98b66f23f9844a61f63ee00a81b9914f9a039d by Duncan P. N. Exon Smith
ADT: Reduce code duplication in SmallVector by reusing reserve, NFC
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
Commit 53b34601abf1d48e8df210ab8127b16fd35e275a by i
[Driver] -gsplit-dwarf: Produce .dwo regardless of -gN for -fthinlto-index=

-g is an IR generation option while -gsplit-dwarf is an object file generation option.
For -gsplit-dwarf in the backend phase of a distributed ThinLTO (-fthinlto-index=) which does object file generation and no IR generation, -g should not be needed.

This patch makes `-fthinlto-index= -gsplit-dwarf` emit .dwo even in the absence of -g.
This should fix https://crbug.com/1158215 after D80391.

```
// Distributed ThinLTO usage
clang -g -O2 -c -flto=thin -fthin-link-bitcode=a.indexing.o a.c
clang -g -O2 -c -flto=thin -fthin-link-bitcode=b.indexing.o b.c
clang -fuse-ld=lld -Wl,--thinlto-index-only=a.rsp -Wl,--thinlto-prefix-replace=';lto/' -Wl,--thinlto-object-suffix-replace='.indexing.o;.o' a.indexing.o b.indexing.o
clang -gsplit-dwarf -O2 -c -fthinlto-index=lto/a.o.thinlto.bc a.o -o lto/a.o
clang -gsplit-dwarf -O2 -c -fthinlto-index=lto/b.o.thinlto.bc b.o -o lto/b.o
clang -fuse-ld=lld @a.rsp -o exe
```

Note: for implicit regular/Thin LTO, .dwo emission works without this patch:
`clang -flto=thin -gsplit-dwarf a.o b.o` passes `-plugin-opt=dwo_dir=` to the linker.
The linker forwards the option to LTO. LTOBackend.cpp emits `$dwo_dir/[01234].dwo`.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D94647
The file was modifiedclang/test/Driver/split-debug.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit 6ed3083a96541a7483cb02bb3b2f52b1d0a37c84 by Duncan P. N. Exon Smith
ADT: Reduce code duplication in SmallVector by calling reserve and clear, NFC
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
Commit ff5e896425577f445ed080d88b582aab0896fba0 by lxfind
Fix unused variable in CoroFrame.cpp when building Release with GCC 10

When building with GCC 10, the following warning is reported:

```
/llvm-project/llvm/lib/Transforms/Coroutines/CoroFrame.cpp:1527:28: warning: unused variable ‘CS’ [-Wunused-variable]
1527 |       if (CatchSwitchInst *CS =
```

This change adds a cast to `void` to avoid the warning.

Reviewed By: lxfind

Differential Revision: https://reviews.llvm.org/D94456
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
Commit 885eae9d85de4b1b1907ac9b3ecba26565932069 by Jason Molenda
Add func call so we don't instruction-step into the builtin_trap

The way this test is structured right now, I set a breakpoint on
the instruction before the __builtin_trap.  It hits the breakpoint,
disables the breakpoint, and instruction steps.  This hits the
builtin_trap instruction which debugserver (on arm64) now advances
to the next instruction and reports that address to lldb.  lldb
doesn't recognize this as a proper response to the instruction
step and continues executing until the next trap, and the test fails.
The file was modifiedlldb/test/API/macosx/builtin-debugtrap/main.cpp
Commit 7ad54d193871ce69968565ea46372e81c9f1ce62 by pavel
[lldb][wasm] Parse DWO section names

Mirror ELF section parsing to support DWARF section names for
debug fission.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D93621
The file was modifiedlldb/test/Shell/ObjectFile/wasm/embedded-debug-sections.yaml
The file was modifiedlldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.cpp
Commit 2bbf724feea9824f9b9e4d20d34828023dbec2af by pavel
Implement vAttachWait in lldb-server

This commit vAttachWait in lldb-server, so --waitfor can be used on
Linux

Reviewed By: labath, clayborg

Differential Revision: https://reviews.llvm.org/D93895
The file was addedlldb/test/API/tools/lldb-server/TestGdbRemoteAttachWait.py
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
Commit ed205f63b4a288ccbffc9af58333d09a7cec40dc by zinenko
[mlir] Update doc to omit the usage of LLVMIntegerType

Since [[ https://reviews.llvm.org/D94178 | the LLVMIntegerType was replaced with build-in integer type ]], the usage in the tutorial should be also updated accordingly.
We need to update chapter 6 for Toy tutorial specifically.

See: https://reviews.llvm.org/D94178

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D94651
The file was modifiedmlir/docs/Tutorials/Toy/Ch-6.md
Commit 4b284b9ca8098e284b8d965a633b71bd283043d6 by pavel
[lldb] Fix TestPlatformProcessConnect.py

The test was marked as remote-only, which means it was run ~never, and
accumulated various problems. This commit modifies the test to run
locally and includes a couple of other fixes necessary to make it run:
- moves the "invoke" method into the "Base" test class
- adds []'s around the IP address in a couple more places to make things
  work with IPv6

The test is now marked as skipped when running the remote test suite. It
would be possible to make it run both locally and remotely, but this
would require writing a lot special logic for the remote case, and that
is not worth it.
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbtest.py
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerPlatform.cpp
The file was modifiedlldb/test/API/tools/lldb-server/platform-process-connect/TestPlatformProcessConnect.py
The file was modifiedlldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
Commit 259936f4910ad7da7589f81862fc855386ae8621 by david.stuttard
[NFC][AsmPrinter] Windows warning: Use explicit cast

static_cast for uint64_t to unsigned gives a MS VC build warning
for Windows:

warning C4309: 'static_cast': truncation of constant value

Use an explicit cast instead.

Change-Id: I692d335b4913070686a102780c1fb05b893a2f69

Differential Revision: https://reviews.llvm.org/D94592
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Commit 2b1e25befefc20f012aa49011f46e11e8530ee21 by lucas.prates
[AArch64] Adding ACLE intrinsics for the LS64 extension

This introduces the ARMv8.7-A LS64 extension's intrinsics for 64 bytes
atomic loads and stores: `__arm_ld64b`, `__arm_st64b`, `__arm_st64bv`,
and `__arm_st64bv0`. These are selected into the LS64 instructions
LD64B, ST64B, ST64BV and ST64BV0, respectively.

Based on patches written by Simon Tatham.

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D93232
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedclang/include/clang/Basic/BuiltinsAArch64.def
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedclang/lib/Headers/arm_acle.h
The file was modifiedclang/lib/Basic/Targets/AArch64.cpp
The file was modifiedclang/test/Preprocessor/aarch64-target-features.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was addedllvm/test/CodeGen/AArch64/ls64-intrinsics.ll
The file was addedclang/test/CodeGen/aarch64-ls64.c
Commit 4bb11b3eafbde75ab026ec180cae62799ba0fb3c by flo
[LTO] Expose opt() in LTOBackend (NFC).

Exposing opt() which runs middle-end LTO optimzation allows re-using it
in LTOCodeGenerator.

Reviewed By: steven_wu

Differential Revision: https://reviews.llvm.org/D94486
The file was modifiedllvm/lib/LTO/LTOBackend.cpp
The file was modifiedllvm/include/llvm/LTO/LTOBackend.h
Commit 53e3b81faaf32a495189182e0e4d635cbe19c5dd by wingo
[lld][WebAssembly] Add support for handling table symbols

This commit adds table symbol support in a partial way, while still
including some special cases for the __indirect_function_table symbol.
No change in tests.

Differential Revision: https://reviews.llvm.org/D94075
The file was modifiedlld/wasm/SymbolTable.h
The file was modifiedlld/wasm/InputChunks.cpp
The file was modifiedlld/wasm/SyntheticSections.h
The file was modifiedlld/wasm/WriterUtils.cpp
The file was modifiedlld/wasm/SymbolTable.cpp
The file was modifiedlld/wasm/SyntheticSections.cpp
The file was modifiedlld/wasm/WriterUtils.h
The file was modifiedllvm/include/llvm/BinaryFormat/Wasm.h
The file was modifiedlld/wasm/MarkLive.cpp
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/wasm/Writer.cpp
The file was addedlld/wasm/InputTable.h
The file was modifiedlld/wasm/InputFiles.h
The file was modifiedllvm/lib/Object/WasmObjectFile.cpp
The file was modifiedlld/include/lld/Common/LLVM.h
The file was modifiedlld/wasm/Symbols.cpp
The file was modifiedllvm/include/llvm/Object/Wasm.h
The file was modifiedlld/wasm/Symbols.h
The file was modifiedllvm/tools/llvm-readobj/WasmDumper.cpp
Commit d58512b2e31a255dccc2c9a351a4e47b2b4c9f79 by bjorn.a.pettersson
[SLP] Don't vectorize stores of non-packed types (like i1, i2)

In the spirit of commit fc783e91e0c0696e (llvm-svn: 248943) we
shouldn't vectorize stores of non-packed types (i.e. types that
has padding between consecutive variables in a scalar layout,
but being packed in a vector layout).

The problem was detected as a miscompile in a downstream test case.

Reviewed By: anton-afanasyev

Differential Revision: https://reviews.llvm.org/D94446
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/bad_types.ll
Commit 17f8c458de631c0311828931a5bdf72b1a13c29d by mikhail.maltsev
[clang] Use SourceLocations in unions [NFCI]

Currently, there are many instances where `SourceLocation` objects are
converted to raw representation to be stored in structs that are
used as fields of tagged unions.

This is done to make the corresponding structs trivial.
Triviality allows avoiding undefined behavior when implicitly changing
the active member of the union.

However, in most cases, we can explicitly construct an active member
using placement new. This patch adds the required active member
selections and replaces `SourceLocation`-s represented as
`unsigned int` with proper `SourceLocation`-s.

One notable exception is `DeclarationNameLoc`: the objects of this class
are often not properly initialized (so the code currently relies on
its default constructor which uses memset). This class will be fixed
in a separate patch.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D94237
The file was modifiedclang/lib/AST/Expr.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/include/clang/Sema/Initialization.h
The file was modifiedclang/lib/Sema/DeclSpec.cpp
The file was modifiedclang/include/clang/Sema/DeclSpec.h
The file was modifiedclang/include/clang/AST/DependentDiagnostic.h
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/include/clang/AST/Expr.h
The file was modifiedclang/include/clang/AST/TemplateBase.h
The file was modifiedclang/include/clang/Sema/Designator.h
The file was modifiedclang/lib/Parse/ParseDeclCXX.cpp
The file was modifiedclang/include/clang/Basic/SourceManager.h
The file was modifiedclang/lib/AST/TemplateBase.cpp
Commit af8d27a7a8266b89916b5e4db2b2fd97eb7d84e5 by llvm-dev
[DAG] visitVECTOR_SHUFFLE - pull out shuffle merging code into lambda helper. NFCI.

Make it easier to reuse in a future patch.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 8f1d7f3753ca132b310bbb0e62c394cfa75daee5 by llvm-dev
[X86] Improve sum-of-reductions v4f32 test coverage

Ensure that the v4f32 reductions use a -0.0f start value and add fast-math test variant.
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
Commit a997a1d7fbe229433fb458bb0035b32424ecf3bd by pavel
[lldb/test] Ensure launched processes are ready to be attached

Linux systems can be configured (and most of them are configured that
way) to disable attaching to unrelated processes, /unless/ those
processes explicitly allow that.

Our test inferiors do that by explicitly calling prctl(PR_SET_PTRACER,
PR_SET_PTRACER_ANY) (a.k.a., lldb_enable_attach). This requires
additional synchronization to ensure that the test does not attempt
attach before that statement is executed.

This is working fine (albeit cumbersome) for most tests but
TestGdbRemoteAttachWait is special in that it wants to start the
inferior _after_ issuing the attach request. This means that the usual
synchronization method does not work.

This patch introduces a different solution -- enable attaching in the
test harness, before the process is launched. Besides fixing this
problem, this is also better because it avoids the need to add special
code to each attach test (which is a common error).

One gotcha here is that it won't work for remote test suites, as we
don't control launching there. However, we could add a similar option to
lldb-platform, or require that lldb-platform itself is started with
attaching enabled. At that point we could delete all lldb_enable_attach
logic.
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbplatformutil.py
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbtest.py
Commit 7c30c05ff71d062f0b8a05b7c3c12ede2c285371 by llvm-dev
[DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - reset shuffle ops and reorder early-out and second op matching. NFCI.

I'm hoping to reuse MergeInnerShuffle in some other folds - so ensure the candidate ops/mask are reset at the start of each run.

Also, move the second op matching before bailing to make it simpler to try to match other things afterward.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 2e25be0b6134e9544f7cee7bb7b31a921ca37cc0 by platonov.aleksandr
[clangd] Add main file macros into the main-file index.

This patch is a try to fix `WorkspaceSymbols.Macros` test after D93796.
If a macro definition is in the preamble section, then it appears to be in the preamble (static) index and not in the main-file (dynamic) index.
Thus, a such macro could not be found at a symbol search according to the logic that we skip symbols from the static index if the location of these symbols is inside the dynamic index files.
To fix this behavior this patch adds main file macros into the main-file (dynamic) index.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D94477
The file was modifiedclang-tools-extra/clangd/unittests/CollectMacrosTests.cpp
The file was modifiedclang-tools-extra/clangd/SemanticHighlighting.cpp
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
The file was modifiedclang-tools-extra/clangd/unittests/ParsedASTTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
The file was modifiedclang-tools-extra/clangd/CollectMacros.cpp
The file was modifiedclang-tools-extra/clangd/index/SymbolCollector.cpp
The file was modifiedclang-tools-extra/clangd/CollectMacros.h
Commit 19297a4171177b942832d49a3767609d2a112ae1 by nigelp
Change XCore code owner.

Discussion: https://lists.llvm.org/pipermail/llvm-dev/2021-January/147603.html
The file was modifiedllvm/CODE_OWNERS.TXT
Commit 3bccd87a588b3c320b669686c8f006b92ff72182 by Jan Svoboda
[clang][cli] NFC: Remove SSPBufferSize assignment

This should've been part of D84669, but got overlooked. Removing the assignment is NFC, as it's also done by the marshalling infrastructure for the stack_protector_buffer_size option.

Reviewed By: dexonsmith in D94488
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
Commit fa2fe9608c1c1b402296960b1edc157230c30062 by Jan Svoboda
[clang][cli] Port more CodeGenOptions to marshalling infrastructure

Leveraging the recently added TableGen constructs (ShouldParseIf and MarshallingInfoStringInt) to shift from manual command line parsing to automatic TableGen-driver marshalling.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D94488
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
Commit 6abbba3fca9fdf8d31f74800a7ddb40b103ae6e3 by alexandre.ganea
Revert "Fix llvm::Optional build breaks in MSVC using std::is_trivially_copyable"

This reverts commit 854f0984f0b7ab9a9a541a4bcda7ea173e4113d3.

This breaks compilation with clang-cl on Windows, while in a MSVC 16.8 cmd.exe.
This also breaks PPC: http://lab.llvm.org:8011/#/builders/93/builds/1435
And: https://reviews.llvm.org/D93510#2497737
The file was modifiedllvm/unittests/ADT/OptionalTest.cpp
The file was modifiedllvm/include/llvm/ADT/Optional.h
Commit 176f5e95e1afad75ff045a00f0fa9c781bd5f54a by mikhail.maltsev
[clang-tidy] Use DenseSet<SourceLocation> in UpgradeDurationConversionsCheck, NFCI

This change replaces `unordered_set<unsigned>` (which used to store
internal representation of `SourceLocation`-s) with
`DenseSet<SourceLocation>` (which stores `SourceLocation`-s directly).

Reviewed By: aaron.ballman, njames93

Differential Revision: https://reviews.llvm.org/D94601
The file was modifiedclang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.h
The file was modifiedclang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.cpp
Commit a1bbd1ef1dbd2a39777ef0b2d623f15f0523cdbf by andrzej.warzynski
[flang][driver] Unify f18_version.h.in and Version.inc.in

Flang has two CMake configurable header files that define compiler
version numbers:
* f18_version.h.in - only used in f18.cpp (uses version numbers from
  LLVM's macro definitions)
* Version.inc.in - not currently used (uses version numbers hard-coded
  in Flang's top CMake script)

Currently only f18_version.h.in provides version numbers consistent with
other subprojects in llvm-project. However, its location and name are
inconsistent with e.g. Clang. This patch merges the two headers
together:
  * hard-coded version numbers in Flang's top CMake script are deleted
  * Version.inc.in is updated to provide string versions of version
  numbers (required by f18.cpp)
  * f18_version.h.in is deleted as it's no longer needed

Differential Revision: https://reviews.llvm.org/D94422
The file was removedflang/tools/f18/f18_version.h.in
The file was modifiedflang/CMakeLists.txt
The file was modifiedflang/include/flang/Version.inc.in
The file was modifiedflang/tools/f18/CMakeLists.txt
The file was modifiedflang/tools/f18/f18.cpp
Commit c23e34e606bf23ee8d4060469ecebe0f7971c5dd by flo
[InferFunctionAttrs] Improve CHECK variable names (NFC).
The file was modifiedllvm/test/Transforms/InferFunctionAttrs/annotate.ll
Commit a1cba5b7a1fb09d2d4082967e2466a5a89ed698a by jay.foad
[SelectionDAG] Make use of KnownBits::commonBits. NFC.

Differential Revision: https://reviews.llvm.org/D94587
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
Commit 517196e569129677be32d6ebcfa57bac552268a4 by jay.foad
[Analysis,CodeGen] Make use of KnownBits::makeConstant. NFC.

Differential Revision: https://reviews.llvm.org/D94588
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 90b310f6caf0b356075c70407c338b3c751eebb3 by jay.foad
[Support] Simplify KnownBits::icmp helpers. NFC.

Remove some special cases that aren't really any simpler than the
general case.

Differential Revision: https://reviews.llvm.org/D94595
The file was modifiedllvm/lib/Support/KnownBits.cpp
Commit e8622d27c0e3020177ff47ad57dd1e5371feb9cf by llvm-dev
[Support] Add KnownBits::sextInReg exhaustive tests

Requested by @foad in rG9cf4f493a72f
The file was modifiedllvm/unittests/Support/KnownBitsTest.cpp
Commit 332e220ef42b92df4e080cfa5b91c9accbe9731b by Stefan Gränitz
[docs] Update DebuggingJITedCode page after fix in LLDB

Generalize the documentation to include both, GDB and LLDB. Add a link to the interface
definition. Make a note on MCJIT's restriction to ELF. Mention the regression and bugfix
in LLDB as well as the jit-loader setting for macOS. Update the command line session to
use LLDB instead of GDB.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D90789
The file was modifiedllvm/docs/DebuggingJITedCode.rst
Commit 0b46f19a9ecd6215cffb51d19f2403c18b0226f5 by llvm-dev
[Support] Ensure KnownBits::sextInReg can handle the src == dst sext-in-reg case.

This was resulting in assertions inside APInt::zext that we were extending to the same bitwidth.
The file was modifiedllvm/unittests/Support/KnownBitsTest.cpp
The file was modifiedllvm/lib/Support/KnownBits.cpp
Commit 3e41ab18db2255028c288a11665c08d260654299 by tkeith
[flang] Fix dangling pointer in LabelEnforce

`DirectiveStructureChecker` was passing in a pointer to a temporary
string for the `construct` argument to the constructor for `LabelEnforce`.
The `LabelEnforce` object had a lifetime longer than the temporary,
resulting in accessing a dangling pointer when emitting an error message
for `omp-parallell01.f90`.

The fix is to make the lifetime of the temporary as long as the lifetime
of the `LabelEnforce` object.

Differential Revision: https://reviews.llvm.org/D94618
The file was modifiedflang/lib/Semantics/check-directive-structure.h
Commit adb77a7456920a46908c7e20b2d3008789274975 by anastasia.stulova
[OpenCL] Improve online documentation.

Update UsersManual and OpenCLSupport pages to reflect
recent functionality i.e. SPIR-V generation,
C++ for OpenCL, OpenCL 3.0 development plans.

Tags: #clang

Differential Revision: https://reviews.llvm.org/D93942
The file was modifiedclang/docs/OpenCLSupport.rst
The file was modifiedclang/docs/UsersManual.rst
Commit 6b9fa8a50d0f9e1e54f238b1c50fee8ff7011218 by antiagainst
[mlir][linalg] Add docstring support for named op spec

Depends on D94335

Reviewed By: nicolasvasilache, hanchung

Differential Revision: https://reviews.llvm.org/D94548
The file was modifiedmlir/docs/Dialects/Linalg.md
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
Commit c0939fddf80c16829502186e2e5b78f77696310a by llvm-dev
[Support] Simplify KnownBits::sextInReg implementation.

As noted by @foad in rG9cf4f493a72f all we need to do is sextInReg both KnownBits One and Zero.
The file was modifiedllvm/lib/Support/KnownBits.cpp
Commit a022be625387370cf67b26c6b99b05f16b2a8610 by Paul C. Anagnostopoulos
[TableGen] Enhance !cast<string> to handle bit and bits types.

Add a test for this.

Differential Revision: https://reviews.llvm.org/D94529
The file was modifiedllvm/lib/TableGen/Record.cpp
The file was addedllvm/test/TableGen/cast-string.td
Commit dbaa6a1858a42f72b683f700d3bd7a9632f7a518 by martin
Revert "[AArch64] Attempt to sink mul operands"

This reverts commit dda60035e9f0769c8907cdf6561489e0435c2275.

This commit caused failures to compile some sources, erroring out
with "error in backend: Cannot select: t85: v2i32 = AArch64ISD::DUP t15",
see https://reviews.llvm.org/D91271 for the full reproduction case.
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was removedllvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
Commit d0dbb0468c26bafa88e7340781fb3a0a79379470 by llvm-dev
[Support] Remove redundant sign bit tests from KnownBits::getSignedMinValue/getSignedMaxValue

As noted by @foad on rG6895581fd2c1
The file was modifiedllvm/include/llvm/Support/KnownBits.h
Commit 0a59647ee407524e6468cc5be4ba288861aa700d by llvm-dev
[SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds

Fixes clang-with-thin-lto-ubuntu buildbot after D94383/rGddd03842c347
The file was modifiedllvm/test/CodeGen/SystemZ/misched-cutoff.ll
Commit 17fb21f875f4aaf6ad2cf9499cb75d76588167f2 by sam.mccall
[clangd] Remove another option that was effectively always true. NFC
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/CodeComplete.h
The file was modifiedclang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp
Commit 7c9c2a2ea5e3760d7310309c96c9a4ce41fa4d9b by selliott
Revert "[RISCV] Legalize select when Zbt extension available"

We found issues with this patch in additional testing. Backing out while
we work on a fix.

This reverts commit 71ed4b6ce57d8843ef705af8f98305976a8f107a.
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbb.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbs.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbt.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
The file was modifiedllvm/test/CodeGen/RISCV/rv64Zbt.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbbp.ll
Commit 0afdbb4d2dead42df14361ca9f5613d56667481c by andrzej.warzynski
[flang][driver] Use __FLANG_VERISION__ in f18.cpp (nfc)

Just a minor improvement suggested in a post-commit review here:
https://reviews.llvm.org/D94422
The file was modifiedflang/tools/f18/f18.cpp
Commit e21bf875c0f709a721d98450203781a605483a1d by mtrofin
[NFC] Disallow unused prefixes under MC/ARM

Differential Revision: https://reviews.llvm.org/D94620
The file was modifiedllvm/test/MC/ARM/ldr-pseudo-cond-darwin.s
The file was modifiedllvm/test/MC/ARM/lsl-zero-errors.s
The file was modifiedllvm/test/MC/ARM/ldr-pseudo-cond.s
The file was modifiedllvm/test/MC/ARM/lsl-zero.s
The file was modifiedllvm/test/MC/ARM/lit.local.cfg
The file was modifiedllvm/test/MC/ARM/thumbv8m.s
The file was modifiedllvm/test/MC/ARM/mve-fp-registers.s
Commit 2f395b7092bdac0e39bb4e2bb5e6b03e521a45dd by usx
[clangd] Make AST-based signals available to runWithPreamble.

Many useful signals can be derived from a valid AST which is regularly updated by
the ASTWorker. `runWithPreamble` does not have access to the ParsedAST
but it can be provided access to some signals derived from a (possibly
stale) AST.

Differential Revision: https://reviews.llvm.org/D94424
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was addedclang-tools-extra/clangd/ASTSignals.cpp
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was addedclang-tools-extra/clangd/ASTSignals.h
The file was modifiedclang-tools-extra/clangd/TUScheduler.h
The file was modifiedclang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
The file was addedclang-tools-extra/clangd/unittests/ASTSignalsTests.cpp
The file was modifiedclang-tools-extra/clangd/TUScheduler.cpp
Commit 8b09cf7956d8abc722fa736874e4cea667a9d3cb by usx
[clangd] Trivial: Documentation fix in ASTSignals.
The file was modifiedclang-tools-extra/clangd/ASTSignals.h
The file was modifiedclang-tools-extra/clangd/ASTSignals.cpp
Commit b4e083b0ef7ca86851b5b1d043004ae632a63f8d by llvmgnsyncbot
[gn build] Port 2f395b7092bd
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit 4864d9f7e91fdd58a84e4ae576f1ad16f71f9d91 by pklausler
[flang] Fix some module file issues exposed by Whizard

Generic type-bound interfaces for user-defined operators need to be formatted
as "OPERATOR(.op.)", not just ".op."

PRIVATE generics need to be marked as such.

Declaration ordering: when a generic interface shadows a
derived type of the same name, it needs to be emitted to the
module file at the point of definition of the derived type;
otherwise, the derived type's definition may appear after its
first use.

The module symbol for a module read from a module file needs
to be marked as coming from a module file before semantic
processing is performed on the contents of the module so that
any special handling for declarations in module files can be
properly activated.

IMPORT statements were sometimes missing for use-associated
symbols in surrounding scopes; fine-tune NeedImport().

Differential Revision: https://reviews.llvm.org/D94636
The file was modifiedflang/lib/Semantics/mod-file.cpp
The file was addedflang/test/Semantics/modfile38.f90
The file was modifiedflang/test/Semantics/modfile35.f90
The file was addedflang/test/Semantics/modfile37.f90
Commit 35c8a6cbf5ff0b525e2c01e5d746067bdda1dde7 by mtrofin
[NFC] Disallow unused prefixes under MC/AArch64

Differential Revision: https://reviews.llvm.org/D94616
The file was modifiedllvm/test/MC/AArch64/armv8.7a-ls64.s
The file was modifiedllvm/test/MC/AArch64/lit.local.cfg
The file was modifiedllvm/test/MC/AArch64/armv8.7a-xs.s
Commit a03ffa98503bb6d5a990e61df060ed480c3e3f3b by aeubanks
[NewPM] Fix placement of LoopFlatten

https://reviews.llvm.org/D90402 was inconsistent with where it put
LoopFlatten between the two pass managers. It also missed adding it to
the non-O1 function simplification pipeline.

PR48738

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D94650
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit b99782cf7850a481fa36fd95ae04923739e0da6d by llvm-dev
[X86][AVX] Adjust unsigned saturation downconvert negative test

D87145 was showing that this test (added in D45315) could always be constant folded (with suitable value tracking).

What we actually needed was smax(smin()) negative test coverage, the invert of negative_test2_smax_usat_trunc_wb_256_mem, so I've tweaked the test to provide that instead.
The file was modifiedllvm/test/CodeGen/X86/avx512-trunc.ll
Commit 5d165f0b893d4fc5fb5caeb2b05c566dd26e4d89 by jonathanchesterfield
[libomptarget][amdgpu] Fix kernel launch tracing to match previous behavior

Restore control of kernel launch tracing to be >= 1 as it was before

export LIBOMPTARGET_KERNEL_TRACE=1

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D94695
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
Commit 868da2ea939baf8c71a6dcb878cf6094ede9486e by jay.foad
[SelectionDAG] Remove an early-out from computeKnownBits for smin/smax

Even if we know nothing about LHS, it can still be useful to know that
smax(LHS, RHS) >= RHS and smin(LHS, RHS) <= RHS.

Differential Revision: https://reviews.llvm.org/D87145
The file was modifiedllvm/test/CodeGen/X86/known-bits-vector.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 85dfcaadc5f0920dc8ecbece6c786701b8f45ab4 by jotrem
[LLDB] MinidumpParser: Prefer executable module even at higher address

When a program maps one of its own modules for reading, and then
crashes, breakpad can emit two entries for that module in the
ModuleList.  We have logic to identify this case by checking permissions
on mapped memory regions and report just the module with an executable
region.  As currently written, though, the check is asymmetric -- the
entry with the executable region must be the second one encountered for
the preference to kick in.

This change makes the logic symmetric, so that the first-encountered
module will similarly be preferred if it has an executable region but
the second-encountered module does not.  This happens for example when
the module in question is the executable itself, which breakpad likes to
report first -- we need to ignore the other entry for that module when
we see it later, even though it may be mapped at a lower virtual
address.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D94629
The file was modifiedlldb/source/Plugins/Process/minidump/MinidumpParser.cpp
The file was modifiedlldb/unittests/Process/minidump/MinidumpParserTest.cpp
Commit be40c12040a0d5551bf3430cbb184b5ef23e25fd by enye.shi
[HIP] Add signbit(long double) decl

An _MSC_VER version of signbit(long double) is required for MSVC headers.

Fixes: SWDEV-256409

Differential Revision: https://reviews.llvm.org/D93062
The file was modifiedclang/lib/Headers/__clang_cuda_math_forward_declares.h
Commit 6ebeba88f51959d763a8f274cdfecea46d51d28c by zinenko
Support emptiness checks for unbounded FlatAffineConstraints.

With this, we have complete support for emptiness checks. This also paves the way for future support to check if two FlatAffineConstraints are equal.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D94272
The file was modifiedmlir/include/mlir/Analysis/Presburger/Fraction.h
The file was modifiedmlir/include/mlir/Analysis/Presburger/Matrix.h
The file was addedmlir/lib/Analysis/LinearTransform.cpp
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
The file was addedmlir/unittests/Analysis/LinearTransformTest.cpp
The file was modifiedmlir/unittests/Analysis/CMakeLists.txt
The file was modifiedmlir/unittests/Analysis/AffineStructuresTest.cpp
The file was modifiedmlir/lib/Analysis/Presburger/CMakeLists.txt
The file was modifiedmlir/lib/Analysis/Presburger/Simplex.cpp
The file was addedmlir/include/mlir/Analysis/LinearTransform.h
The file was modifiedmlir/lib/Analysis/CMakeLists.txt
The file was modifiedmlir/include/mlir/Analysis/AffineStructures.h
The file was modifiedmlir/include/mlir/Analysis/Presburger/Simplex.h
The file was modifiedmlir/lib/Analysis/Presburger/Matrix.cpp
Commit 763c1f9933463c40c39c04b68bbe4d296823b003 by tianshilei1992
[OpenMP] Drop the static library libomptarget-nvptx

For NVPTX target, OpenMP provides a static library `libomptarget-nvptx`
built by NVCC, and another bitcode `libomptarget-nvptx-sm_{$sm}.bc` generated by
Clang. When compiling an OpenMP program, the `.bc` file will be fed to `clang`
in the second run on the program that compiles the target part. Then the generated
PTX file will be fed to `ptxas` to generate the object file, and finally the driver
invokes `nvlink` to generate the binary, where the static library will be appened
to `nvlink`.

One question is, why do we need two libraries? The only difference is, the static
library contains `omp_data.cu` and the bitcode library doesn't. It's unclear why
they were implemented in this way, but per D94565, there is no issue if we also
include the file into the bitcode library. Therefore, we can safely drop the
static library.

This patch is about the change in OpenMP. The driver will be updated as well if
this patch is accepted.

Reviewed By: jdoerfert, JonChesterfield

Differential Revision: https://reviews.llvm.org/D94573
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/CMakeLists.txt
Commit 4fffbc150cca1638051b8ad2a20f4b8240df0869 by zequanwu
[clang][MSVC] Fix missing MSInheritanceAttr in template specialization.

Fix PR48687.

Differential Revision: https://reviews.llvm.org/D94646
The file was modifiedclang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
Commit 202d359753d1f130a228c3ad52dfaabf384250d1 by yamauchi
[X86] Add the FSRM feature (Fast Short Rep Mov) to Zen3.

Note -x86-use-fsrm-for-memcpy is still disabled by default and there's no
default behavior change.

Differential Revision: https://reviews.llvm.org/D94436
The file was modifiedllvm/lib/Target/X86/X86.td
The file was modifiedllvm/test/CodeGen/X86/memcpy-inline-fsrm.ll
Commit 64e9e9aeee0155fc12d7d40d56e7611a63d8e47d by tianshilei1992
[OpenMP] Dropped unnecessary define when compiling deviceRTLs for NVPTX

The comment said CUDA 9 header files use the `nv_weak` attribute which
`clang` is not yet prepared to handle. It's three years ago and now things have
changed. Based on my test, removing the definition doesn't have any problem on
my machine with CUDA 11.1 installed.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D94700
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/CMakeLists.txt
Commit a8520f6970fd4d44ceae1ec5969563a0dbe30f54 by 31459023+hctim
[GWP-ASan] Minor refactor of optional components.

In preparation for the inbuilt options parser, this is a minor refactor
of optional components including:
- Putting certain optional elements in the right header files,
according to their function and their dependencies.
- Cleaning up some old and mostly-dead code.
- Moving some functions into anonymous namespaces to prevent symbol
export.

Reviewed By: cryptoad, eugenis

Differential Revision: https://reviews.llvm.org/D94117
The file was modifiedcompiler-rt/lib/gwp_asan/optional/backtrace_linux_libc.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
The file was modifiedcompiler-rt/lib/gwp_asan/optional/backtrace_fuchsia.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/optional/backtrace.h
The file was modifiedcompiler-rt/lib/gwp_asan/optional/segv_handler.h
The file was modifiedcompiler-rt/lib/gwp_asan/tests/CMakeLists.txt
The file was modifiedcompiler-rt/lib/gwp_asan/optional/segv_handler_posix.cpp
The file was removedcompiler-rt/lib/gwp_asan/tests/optional/printf_sanitizer_common.cpp
The file was addedcompiler-rt/lib/gwp_asan/tests/platform_specific/printf_sanitizer_common.cpp
The file was modifiedcompiler-rt/lib/scudo/scudo_allocator.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/optional/backtrace_sanitizer_common.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/optional/segv_handler_fuchsia.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/tests/harness.h
The file was addedcompiler-rt/lib/gwp_asan/optional/printf.h
Commit ca98baa042538e1a8654dd86b24d1602df9a1aec by clementval
[openacc] Rename generated file from ACC.cpp.inc to ACC.inc to match D92955

This patch rename the tablegen generated file ACC.cpp.inc to ACC.inc in order
to match what was done in D92955. This file is included in header file as well as .cpp
file so it make more sense.

Reviewed By: sameeranjoshi

Differential Revision: https://reviews.llvm.org/D93485
The file was modifiedflang/lib/Parser/unparse.cpp
The file was modifiedflang/include/flang/Parser/dump-parse-tree.h
The file was modifiedflang/include/flang/Parser/parse-tree.h
The file was modifiedflang/lib/Semantics/check-acc-structure.h
The file was modifiedllvm/include/llvm/Frontend/OpenACC/CMakeLists.txt
The file was modifiedllvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenACC/BUILD.gn
Commit 9e53c94d8dd737fcedb543d6ac687ea9696db8a6 by erich.keane
[NFC] Update test to not check for 'opaque' in the file name.

The intent presumably is to avoid generating 'opaque' in the IR, but the
header contains the filename. Thus, having the workspace in a directory
with opaque in it causes this test to fail.

This just adds a 'CHECK' line on target-triple, which is the last line
of the IR-header.
The file was modifiedclang/test/CodeGen/incomplete-function-type.c
Commit 1d973b7ded124dd19f766db0c8e07d1c686dfb1b by rob.suderman
[MLIR][TOSA] First lowerings from Tosa to Linalg

Initial commit to add support for lowering from TOSA to Linalg. The focus is on
the essential infrastructure for these lowerings and integration with existing
passes.

Includes lowerings for a subset of operations including:
  abs, add, sub, pow, and, or, xor, left shift, right shift, tanh

Lit tests are used to validate correctness.

Differential Revision: https://reviews.llvm.org/D94247
The file was addedmlir/lib/Conversion/TosaToLinalg/CMakeLists.txt
The file was modifiedmlir/lib/Conversion/CMakeLists.txt
The file was modifiedmlir/include/mlir/Conversion/Passes.h
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was addedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was addedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was addedmlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h
The file was addedmlir/lib/Conversion/TosaToLinalg/TosaToLinalgPass.cpp
Commit d8113cda782b56477d71321027c50389f05f5d31 by joker.eph
Add newline to terminate debug message (NFC)
The file was modifiedmlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
Commit a3904cc77f181cff7355357688edfc392a236f5d by nikita.ppv
[BasicAA] Handle recursive queries more efficiently

An alias query currently works out roughly like this:

* Look up location pair in cache.
* Perform BasicAA logic (including cache lookup and insertion...)
* Perform a recursive query using BestAAResults.
   * Look up location pair in cache (and thus do not recurse into BasicAA)
   * Query all the other AA providers.
* Query all the other AA providers.

This is a lot of unnecessary work, all ultimately caused by the
BestAAResults query at the end of aliasCheck(). The reason we perform
it, is that aliasCheck() is getting called recursively, and we of
course want those recursive queries to also make use of other AA
providers, not just BasicAA. We can solve this by making the recursive
queries directly use BestAAResults (which will check both BasicAA
and other providers), rather than recursing into aliasCheck().

There are some tradeoffs:

* We can no longer pass through the precomputed underlying object
   to aliasCheck(). This is not a major concern, because nowadays
   getUnderlyingObject() is quite cheap.
* Results from other AA providers are no longer cached inside
   BasicAA. The way this worked was already a bit iffy, in that a
   result could be cached, but if it was MayAlias, we'd still end
   up re-querying other providers anyway. If we want to cache
   non-BasicAA results, we should do that in a more principled manner.

In any case, despite those tradeoffs, this works out to be a decent
compile-time improvment. I think it also simplifies the mental model
of how BasicAA works. It took me quite a while to fully understand
how these things interact.

Differential Revision: https://reviews.llvm.org/D90094
The file was modifiedllvm/include/llvm/Analysis/BasicAliasAnalysis.h
The file was modifiedllvm/lib/Analysis/BasicAliasAnalysis.cpp
The file was modifiedllvm/lib/Analysis/GlobalsModRef.cpp
Commit 00a61b327dd8a7071ce0baadd16ea4c7b7e31e73 by riddleriver
[mlir][ODS] Add new RangedTypesMatchWith operation predicate

This is a variant of TypesMatchWith that provides support for variadic arguments. This is necessary because ranges generally can't use the default operator== comparators for checking equality.

Differential Revision: https://reviews.llvm.org/D94574
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/test/mlir-tblgen/op-format.mlir
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
Commit 93592b726c7587aa86548cc74268346e25a4a7f2 by riddleriver
[mlir][OpFormatGen] Format enum attribute cases as keywords when possible

In the overwhelmingly common case, enum attribute case strings represent valid identifiers in MLIR syntax. This revision updates the format generator to format as a keyword in these cases, removing the need to wrap values in a string. The parser still retains the ability to parse the string form, but the printer will use the keyword form when applicable.

Differential Revision: https://reviews.llvm.org/D94575
The file was modifiedmlir/test/Dialect/SPIRV/IR/barrier-ops.mlir
The file was modifiedmlir/test/Transforms/cse.mlir
The file was modifiedmlir/test/Dialect/SPIRV/IR/target-env.mlir
The file was modifiedmlir/test/Transforms/sccp-callgraph.mlir
The file was modifiedmlir/test/Dialect/SCF/ops.mlir
The file was modifiedmlir/test/Transforms/sccp-structured.mlir
The file was modifiedmlir/test/Transforms/canonicalize.mlir
The file was modifiedmlir/test/Conversion/LinalgToSPIRV/linalg-to-spirv.mlir
The file was modifiedmlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
The file was modifiedmlir/test/Transforms/canonicalize-block-merge.mlir
The file was modifiedmlir/test/Conversion/ShapeToStandard/convert-shape-constraints.mlir
The file was modifiedmlir/test/Transforms/sccp.mlir
The file was modifiedmlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
The file was modifiedmlir/test/Dialect/Standard/canonicalize.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/matmul-vs-matvec.mlir
The file was modifiedmlir/test/Dialect/GPU/all-reduce-max.mlir
The file was modifiedmlir/test/Dialect/SCF/for-loop-specialization.mlir
The file was modifiedmlir/test/Conversion/ShapeToStandard/shape-to-standard.mlir
The file was modifiedmlir/test/Dialect/Linalg/convert-elementwise-to-linalg.mlir
The file was modifiedmlir/test/Dialect/SPIRV/IR/availability.mlir
The file was modifiedmlir/test/Dialect/Standard/expand-ops.mlir
The file was modifiedmlir/test/Dialect/Standard/expand-tanh.mlir
The file was modifiedmlir/test/Dialect/Linalg/tile-and-distribute.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_3d.mlir
The file was modifiedmlir/test/Target/SPIRV/non-uniform-ops.mlir
The file was modifiedmlir/test/Conversion/SCFToGPU/parallel_loop.mlir
The file was modifiedmlir/test/Transforms/buffer-loop-hoisting.mlir
The file was modifiedmlir/test/Conversion/VectorToSCF/vector-to-loops.mlir
The file was modifiedmlir/test/mlir-tblgen/op-format.mlir
The file was modifiedmlir/test/Transforms/constant-fold.mlir
The file was modifiedmlir/test/Dialect/Linalg/loops.mlir
The file was modifiedmlir/test/Dialect/Vector/vector-transforms.mlir
The file was modifiedmlir/test/Target/SPIRV/barrier-ops.mlir
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/test/Conversion/AffineToStandard/lower-affine.mlir
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
The file was modifiedmlir/test/Dialect/Vector/vector-contract-transforms.mlir
The file was modifiedmlir/test/Analysis/test-liveness.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_1d.mlir
The file was modifiedmlir/test/Conversion/StandardToLLVM/convert-to-llvmir.mlir
The file was modifiedmlir/test/Dialect/Vector/vector-transfer-full-partial-split.mlir
The file was modifiedmlir/test/Conversion/SCFToStandard/convert-to-cfg.mlir
The file was modifiedmlir/test/Dialect/Affine/parallelize.mlir
The file was modifiedmlir/test/IR/invalid-ops.mlir
The file was modifiedmlir/test/EDSC/builder-api-test.cpp
The file was modifiedmlir/test/Target/SPIRV/group-ops.mlir
The file was modifiedmlir/test/Transforms/buffer-deallocation.mlir
The file was modifiedmlir/test/Transforms/copy-removal.mlir
The file was modifiedmlir/test/Transforms/parametric-tiling.mlir
The file was modifiedmlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
The file was modifiedmlir/test/IR/invalid.mlir
The file was modifiedmlir/test/Dialect/SCF/parallel-loop-specialization.mlir
The file was modifiedmlir/test/Dialect/GPU/all-reduce.mlir
The file was modifiedmlir/test/IR/core-ops.mlir
The file was modifiedmlir/test/Analysis/test-dominance.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_2d.mlir
The file was modifiedmlir/test/Transforms/promote-buffers-to-stack.mlir
The file was modifiedmlir/test/Transforms/buffer-hoisting.mlir
The file was modifiedmlir/test/Dialect/Linalg/vectorization.mlir
The file was modifiedmlir/test/Dialect/SPIRV/IR/group-ops.mlir
Commit e3b9af92a4821fec25c207e2d1e443e09ff6b11e by i
[Driver] -gsplit-dwarf: Produce .dwo regardless of -gN for IR input

This generalizes D94647 to IR input, as suggested by @tejohnson.
Ideally the driver should just forward split dwarf options, but doing this currently will cause `clang -gsplit-dwarf -c a.c` to create a .dwo with just `.strtab`.

Reviewed By: dblaikie, tejohnson

Differential Revision: https://reviews.llvm.org/D94655
The file was modifiedclang/test/Driver/split-debug.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit 387d3c24792f7ab5f2f8aab37d64948f42523825 by craig.topper
[RISCV] Merge Utils library into MCTargetDesc

MCTargetDesc includes headers from Utils and Utils includes headers
from MCTargetDesc. So from a library layering perspective it makes sense
for them to be in the same library. I guess the other option might be to
move the tablegen includes from RISCVMCTargetDesc.h to RISCVBaseInfo.h
so that RISCVBaseInfo.h didn't need to include RISCVMCTargetDesc.h.
Everything else that depends on Utils also depends on MCTargetDesc so
having one library seemed simpler.

Differential Revision: https://reviews.llvm.org/D93168
The file was addedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was addedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
The file was removedllvm/lib/Target/RISCV/Utils/CMakeLists.txt
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
The file was removedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was addedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
The file was removedllvm/lib/Target/RISCV/Utils/RISCVMatInt.h
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt
The file was removedllvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/CMakeLists.txt
The file was addedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
The file was modifiedllvm/lib/Target/RISCV/RISCV.h
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
The file was removedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/CMakeLists.txt
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
Commit c8fb6ee34151b18bcc9ed1a6b8f502a0b40a414e by riddleriver
[mlir][PatternRewriter] Add a new hook to selectively replace uses of an operation

This revision adds a new `replaceOpWithIf` hook that replaces uses of an operation that satisfy a given functor. If all uses are replaced, the operation gets erased in a similar manner to `replaceOp`. DialectConversion support will be added in a followup as this requires adjusting how replacements are tracked there.

Differential Revision: https://reviews.llvm.org/D94632
The file was addedmlir/test/Transforms/test-pattern-selective-replacement.mlir
The file was modifiedmlir/include/mlir/Transforms/DialectConversion.h
The file was modifiedmlir/include/mlir/IR/PatternMatch.h
The file was modifiedmlir/lib/IR/PatternMatch.cpp
The file was modifiedmlir/lib/Transforms/Utils/DialectConversion.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestPatterns.cpp
Commit 5cf2696317afb0631a4a09414ae40a4e226a905e by tpopp
[mlir] Remove TosaToLinalg dependency on all Passes

TosaToLinalg was depending on its header file indirectly through
Passes.h rather than directly. This removes that indirection.

Differential Revision: https://reviews.llvm.org/D94706
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
Commit a71877edfbb7094584f6d20d93f6091e7d374024 by adamcz
[clang] Do not crash when CXXRecordDecl has a non-CXXRecordDecl base.

This can happen on some invalid code, like the included test case.

Differential Revision: https://reviews.llvm.org/D94704
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
The file was modifiedclang/test/SemaTemplate/temp_class_spec.cpp
Commit e2d7d3cb0eade079690c3938f694c8f7ef2b686b by silvasean
[mlir][docs] Bring bufferization docs up to date.

This spilts out BufferDeallocationInternals.md, since buffer
deallocation is not part of bufferization per se.

Differential Revision: https://reviews.llvm.org/D94351
The file was addedmlir/docs/BufferDeallocationInternals.md
The file was modifiedmlir/docs/Bufferization.md
Commit 0f588ac03e15a204b68f0214dda2b9f67410ff62 by Jinsong Ji
[PowerPC] Only use some extend mne if assembler is modern enough

Legacy AIX assembly might not support all extended mnes,
add one feature bit to control the generation in MC,
and avoid generating them by default on AIX.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D94458
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetMachine.cpp
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
The file was addedllvm/test/MC/PowerPC/modern-aix-as.s
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
Commit 0975604cc013b51ef2435199bd74a6d635b11150 by thakis
[gn build] (manually) port 387d3c24792f
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/RISCV/AsmParser/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCTargetDesc/BUILD.gn
The file was removedllvm/utils/gn/secondary/llvm/lib/Target/RISCV/Utils/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/RISCV/Disassembler/BUILD.gn
Commit e7228062b2bb87abf762abcb77668452a1ed35d4 by mcgrathr
[libc] Use #undef isascii in specific header

Standard C allows all standard headers to declare macros for all
their functions.  So after possibly including any standard header
like <ctype.h>, it's perfectly normal for any and all of the
functions it declares to be defined as macros.  Standard C requires
explicit `#undef` before using that identifier in a way that is not
compatible with function-like macro definitions.

The C standard's rules for this are extended to POSIX as well for
the interfaces it defines, and it's the expected norm for
nonstandard extensions declared by standard C library headers too.

So far the only place this has come up for llvm-libc's code is with
the isascii function in Fuchsia's libc.  But other cases can arise
for any standard (or common extension) function names that source
code in llvm-libc is using in nonstandard ways, i.e. as C++
identifiers.

The only correct and robust way to handle the possible inclusion of
standard C library headers when building llvm-libc source code is to
use `#undef` explicitly for each identifier before using it.  The
easy and obvious place to do that is in the per-function header.
This requires that all code, such as test code, that might include
any standard C library headers, e.g. via utils/UnitTest/Test.h, make
sure to include those *first* before the per-function header.

This change does that for isascii and its test.  But it should be
done uniformly for all the code and documented as a consistent
convention so new implementation files are sure to get this right.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D94642
The file was modifiedlibc/test/src/ctype/isascii_test.cpp
The file was modifiedlibc/utils/UnitTest/FuchsiaTest.h
The file was modifiedlibc/src/ctype/isascii.h
Commit f85b1531666d12e6ca9b29217b5c5da30dfd93cf by douglas.yung
Add -fexceptions to test as it uses them and fails on platforms where it is not on by default (like the PS4).
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/readability-function-cognitive-complexity.cpp
Commit b894a9fb237345db64d14ce3881d3195e124df0d by craig.topper
[RISCV] Optimize select_cc after fp compare expansion

Some FP compares expand to a sequence ending with (xor X, 1) to invert the result. If
the consumer is a select_cc we can likely get rid of this xor by fixing
up the select_cc condition.

This patch combines (select_cc (xor X, 1), 0, setne, trueV, falseV) -
(select_cc X, 0, seteq, trueV, falseV) if we can prove X is 0/1.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D94546
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/half-select-fcmp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/test/CodeGen/RISCV/double-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-select-fcmp.ll
Commit 4fcb25583c3ccbe10c4367d02086269e5fa0bb87 by alexandre.ganea
Re-land [Support] On Windows, take the affinity mask into account

The number of hardware threads available to a ThreadPool can be limited if setting an affinity mask.
For example:

    > start /B /AFFINITY 0xF lld-link.exe ...

Would let LLD only use 4 hyper-threads.

Previously, there was an outstanding issue on Windows Server 2019 on dual-CPU machines, which was preventing from using both CPU sockets. In normal conditions, when no affinity mask was set, ProcessorGroup::AllThreads was different from ProcessorGroup::UsableThreads. The previous code in llvm/lib/Support/Windows/Threading.inc L201 was improperly assuming those two values to be equal, and consequently was limiting the execution to only one CPU socket.

Differential Revision: https://reviews.llvm.org/D92419
The file was modifiedllvm/lib/Support/Program.cpp
The file was modifiedllvm/lib/Support/Windows/Threading.inc
The file was modifiedllvm/unittests/Support/ThreadPool.cpp
The file was modifiedllvm/lib/Support/Windows/Program.inc
The file was modifiedllvm/lib/Support/Unix/Program.inc
The file was modifiedllvm/include/llvm/Support/Program.h
Commit 5b42fd8dd4e7e29125a09a41a33af7c9cb57d144 by tejohnson
[LTO] Test format fix (NFC)

As requested in D91583, use ';;' instead of ';' to preceed comments in
lld test. I did this in the equivalent gold test as well.
The file was modifiedlld/test/ELF/lto/devirt_vcall_vis_public.ll
The file was modifiedllvm/test/tools/gold/X86/devirt_vcall_vis_public.ll
Commit 8a53a7375a86a5a89ba124de9e17aa5701544104 by selliott
[RISCV][NFC] Regenerate Calling Convention Tests

This regenerates these tests using utils/update_llc_test_checks.py so
that future changes in this area don't have the noise of lots of `@plt`
lines being added.

I also removed the `nounwind`s from the stack-realignment.ll test to
increase coverage on the generated call frame information.
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-gprs.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
The file was modifiedllvm/test/CodeGen/RISCV/stack-realignment.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
The file was modifiedllvm/test/CodeGen/RISCV/vararg.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64.ll
Commit a55a0a3056b8163d9e709b534bd737730fbb5d44 by youngar17
[mlir] Remove over specified memory effects

The standard and gpu dialect both have `alloc` operations which use the
memory effect `MemAlloc`.  In both cases, it is specified on both  the
operation itself and on the result.  This results in two memory effects
being created for these operations.  When `MemAlloc` is defined on an
operation, it represents some background effect which the compiler
cannot reason about, and  inhibits the ability of the compiler to
remove dead `std.alloc` operations.  This change removes the uneeded
`MemAlloc` effect from these operations and leaves the effect on the
result, which allows dead allocs to be erased.

There is the same problem, but to a lesser extent, with MemFree, MemRead
and MemWrite. Over-specifying these traits is not currently inhibiting
any optimization.

Differential Revision: https://reviews.llvm.org/D94662
The file was modifiedmlir/docs/Interfaces.md
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/test/Dialect/Linalg/sparse_3d.mlir
The file was modifiedmlir/test/Transforms/canonicalize.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_2d.mlir
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
The file was modifiedmlir/test/Dialect/Linalg/sparse_1d.mlir
Commit 4183999e0fe1ffbc8bdb2f06f2e5f210a0c94e35 by sam.mccall
[clangd] Reduce logspam for CDB scanning
The file was modifiedclang-tools-extra/clangd/GlobalCompilationDatabase.cpp
Commit 722ae10907e06a0bafa00c557e5242b53419a3ce by ravishankarm
[mlir][Linalg] Add canonicalization to remove no-op linalg operations.

linalg.generic/indexed_generic operations on tensors whose body is
just yielding the (non-induction variable) arguments of the operation
can be canonicalized by replacing uses of the result with the
corresponding arguments.

Differential Revision: https://reviews.llvm.org/D94581
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
Commit b21905dfe3797289791443661540b72cb43dfdf3 by spatel
[SLP] remove unnecessary state in matching reductions

This is NFC-intended. I'm still trying to figure out
how the loop where this is used works. It does not
seem like we require this data at all, but it's
hard to confirm given the complicated predicates.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 547b032ccc8e1da5d1716afeb0afa8988e129fd0 by tianshilei1992
[OpenMP] Remove omptarget-nvptx from deps as it is no longer a valid target

`omptarget-nvptx` is still a dependence for `check-libomptarget-nvtpx`
although it has been removed by D94573.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D94725
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/test/CMakeLists.txt
Commit 774c9c6ef3addc735939a388965a0a694bbd4f57 by ravishankarm
[mlir][Linalg] Add canonicalization of linalg op -> dim op.

Add canonicalization to replace use of the result of a linalg
operation on tensors in a dim operation, to use one of the operands of
the linalg operations instead. This allows the linalg op itself to be
deleted when all its non-dim uses are removed (say through tiling, etc.)

Differential Revision: https://reviews.llvm.org/D93076
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/include/mlir/IR/AffineExprVisitor.h
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgTypes.h
Commit 42444d0cf0c9cf92f89acf16f11f3b7242d81619 by ravishankarm
[mlir][Linalg] NFC: Verify tiling on linalg.generic operation on tensors.

With the recent changes to linalg on tensor semantics, the tiling
operations works out-of-the-box for generic operations. Add a test to
verify that and some minor refactoring.

Differential Revision: https://reviews.llvm.org/D93077
The file was modifiedmlir/include/mlir/IR/AffineMap.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
The file was modifiedmlir/test/Dialect/Linalg/tile-tensors.mlir
Commit 6e7094c14b22a202c15959316033c164d7a84122 by jonathanchesterfield
[libomptarget][nvptx][nfc] Move target_impl functions out of header

[libomptarget][nvptx][nfc] Move target_impl functions out of header

This removes most of the differences between the two target_impl.h.

Also change name mangling from C to C++ for __kmpc_impl_*_lock.

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D94728
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/src/target_impl.h
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/src/target_impl.cu
Commit d6acf3c2012b00f06a422e8704609676be7729b2 by tkeith
[flang] Fix use-associated procedure in generic

When a use-associated procedure was included in a generic, we weren't
correctly recording that fact. The ultimate symbol was added rather than
the local symbol.

Also, improve the message emitted for the specific procedure by
mentioning the module it came from.

This fixes one of the problems in https://bugs.llvm.org/show_bug.cgi?id=48648.

Differential Revision: https://reviews.llvm.org/D94696
The file was modifiedflang/test/Semantics/modfile07.f90
The file was modifiedflang/test/Semantics/resolve53.f90
The file was modifiedflang/lib/Semantics/resolve-names.cpp
Commit 036bc798f2ae4d266fe01e70778afe0b3381c088 by Amara Emerson
[AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions.

G_[US]ITOFP users of loads on AArch64 can operate on both gpr and fpr banks for scalars.
Because of this, if their source is a load, then that load can be assigned to an fpr
bank and therefore avoid having to do a cross bank copy via a gpr->fpr conversion.

Differential Revision: https://reviews.llvm.org/D94701
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
Commit 9dfeec853008109b1cbe926c22675c96226040d9 by jiancai
Reland "[AsmParser] make .ascii support spaces as separators"

This relands commit e0963ae274be5b071d1e1b00f5e4e019483c09e9, which was
reverted on commit 82c4153e66fa284729da86a8d6c302d4b8cec86c due to a
test failure, which turned out to be a false positive.
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedllvm/test/MC/AsmParser/directive_ascii.s
Commit 214387c2c694c92fec713f7ad224f10c1aebc1cf by jonathanchesterfield
[libomptarget][nvptx] Reduce calls to cuda header

[libomptarget][nvptx] Reduce calls to cuda header

Remove use of clock_t in favour of a builtin. Drop a preprocessor branch.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D94731
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/src/target_impl.cu
Commit 1fabe6e51917bcd7a1242294069c682fe6dffa45 by yitzhakm
[libTooling] Change `addInclude` to use expansion locs.

This patch changes the default range used to anchor the include insertion to use
an expansion loc.  This ensures that the location is valid, when the user relies
on the default range.

Driveby: extend a FIXME for a problem that was emphasized by this change; fix some spellings.

Differential Revision: https://reviews.llvm.org/D93703
The file was modifiedclang/lib/Tooling/Transformer/RewriteRule.cpp
The file was modifiedclang/include/clang/Tooling/Transformer/RewriteRule.h
Commit 8f283cafddfa8d6d01a94b48cdc5d25817569e91 by Amara Emerson
[AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP.

In order to import patterns for these, we need to define new ops that can map to
the AArch64ISD::[SU]ITOF nodes. We then transform fpr->fpr variants of the generic
opcodes to these custom opcodes in preisel-lowering. We have to do it here and
not the PostLegalizer combiner because this has to run after regbankselect.

Differential Revision: https://reviews.llvm.org/D94702
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
Commit 2423ec583761304f93b5d01493a26aeb11cb5b8f by chennngwang
[libc] Add memmove implementation.

Use `memcpy` rather than copying bytes one by one, for there might be large
size structs to move.

Reviewed By: gchatelet, sivachandra

Differential Revision: https://reviews.llvm.org/D93195
The file was addedlibc/src/string/memmove.cpp
The file was modifiedlibc/config/linux/aarch64/entrypoints.txt
The file was modifiedlibc/src/string/CMakeLists.txt
The file was addedlibc/src/string/memmove.h
The file was addedlibc/test/src/string/memmove_test.cpp
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt
The file was modifiedlibc/test/src/string/CMakeLists.txt
Commit 9bcc0d1040ddd63b7f82e309c0d5feb4e0c9005e by kazu
[CodeGen, Transforms] Use llvm::sort (NFC)
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
The file was modifiedllvm/lib/Transforms/Scalar/NewGVN.cpp
The file was modifiedllvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
The file was modifiedllvm/lib/CodeGen/RDFLiveness.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was modifiedllvm/lib/Transforms/Scalar/ConstraintElimination.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
Commit 2efcbe24a75b2a9ff6d59d242f560dca96e5f7e0 by kazu
[llvm] Use llvm::drop_begin (NFC)
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
The file was modifiedllvm/lib/Analysis/LazyCallGraph.cpp
The file was modifiedllvm/tools/llvm-xray/xray-stacks.cpp
The file was modifiedllvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/lib/Analysis/VFABIDemangling.cpp
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
The file was modifiedllvm/lib/Analysis/ModuleSummaryAnalysis.cpp
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
Commit 7dc3575ef2dc85d92aa3ad916d0eb73a0aa088c9 by kazu
[llvm] Remove redundant return and continue statements (NFC)

Identified with readability-redundant-control-flow.
The file was modifiedllvm/lib/Target/X86/X86IndirectThunks.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
The file was modifiedllvm/lib/Target/X86/X86FlagsCopyLowering.cpp
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.cpp
The file was modifiedllvm/lib/CodeGen/MachinePipeliner.cpp
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
The file was modifiedllvm/tools/llvm-mca/CodeRegion.cpp
The file was modifiedllvm/tools/llvm-profdata/llvm-profdata.cpp
The file was modifiedllvm/lib/FileCheck/FileCheck.cpp
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/tools/llvm-pdbutil/DumpOutputStyle.cpp
The file was modifiedllvm/lib/Support/Unix/Path.inc
The file was modifiedllvm/utils/TableGen/X86FoldTablesEmitter.cpp
The file was modifiedllvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/include/llvm/CodeGen/LiveRegUnits.h
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedllvm/lib/Transforms/IPO/IROutliner.cpp
The file was modifiedllvm/lib/Demangle/MicrosoftDemangleNodes.cpp
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
The file was modifiedllvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/TextAPI/MachO/InterfaceFile.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
Commit 39665d9aabb7cd92d58f8ba45b32a1899922ec01 by yhegde
Add Semantic check for Flang OpenMP 4.5 - 2.7.1  Do Loop restrictions on single directive and firstprivate clause.

Semantic checks added to check the worksharing 'single' region closely nested inside a worksharing 'do' region. And also to check whether the 'do' iteration variable is a variable in 'Firstprivate' clause.

Files:
check-directive-structure.h
check-omp-structure.h
check-omp-structure.cpp

Testcases:
omp-do01-positivecase.f90
omp-do01.f90
omp-do05-positivecase.f90
omp-do05.f90

Reviewed by: Kiran Chandramohan @kiranchandramohan , Valentin Clement @clementval

Differential Revision: https://reviews.llvm.org/D93205
The file was modifiedflang/lib/Semantics/check-directive-structure.h
The file was modifiedflang/test/Semantics/omp-do01.f90
The file was addedflang/test/Semantics/omp-do05-positivecase.f90
The file was addedflang/test/Semantics/omp-do01-positivecase.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.h
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
The file was modifiedflang/test/Semantics/omp-do05.f90
Commit 5508516b06633e95fb5c2d6a5e196e4dcaa72c8d by ajcbik
[mlir][sparse] retry sparse-only for cyclic iteration graphs

This is a very minor improvement during iteration graph construction.
If the first attempt considering the dimension order of all tensors fails,
a second attempt is made using the constraints of sparse tensors only.
Dense tensors prefer dimension order (locality) but provide random access
if needed, enabling the compilation of more sparse kernels.

Reviewed By: penpornk

Differential Revision: https://reviews.llvm.org/D94709
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
The file was addedmlir/test/Dialect/Linalg/sparse_nd.mlir
Commit c495dfe0268bc2be8737725d657411baa1399e9d by Jan Svoboda
[clang][cli] NFC: Decrease the scope of ParseLangArgs parameters

Instead of passing the whole `TargetOptions` and `PreprocessorOptions` to `ParseLangArgs` give it only the necessary members.
This makes tracking the dependencies between various parsers and option groups easier.

Reviewed By: Bigcheese

Differential Revision: https://reviews.llvm.org/D94674
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Frontend/CompilerInvocation.h
Commit 1a49944b59dbbfd62bd860b564919087f274a5bf by Jan Svoboda
[clang][cli] NFC: Decrease the scope of ParseCodeGenArgs parameters

Instead of passing the whole `TargetOptions` and `FrontendOptions` to `ParseCodeGenArgs` give it only the necessary members.
This makes tracking the dependencies between various parsers and option groups easier.

Reviewed By: Bigcheese

Differential Revision: https://reviews.llvm.org/D94675
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
Commit b6575bfd0eeb5a364dd2e4f4a2e461679da1f8a9 by Jan Svoboda
[clang][cli] Specify KeyPath prefixes via TableGen classes

It turns out we need to handle `LangOptions` separately from the rest of the options. `LangOptions` used to be conditionally parsed only when `!(DashX.getFormat() == InputKind::Precompiled || DashX.getLanguage() == Language::LLVM_IR)` and we need to restore this order (for more info, see D94682).

We could do this similarly to how `DiagnosticOptions` are handled: via a counterpart to the `IsDiag` mix-in (e.g. `IsLang`). These mix-ins would prefix the option key path with the appropriate `CompilerInvocation::XxxOpts` member. However, this solution would be problematic, as we'd now have two kinds of options (`Lang` and `Diag`) with seemingly incomplete key paths in the same file. To understand what `CompilerInvocation` member an option affects, one would need to read the whole option definition and notice the `IsDiag` or `IsLang` class.

Instead, this patch introduces more robust way to handle different kinds of options separately: via the `KeyPathAndMacroPrefix` class. We have one specialization of that class per `CompilerInvocation` member (e.g. `LangOpts`, `DiagnosticOpts`, etc.). Now, instead of specifying a key path with `"LangOpts->UndefPrefixes"`, we use `LangOpts<"UndefPrefixes">`. This keeps the readability intact (you don't have to look for the `IsLang` mix-in, the key path is complete on its own) and allows us to specify a custom macro prefix within `LangOpts`.

Reviewed By: Bigcheese

Differential Revision: https://reviews.llvm.org/D94676
The file was modifiedllvm/unittests/Option/OptionMarshallingTest.cpp
The file was modifiedllvm/unittests/Option/Opts.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedllvm/include/llvm/Option/OptParser.td
Commit b54337070b198cf66356a4ee3e420666151a2023 by t-kawashima
[AArch64] Add Fujitsu A64FX scheduling model

Basic support of A64FX was added in D75594 but its scheduling model
was missing. This commit adds the scheduling model. Also, this commit
amends/adds some subtarget parameters of A64FX.

The A64FX Microarchitecture Manual, which is source information of
this commit, is on GitHub.

https://github.com/fujitsu/A64FX/

Differential Revision: https://reviews.llvm.org/D93791
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.cpp
The file was modifiedllvm/test/CodeGen/AArch64/preferred-function-alignment.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-combiner-madd.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
The file was addedllvm/lib/Target/AArch64/AArch64SchedA64FX.td
Commit 38dfce706f796dc109ea495dd69a8cb4c8fa819d by wingo
[WebAssembly] Add support for table linking to wasm-ld

This patch adds support to wasm-ld for linking multiple table references
together, in a manner similar to wasm globals. The indirect function
table is synthesized as needed.

To manage the transitional period in which the compiler doesn't yet
produce TABLE_NUMBER relocations and doesn't residualize table symbols,
the linker will detect object files which have table imports or
definitions, but no table symbols. In that case it will synthesize
symbols for the defined and imported tables.

As a change, relocatable objects are now written with table symbols,
which can cause symbol renumbering in some of the tests. If no object
file requires an indirect function table, none will be written to the
file. Note that for legacy ObjFile inputs, this test is conservative: as
we don't have relocs for each use of the indirecy function table, we
just assume that any incoming indirect function table should be
propagated to the output.

Differential Revision: https://reviews.llvm.org/D91870
The file was modifiedlld/wasm/Driver.cpp
The file was modifiedlld/wasm/InputFiles.h
The file was modifiedlld/wasm/SymbolTable.cpp
The file was modifiedlld/test/wasm/alias.s
The file was modifiedlld/wasm/Symbols.h
The file was modifiedlld/wasm/SyntheticSections.h
The file was modifiedlld/test/wasm/weak-alias.ll
The file was modifiedlld/test/wasm/stack-pointer.ll
The file was modifiedlld/test/wasm/local-symbols.ll
The file was modifiedlld/wasm/SymbolTable.h
The file was modifiedlld/test/wasm/pie.ll
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/wasm/MarkLive.cpp
The file was modifiedlld/test/wasm/locals-duplicate.test
The file was modifiedlld/test/wasm/init-fini.ll
The file was modifiedlld/wasm/Symbols.cpp
The file was modifiedlld/test/wasm/shared.ll
The file was modifiedlld/wasm/Writer.cpp
The file was modifiedlld/test/wasm/section-symbol-relocs.yaml
The file was modifiedlld/wasm/SyntheticSections.cpp
The file was modifiedlld/test/wasm/signature-mismatch.ll
Commit 33be50daa9ce1074c3b423a4ab27c70c0722113a by nikita.ppv
Revert "Reapply "ADT: Fix reference invalidation in SmallVector::push_back and single-element insert""

This reverts commit 260a856c2abcef49c7cb3bdcd999701db3e2af38.
This reverts commit 3043e5a5c33c4c871f4a1dfd621a8839f9a1f0b3.
This reverts commit 49142991a685bd427d7e877c29c77371dfb7634c.

This change had a larger than anticipated compile-time impact,
possibly because the small value optimization is not working as
intended. See D93779.
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
The file was modifiedllvm/unittests/ADT/SmallVectorTest.cpp
Commit 168be4208304e36d3bb156b5c413b340a391383e by qiucofan
[Clang] Mutate long-double math builtins into f128 under IEEE-quad

Under -mabi=ieeelongdouble on PowerPC, IEEE-quad floating point semantic
is used for long double. This patch mutates call to related builtins
into f128 version on PowerPC. And in theory, this should be applied to
other targets when their backend supports IEEE 128-bit style libcalls.

GCC already has these mutations except nansl, which is not available on
PowerPC along with other variants (nans, nansf).

Reviewed By: RKSimon, nemanjai

Differential Revision: https://reviews.llvm.org/D92080
The file was modifiedclang/test/CodeGen/math-builtins-long.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
Commit 1185d3f43d2186fa9291fe7779abf48d9b962ef4 by grimar
[llvm-readobj] - Fix the compilation with GCC < 7.0.

This addressed post commit comments for D93900.

GCC had an issue and requires placing a specialization of
`printUnwindInfo` to a namespace to compile:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56480
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 89e84dec1879417fb7eb96edaa55dac7eca204ab by Amara Emerson
[AArch64][GlobalISel] Fix fallbacks introduced for G_SITOFP in 8f283cafddfa8d6d01a94b48cdc5d25817569e91

If we have an integer->fp convert that has differing sizes, e.g. s32 to s64,
then don't try to convert it to AArch64::G_SITOF since it won't select.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Commit 78036360573c35ea9e6a697d2eed92db893b4850 by ikudrin
[libcxx testing] Fix UB in tests for std::lock_guard

If mutex::try_lock() is called in a thread that already owns the mutex,
the behavior is undefined. The patch fixes the issue by creating another
thread, where the call is allowed.

Differential Revision: https://reviews.llvm.org/D94656
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.guard/mutex.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.guard/adopt_lock.pass.cpp
Commit 104a9f99ccab9d6dbc07a70f569246c23feaf4c1 by AlokKumar.Sharma
[Debuginfo][DW_OP_implicit_pointer] (1/7) Support for DW_OP_LLVM_implicit_pointer

New dwarf operator DW_OP_LLVM_implicit_pointer is introduced (present only in LLVM IR)
This operator is required as it is different than DWARF operator
DW_OP_implicit_pointer in representation and specification (number
and types of operands) and later can not be used as multiple level.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D84113
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/lib/IR/DebugInfoMetadata.cpp
The file was addedllvm/test/DebugInfo/X86/LLVM_implicit_pointer.ll
The file was modifiedllvm/include/llvm/BinaryFormat/Dwarf.h
The file was modifiedllvm/lib/BinaryFormat/Dwarf.cpp
Commit bfb8f45ef3f46102d290f11039faa82456c920ae by grimar
[llvm-nm] - Move MachO specific logic out from the dumpSymbolNamesFromObject(). NFC.

`dumpSymbolNamesFromObject` is the method that dumps symbol names.

It has 563 lines, mostly because of huge piece of MachO specific code.
In this patch I move it to separate helper method.

The new size of `dumpSymbolNamesFromObject` is 93 lines. With it it becomes
much easier to maintain it.

I had to change the type of 2 name fields to `std::string`, because MachO logic
uses temporarily buffer strings (e.g `ExportsNameBuffer`, `BindsNameBuffer` etc):

```
  std::string ExportsNameBuffer;
  raw_string_ostream EOS(ExportsNameBuffer);
```

these buffers were moved to `dumpSymbolsFromDLInfoMachO` by this patch and
invalidated after return. Technically, before this patch we had a situation
when local pointers (symbol names) were assigned to members of global static `SymbolList`,
what is dirty by itself.

Differential revision: https://reviews.llvm.org/D94667
The file was modifiedllvm/tools/llvm-nm/llvm-nm.cpp