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Took 1 hr 12 min

Success Build clang-r362958-t57405-b57405.tar.gz (Jun 10, 2019 10:08:41 AM)


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Build Log

Revision: 362564
  1. [ExecutionEngine] Fix rL362941: Add UnaryOperator visitor to the interpreter

    Missed break statements. This was D62881. (detail)
    by mcinally
  2. [AMDGPU] Optimize image_[load|store]_mip

    Replace image_load_mip/image_store_mip
    with image_load/image_store if lod is 0.

    Reviewers: arsenm, nhaehnle

    Reviewed By: arsenm

    Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

    Tags: #llvm

    Differential Revision: (detail)
    by Piotr Sobczak
  3. Revert rL362953 and its followup rL362955.

    These caused a build failure because I managed not to notice they
    depended on a later unpushed commit in my current stack. Sorry about
    that. (detail)
    by statham
  4. [ARM] Add the non-MVE instructions in Arm v8.1-M.

    This should have been part of r362953, but I had a finger-trouble
    incident and committed the old rather than new version of the patch.
    Sorry. (detail)
    by statham
  5. [InstCombine] allow unordered preds when canonicalizing to fabs()

    We have a known-never-nan value via 'nnan', so an unordered predicate
    is the same as its ordered sibling.

    Similar to:
    rL362937 (detail)
    by spatel
  6. [ARM] Add the non-MVE instructions in Arm v8.1-M.

    This adds support for the new family of conditional selection /
    increment / negation instructions; the low-overhead branch
    instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole
    list of registers at once; the new VMRS/VMSR and VLDR/VSTR
    instructions to get data in and out of 8.1-M system registers,
    particularly including the new VPR register used by MVE vector

    To support this, we also add a register name 'zr' (used by the CSEL
    family to force one of the inputs to the constant 0), and operand
    types for lists of registers that are also allowed to include APSR or
    VPR (used by CLRM). The VLDR/VSTR instructions also need some new
    addressing modes.

    The low-overhead branch instructions exist in their own separate
    architecture extension, which we treat as enabled by default, but you
    can say -mattr=-lob or equivalent to turn it off.

    Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover

    Reviewed By: samparker

    Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail)
    by statham
  7. [DA] Add an option to control delinearization validity checks

    Summary: Dependence Analysis performs static checks to confirm validity
    of delinearization. These checks often fail for 64-bit targets due to
    type conversions and integer wrapping that prevent simplification of the
    SCEV expressions. These checks would also fail at compile-time if the
    lower bound of the loops are compile-time unknown.
    Author: bmahjour
    Reviewer: Meinersbur, jdoerfert, kbarton, dmgreen, fhahn
    Reviewed By: Meinersbur, jdoerfert, dmgreen
    Subscribers: fhahn, hiraditya, javed.absar, llvm-commits, Whitney,
    Tag: LLVM
    Differential Revision: (detail)
    by whitneyt
  8. [DebugInfo] Terminate all location-lists at end of block

    This commit reapplies r359426 (which was reverted in r360301 due to
    performance problems) and rolls in D61940 to address the performance problem.
    I've combined the two to avoid creating a span of slow-performance, and to
    ease reverting if more problems crop up.

    The summary of D61940: This patch removes the "ChangingRegs" facility in
    DbgEntityHistoryCalculator, as its overapproximate nature can produce incorrect
    variable locations. An unchanging register doesn't mean a variable doesn't
    change its location.

    The patch kills off everything that calculates the ChangingRegs vector.
    Previously ChangingRegs spotted epilogues and marked registers as unchanging if
    they weren't modified outside the epilogue, increasing the chance that we can
    emit a single-location variable record. Without this feature,
    debug-loc-offset.mir and pr19307.mir become temporarily XFAIL. They'll be
    re-enabled by D62314, using the FrameDestroy flag to identify epilogues, I've
    split this into two steps as FrameDestroy isn't necessarily supported by all

    The logic for terminating variable locations at the end of a basic block now
    becomes much more enjoyably simple: we just terminate them all.

    Other test changes: inlined-argument.ll becomes XFAIL, but for a longer term.
    The current algorithm for detecting that a variable has a single-location
    doesn't work in this scenario (inlined function in multiple blocks), only other
    bugs were making this test work. fission-ranges.ll gets slightly refreshed too,
    as the location of "p" is now correctly determined to be a single location.

    Differential Revision: (detail)
    by jmorse
  9. [InstCombine] add tests for fabs() with unordered preds; NFC (detail)
    by spatel
  10. [IRBuilder] Add CreateFNegFMF(...) to the IRBuilder

    Differential Revision: (detail)
    by mcinally
  11. [InstCombine] fix bug in canonicalization to fabs()

    Forgot to translate the predicate clauses in rL362943. (detail)
    by spatel
  12. [InstCombine] change canonicalization to fabs() to use FMF on fsub

    Similar to rL362909:
    This isn't the ideal fix (use FMF on the select), but it's still an
    improvement until we have better FMF propagation to selects and other
    FP math operators.

    I don't think there's much risk of regression from this change by
    not including the FMF on the fcmp any more. The nsz/nnan FMF
    should be the same on the fcmp and the fsub because they have the
    same operand. (detail)
    by spatel
  13. [ARM] Disallow PC, and optionally SP, in VMOVRH and VMOVHR.

    Arm v8.1-M supports the VMOV instructions that move a half-precision
    value to and from a GPR, but not if the GPR is SP or PC.

    To fix this, I've changed those instructions to use the rGPR register
    class instead of GPR. rGPR always excludes PC, and it excludes SP
    except in the presence of the HasV8Ops target feature (i.e. Arm v8-A).
    So the effect is that VMOV.F16 to and from PC is now illegal
    everywhere, but VMOV.F16 to and from SP is illegal only on non-v8-A
    cores (which I believe is all as it should be).

    Reviewers: dmgreen, samparker, SjoerdMeijer, ostannard

    Reviewed By: ostannard

    Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail)
    by statham
  14. [ExecutionEngine] Add UnaryOperator visitor to the interpreter

    This is to support the unary FNeg instruction.

    Differential Revision: (detail)
    by mcinally
  15. [yaml2obj] - Remove TODOs from dynsymtab-implicit-sections-size-content.yaml. NFCI.

    Now when is fixed,
    we can remove these TODOs. (detail)
    by grimar
Revision: 362564
  1. Re-land "[CodeComplete] Improve overload handling for C++ qualified and ref-qualified methods."

    ShadowMapEntry is now really, truly a normal class. (detail)
    by sammccall
  2. Revert "[CodeComplete] Improve overload handling for C++ qualified and ref-qualified methods."

    This reverts commit r362924, which causes a double-free of ShadowMapEntry. (detail)
    by sammccall
Revision: 362564
  1. [clangd] Revamp textDocument/onTypeFormatting.

    The existing implementation (which triggers on }) is fairly simple and
    has flaws:
    - doesn't trigger frequently/regularly enough (particularly in editors that type the }
    for you)
    - often reformats too much code around the edit
    - has jarring cases that I don't have clear ideas for fixing

    This implementation is designed to trigger on newline, which feels to me more
    intuitive than } or ;.
    It does have allow for reformatting after other characters - it has a
    basic behavior and a model for adding specialized behavior for
    particular characters. But at least initially I'd stick to advertising
    \n in the capabilities.

    This also handles comment splitting: when you insert a line break inside
    a line comment, it will make the new line into an aligned line comment.

    Working on tests, but want people to patch it in and try it - it's hard to
    see if "feel" is right purely by looking at a test.

    Reviewers: ilya-biryukov, hokein

    Subscribers: mgorny, ioeric, MaskRay, jkorous, arphaman, kadircet, cfe-commits

    Tags: #clang

    Differential Revision: (detail)
    by sammccall

Started by upstream project relay-test-suite-verify-machineinstrs build number 5428
originally caused by:

This run spent:

  • 40 min waiting;
  • 1 hr 12 min build duration;
  • 1 hr 12 min total from scheduled to completion.