SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads (details)
  2. AMDGPU/GlobalISel: Select G_PTR_MASK (details)
  3. AMDGPU: Remove code address space predicates (details)
  4. AMDGPU/GlobalISel: Fix regbankselect for uniform extloads (details)
  5. Fix typo in comment noticed in D60295. NFCI. (details)
  6. AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant (details)
  7. LLDB - Simplify GetProgramFileSpec (details)
  8. AMDGPU/GlobalISel: Select atomic loads (details)
  9. [ARM] Fix loads and stores for predicate vectors (details)
  10. [yaml2obj] Simplify p_filesz/p_memsz computing (details)
  11. Revert "[MachineCopyPropagation] Remove redundant copies after TailDup (details)
  12. [clangd] Attempt to fix failing Windows buildbots. (details)
  13. AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC (details)
  14. AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE (details)
  15. [GlobalISel][AArch64] Handle tail calls with non-void return types (details)
  16. [SLP] add test for over-vectorization (PR33958); NFC (details)
  17. AMDGPU: Move MnemonicAlias out of instruction def hierarchy (details)
  18. [mips] Fix decoding of microMIPS JALX instruction (details)
Commit fdb70301172025ee77d3c77c28e18fd02ba5503f by Matthew.Arsenault
AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads
The pointer is always a VGPR. Also fix hardcoding the pointer size to
64.
llvm-svn: 371411
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit c34b4036ffe115c7cc03b9236922e98b78adb8b1 by Matthew.Arsenault
AMDGPU/GlobalISel: Select G_PTR_MASK
llvm-svn: 371412
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit ebbd6e49768271297d17bcecd22eae2128e24e26 by Matthew.Arsenault
AMDGPU: Remove code address space predicates
Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due to
not be reported as legal.
llvm-svn: 371413
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
Commit 02eb308387d73de035492c0ae56ce167eaa97a5f by Matthew.Arsenault
AMDGPU/GlobalISel: Fix regbankselect for uniform extloads
There are no scalar extloads.
llvm-svn: 371414
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Commit 9ede7c03956376105130421c786e1360e948b290 by llvm-dev
Fix typo in comment noticed in D60295. NFCI.
llvm-svn: 371415
The file was modifiedllvm/include/llvm/CodeGen/SwitchLoweringUtils.h
Commit d8409b178ed4b5af52eb82190b5d1c846ed8b63c by Matthew.Arsenault
AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant
loads
llvm-svn: 371416
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit f707dac742f39774aef446f275cc70f43586312a by David CARLIER
LLDB - Simplify GetProgramFileSpec
Reviewers: zturner, emaste
Reviewed By: emaste
Differential Revision: https://reviews.llvm.org/D46518
llvm-svn: 371417
The file was modifiedlldb/source/Host/freebsd/HostInfoFreeBSD.cpp
Commit 63e6d8db1cbfe75142669c55819c655c600f00a5 by Matthew.Arsenault
AMDGPU/GlobalISel: Select atomic loads
A new check for an explicitly atomic MMO is needed to avoid incorrectly
matching pattern for non-atomic loads
llvm-svn: 371418
The file was modifiedllvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
Commit 2b7089949eda508203eb23c835d6a295eb00b46b by david.green
[ARM] Fix loads and stores for predicate vectors
These predicate vectors can usually be loaded and stored with a single
instruction, a VSTR_P0. However this instruction will store the entire
P0 predicate, 16 bits, zeroextended to 32bits. Each lane of the the
v4i1/v8i1/v16i1 representing 4/2/1 bits.
As far as I understand, when llvm says "store this v4i1", it really does
need to store 4 bits (or 8, that being the size of a byte, with this
bottom 4 as the interesting bits). For example a bitcast from a v8i1 to
a i8 is defined as a store followed by a load, which is how the code is
expanded.
So this instead lowers the v4i1/v8i1 load/store through some shuffles to
get the bits into the correct positions. This, as you might imagine, is
not as efficient as a single instruction. But I believe it is needed for
correctness. v16i1 equally should not load/store 32bits, only storing
the 16bits of data. Stack loads/stores are still using the VSTR_P0 (as
can be seen by the test not changing). This is fine as they are
self-consistent, it is only "externally observable loads/stores" (from
our point of view) that need to be corrected.
Differential revision: https://reviews.llvm.org/D67085
llvm-svn: 371419
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-load.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-store.ll
Commit c28f3e6e2c3ef1323ed18d4c485681bb4ff72ced by maskray
[yaml2obj] Simplify p_filesz/p_memsz computing
This fixes a bug as well. When "FileSize:" (p_filesz) is specified and
different from the actual value, the following code probably should not
use PHeader.p_filesz:
  if (SHeader->sh_offset == PHeader.p_offset + PHeader.p_filesz)
   PHeader.p_memsz += SHeader->sh_size;
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D67256
llvm-svn: 371420
The file was modifiedllvm/test/tools/yaml2obj/program-header-size-offset.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
Commit d9c4060bd5c9e6c24a96cd7e4501be30301dad9d by gribozavr
Revert "[MachineCopyPropagation] Remove redundant copies after TailDup
via machine-cp"
This reverts commit 371359. I'm suspecting a miscompile, I posted a
reproducer to https://reviews.llvm.org/D65267.
llvm-svn: 371421
The file was modifiedllvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
The file was modifiedllvm/lib/CodeGen/MachineCopyPropagation.cpp
The file was modifiedllvm/test/CodeGen/X86/mul-i512.ll
The file was modifiedllvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
Commit 6d7fba6aae28e313ba3e457ad9eff13b5e541204 by ibiryukov
[clangd] Attempt to fix failing Windows buildbots.
The assertion is failing on Windows, probably because path separator is
different.
For the failure see:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/28072/steps/test/logs/stdio
llvm-svn: 371422
The file was modifiedclang-tools-extra/clangd/index/CanonicalIncludes.cpp
Commit 182f9248e8f2c11e5aeeb08263c5b56dbf1ea9c6 by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC
Treat this as legal on gfx9 since it can use S_PACK_* instructions for
this.
This isn't used by anything yet. The same will probably apply to 16-bit
G_BUILD_VECTOR without the trunc.
llvm-svn: 371423
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector-trunc.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 64ecca90d4290f670b58111cc46e63b3aa9b72f5 by Matthew.Arsenault
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE
Handle the simple case that lowers to a constant.
llvm-svn: 371424
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-size.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit bfb00e3d536e4a907f257684eba7836951677864 by Jessica Paquette
[GlobalISel][AArch64] Handle tail calls with non-void return types
Just return once you emit the call, which is exactly what SelectionDAG
does in this situation.
Update call-translator-tail-call.ll.
Also update dllimport.ll to show that we tail call here in GISel again.
Add
-verify-machineinstrs to the GISel line too, to defend against verifier
failures.
Differential revision: https://reviews.llvm.org/D67282
llvm-svn: 371425
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
The file was modifiedllvm/test/CodeGen/AArch64/dllimport.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64CallLowering.cpp
Commit c0728eac15b416206a715f4ee84e5956aa169c91 by spatel
[SLP] add test for over-vectorization (PR33958); NFC
llvm-svn: 371426
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
Commit d2a9516a6d08c3edd7c5484f4d10f4b38b48c9d6 by Matthew.Arsenault
AMDGPU: Move MnemonicAlias out of instruction def hierarchy
Unfortunately MnemonicAlias defines a "Predicates" field just like an
instruction or pattern, with a somewhat different interpretation.
This ends up overriding the intended Predicates set by PredicateControl
on the pseudoinstruction defintions with an empty list. This allowed
incorrectly selecting instructions that should have been rejected due to
the SubtargetPredicate from patterns on the instruction definition.
This does remove the divergent predicate from the 64-bit shift patterns,
which were already not used for the 32-bit shift, so I'm not sure what
the point was. This also removes a second, redundant copy of the 64-bit
divergent patterns.
llvm-svn: 371427
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOPInstructions.td
Commit 56e4ea2bff9eb2f43b20a68951e6263ad3c9022f by simon
[mips] Fix decoding of microMIPS JALX instruction
microMIPS jump and link exchange instruction stores a target in a
26-bits field. Despite other microMIPS JAL instructions these bits are
target address shifted right 2 bits [1]. The patch fixes the JALX
instruction decoding and uses 2-bit shift.
[1] MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set
Differential Revision: https://reviews.llvm.org/D67320
llvm-svn: 371428
The file was modifiedlld/test/ELF/mips-micro-cross-calls.s
The file was modifiedllvm/lib/Target/Mips/MicroMipsInstrInfo.td
The file was modifiedllvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
The file was modifiedllvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
The file was modifiedllvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt