SuccessChanges

Summary

  1. Use getLocation() in "too few/too many arguments" diagnostic (details)
  2. [mlir] Add short readme.txt to docs directory (details)
  3. Hopefully fixing a failing build bot. (details)
  4. Cover cases like (b && c && b) in the redundant expression check. (details)
  5. [InstCombine] Add more tests for icmp+and+ashr; NFC (details)
  6. [InstCombine] Relax preconditions for ashr+and+icmp fold (PR44754) (details)
  7. [PowerPC][NFC] Add defines to help creating the SpillSlot arrays. (details)
  8. [InstCombine] Fix multi-use handling in cttz transform (details)
  9. [InstCombine] Fix worklist management when simplifying demanded bits (details)
  10. [BuildLibCalls] Accept IRBuilderBase; NFC (details)
  11. [LoopUtils] Accept IRBuilderBase; NFC (details)
  12. [SimplifyLibCalls] Accept IRBuilderBase; NFC (details)
  13. [VectorUtils] Accept IRBuilderBase; NFC (details)
  14. [lldb] [nfc] Separate DIERef vs. user_id_t: GetForwardDeclClangTypeToDie() (details)
  15. [SLPVectorizer] Do not assume extracelement idx is a ConstantInt. (details)
  16. [ARM,MVE] Add vbrsrq intrinsics family (details)
  17. Revert "[llvm-exegesis] Improve error reporting in Assembler.cpp" (details)
  18. [scudo][standalone] Shift some data from dynamic to static (details)
Commit 260b91f379c8f86d3d6008648b3f2a945a007888 by aaron
Use getLocation() in "too few/too many arguments" diagnostic

Use the more accurate location when emitting the location of the
function being called's prototype in diagnostics emitted when calling
a function with an incorrect number of arguments.

In particular, avoids showing a trace of irrelevant macro expansions
for "MY_EXPORT static int AwesomeFunction(int, int);". Fixes PR#23564.
The file was modifiedclang/test/Sema/exprs.c
The file was modifiedclang/test/Misc/serialized-diags.c
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit fa7d04a0d3f40d1b9997775f24e9c6032011e15f by jpienaar
[mlir] Add short readme.txt to docs directory

Summary:
Refer folks to the main website and make it explicit that the rendered
output is what is of interest and that the GitHub viewing experience may
not match (even though we are trying to keep it as close as possible, the
renderers do differ).

Differential Revision: https://reviews.llvm.org/D74739
The file was addedmlir/docs/README.txt
Commit 66c01627719f088bff9a0d09655a8ca0842b2c82 by aaron
Hopefully fixing a failing build bot.

Should fix the changes from 260b91f379c8f86d3d6008648b3f2a945a007888.
The file was modifiedclang/bindings/python/tests/cindex/test_diagnostics.py
Commit 5e7d0ebf735a8b70f92acd1f91c7c45423e611cc by aaron
Cover cases like (b && c && b) in the redundant expression check.

readability-redundant-expression now detects expressions where a logical
or bitwise operator had equivalent LHS and RHS where the equivalent
operands were separated by more operands.
The file was modifiedclang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/misc-redundant-expression.cpp
Commit 9bc6bc2d8cebd34f4449524dba6b199aa86f0f28 by nikita.ppv
[InstCombine] Add more tests for icmp+and+ashr; NFC
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
Commit 9adedd146d53101059a3884c2453f15646bc863a by nikita.ppv
[InstCombine] Relax preconditions for ashr+and+icmp fold (PR44754)

Fix for https://bugs.llvm.org/show_bug.cgi?id=44754. We already have
a fold that converts icmp (and (ashr X, C3), C2), C1 into
icmp (and C2'), C1', but it imposed overly strict requirements on the
transform.

Relax this by checking that both C2 and C1 don't shift out bits
(in a signed sense) when forming the new constants.

Alive proofs (https://rise4fun.com/Alive/PTz0):

    Name: ashr_legal
    Pre: ((C2 << C3) >> C3) == C2 && ((C1 << C3) >> C3) == C1
    %a = ashr i16 %x, C3
    %b = and i16 %a, C2
    %c = icmp i16 %b, C1
    =>
    %d = and i16 %x, C2 << C3
    %c = icmp i16 %d, C1 << C3

    Name: ashr_shiftout_eq
    Pre: ((C2 << C3) >> C3) == C2 && ((C1 << C3) >> C3) != C1
    %a = ashr i16 %x, C3
    %b = and i16 %a, C2
    %c = icmp eq i16 %b, C1
    =>
    %c = false

Note that >> corresponds to ashr here. The case of an equality
comparison has some special handling in this transform, because
it will form to a true/false result if the condition on the comparison
constant it violated.

Differential Revision: https://reviews.llvm.org/D74294
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Commit 3126b556d13fa4d4eca87592b598c3af895292a5 by sd.fertile
[PowerPC][NFC] Add defines to help creating the SpillSlot arrays.

Create preprocessor defines for callee saved floating-point register spill
slots, vector register spill slots, and both 32-bit and 64-bit general
purpose register spill slots. This is an NFC refactor to prepare for
adding ABI compliant callee saves and restores for AIX.
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Commit c9540fe59bbf53223368c18e457f79d3e981a3a5 by nikita.ppv
[InstCombine] Fix multi-use handling in cttz transform

The select-of-cttz transform can currently duplicate cttz intrinsics
and zext/trunc ops. The cause is that it unnecessarily duplicates
the intrinsic and the zext/trunc when setting the "undef_on_zero"
flag to false. However, it's always legal to set the flag from true
to false, so we can make this replacement even if there are extra users.

Differential Revision: https://reviews.llvm.org/D74685
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
Commit 1ab37fad61ab3b44bdb11b6865925321fccb7947 by nikita.ppv
[InstCombine] Fix worklist management when simplifying demanded bits

When simplifying demanded bits, we currently only report the
instruction on which SimplifyDemandedBits was called as changed.
However, this is a recursive call, and the actually modified
instruction will usually be further up the chain. Additionally,
all the intermediate instructions should also be revisited,
as additional combines may be possible after the demanded bits
simplification. We fix this by explicitly adding them back to the
worklist.

Differential Revision: https://reviews.llvm.org/D72944
The file was modifiedllvm/test/Transforms/InstCombine/pr44541.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
The file was modifiedllvm/test/Transforms/InstCombine/select-imm-canon.ll
Commit ed6d30b517b618fb0d0b9b61c4586b7ab7dc74ec by nikita.ppv
[BuildLibCalls] Accept IRBuilderBase; NFC

Accept IRBuilderBase instead of IRBuilder<>. Remove dependency
on IRBuilder from header.
The file was modifiedllvm/lib/Transforms/Utils/BuildLibCalls.cpp
The file was modifiedllvm/include/llvm/Transforms/Utils/BuildLibCalls.h
Commit 28ffe38bbafebf049e4c1f5a5a6b4ce6b00357af by nikita.ppv
[LoopUtils] Accept IRBuilderBase; NFC
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopUtils.h
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
Commit ec6c623ff90ae35ecc272df140e473d98d79a514 by nikita.ppv
[SimplifyLibCalls] Accept IRBuilderBase; NFC
The file was modifiedllvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit f37e899fd73d1a8958246d761eeb306a8846e81a by nikita.ppv
[VectorUtils] Accept IRBuilderBase; NFC
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
The file was modifiedllvm/lib/Analysis/VectorUtils.cpp
Commit aa3e99dc859febba398925afeefb118403e15ab9 by jan.kratochvil
[lldb] [nfc] Separate DIERef vs. user_id_t: GetForwardDeclClangTypeToDie()

Reasons are the same as for D74637.

Differential Revision: https://reviews.llvm.org/D74690
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
Commit e32522ca178acc42e26f21d64ef8fc180ad772bd by flo
[SLPVectorizer] Do not assume extracelement idx is a ConstantInt.

The index of an ExtractElementInst is not guaranteed to be a
ConstantInt. It can be any integer value. Check explicitly for
ConstantInts.

The new test cases illustrate scenarios where we crash without
this patch. I've also added another test case to check the matching
of extractelement vector ops works.

Reviewers: RKSimon, ABataev, dtemirbulatov, vporpo

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D74758
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 63809d365e56512b1b6eac6065547f523d10dbf0 by mikhail.maltsev
[ARM,MVE] Add vbrsrq intrinsics family

Summary:
This patch adds a new MVE intrinsics family, `vbrsrq`: vector bit
reverse and shift right. The intrinsics are compiled into the VBRSR
instruction. Two new LLVM IR intrinsics were also added: arm.mve.vbrsr
and arm.mve.vbrsr.predicated.

Reviewers: simon_tatham, dmgreen, ostannard, MarkMurrayARM

Reviewed By: simon_tatham

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74721
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was addedclang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was addedllvm/test/CodeGen/Thumb2/mve-intrinsics/vbrsrq.ll
Commit 7603bfb4b0a6a90137d47f0182a490fe54bf7ca3 by Milos.Stojanovic
Revert "[llvm-exegesis] Improve error reporting in Assembler.cpp"

This reverts https://reviews.llvm.org/rG63bb9fee525f
due to buildbot failures:
http://lab.llvm.org:8011/builders/clang-ppc64le-rhel/builds/1389
The file was modifiedllvm/tools/llvm-exegesis/lib/Assembler.h
The file was modifiedllvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/Assembler.cpp
Commit fc69967a4b98df34c03a3c57134940688b863dff by kostyak
[scudo][standalone] Shift some data from dynamic to static

Summary:
Most of our larger data is dynamically allocated (via `map`) but it
became an hindrance with regard to init time, for a cost to benefit
ratio that is not great. So change the `TSD`s, `RegionInfo`, `ByteMap`
to be static.

Additionally, for reclaiming, we used mapped & unmapped a buffer each
time, which is costly. It turns out that we can have a static buffer,
and that there isn't much contention on it.

One of the other things changed here, is that we hard set the number
of TSDs on Android to the maximum number, as there could be a
situation where cores are put to sleep and we could miss some.

Subscribers: mgorny, #sanitizers, llvm-commits

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D74696
The file was modifiedcompiler-rt/lib/scudo/standalone/release.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tsd_shared.h
The file was modifiedcompiler-rt/lib/scudo/standalone/wrappers_c.inc
The file was modifiedcompiler-rt/lib/scudo/standalone/bytemap.h
The file was addedcompiler-rt/lib/scudo/standalone/release.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/primary32.h
The file was modifiedcompiler-rt/lib/scudo/standalone/primary64.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tsd_exclusive.h
The file was modifiedcompiler-rt/lib/scudo/standalone/CMakeLists.txt