SuccessChanges

Summary

  1. TableGen: Don't reconstruct CodeGenDAGTarget (details)
  2. [ELF] Parse SHT_GNU_verneed and respect versioned undefined symbols in shared objects (details)
  3. Silence warning from unit test (details)
  4. AMDGPU: Define mode register (details)
  5. AMDGPU: Implement isConstantPhysReg (details)
Commit 421a40b32520f5a3764a974df44f89e7d80bc6b4 by arsenm2
TableGen: Don't reconstruct CodeGenDAGTarget

This is quite expensive and it's already available.

Just ReadLegalValueTypes is taking 4 seconds for me in a debug build
for AMDGPU's -gen-instr-info, and this was introducing a second call.
The file was modifiedllvm/utils/TableGen/InstrInfoEmitter.cpp
Commit e32f04cdc95224589f30148599c362ba37bae7b6 by maskray
[ELF] Parse SHT_GNU_verneed and respect versioned undefined symbols in shared objects

An undefined symbol in a shared object can be versioned, like `f@v1`.
We currently insert `f` as an Undefined into the symbol table, but we
should insert `f@v1` instead.

The string `v1` is inferred from SHT_GNU_versym and SHT_GNU_verneed.
This patch implements the functionality.

Failing to do this can cause two issues:

* If a versioned symbol referenced by a shared object is defined in the
  executable, we will fail to export it.
* If a versioned symbol referenced by a shared object in another object
  file, --no-allow-shlib-undefined may spuriously report an
  "undefined reference to " error. See https://bugs.llvm.org/show_bug.cgi?id=44842
  (Linking -lfftw3 -lm on Arch Linux can cause
  `undefined reference to __log_finite`)

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D80059
The file was addedlld/test/ELF/verneed-shared.s
The file was modifiedlld/ELF/InputFiles.h
The file was modifiedlld/ELF/InputFiles.cpp
The file was addedlld/test/ELF/invalid/verneed-shared.yaml
Commit 286ca0f7fd6bf26923f3df464e6a74d032f242ea by arsenm2
Silence warning from unit test

This was printing about r600 not being a valid subtarget for an amdgcn
triple. This is an awkward place because r600 and amdgcn unfortunately
occupy the same target. Silence the warning by specifying an explicit
subtarget.
The file was modifiedllvm/unittests/MI/LiveIntervalTest.cpp
Commit 2e82667f60237c32d8a10eb04825ff434a3e474c by arsenm2
AMDGPU: Define mode register

This should eventually model FP mode constraints as well as the other
special fields it tracks.
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
Commit 76e3dd0a490d7da25ccf35c29b3b7ec34908f7d6 by arsenm2
AMDGPU: Implement isConstantPhysReg

I don't think any of these registers are used in contexts where this
would do anything yet.
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp