SuccessChanges

Summary

  1. LocalStackSlotAllocation: Swap order of check (details)
  2. AMDGPU: Add baseline test for incorrect SP access (details)
  3. AMDGPU: Clear offset register when using local stack area (details)
  4. Include (Type|Symbol)Record.h less (details)
  5. RegAllocFast: Make self loop live-out heuristic more aggressive (details)
  6. [libc++] Ensure streams are initialized early (details)
  7. Re-land: Add new hidden option -print-changed which only reports changes to IR (details)
  8. [llvm-nm] Use aggregate initialization instead of memset zero (details)
  9. [SLP] add tests for reduction ordering; NFC (details)
  10. ValueEnumerator.cpp - remove duplicate includes. NFCI. (details)
  11. InterferenceCache.cpp - remove duplicate includes. NFCI. (details)
  12. raw_ostream.cpp - remove duplicate includes. NFCI. (details)
  13. DwarfUnit.h - remove unnecessary includes. NFCI. (details)
  14. [GISel] Add new combines for unary FP instrs with constant operand (details)
  15. [Sema][MSVC] warn at dynamic_cast/typeid when /GR- is given (details)
  16. [libFuzzer] Enable entropic by default. (details)
  17. Sema: add support for `__attribute__((__swift_bridge__))` (details)
  18. fix test no-rtti.cpp (details)
  19. [clang][codegen] Skip adding default function attributes on intrinsics. (details)
  20. [AArch64][GlobalISel] Make G_BUILD_VECTOR os <16 x s8> legal. (details)
  21. [gn build] make "all" target build (details)
  22. GlobalISel: Lift store value widening restriction (details)
Commit 8d8a496356dbdf4fcc17caa69fe489d8d87068ac by Matthew.Arsenault
LocalStackSlotAllocation: Swap order of check
The file was modifiedllvm/lib/CodeGen/LocalStackSlotAllocation.cpp
Commit deae5e567d65c49c40abc99d5ad53855c9872d5b by Matthew.Arsenault
AMDGPU: Add baseline test for incorrect SP access
The file was addedllvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
Commit 367248956e93982a73c0441868a562aeb85af5a0 by Matthew.Arsenault
AMDGPU: Clear offset register when using local stack area

eliminateFrameIndex won't fix up the offset register when the direct
frame index reference is moved to a separate move instruction. Switch
the offset to a base 0 (which it probably should be to begin with).
The file was modifiedllvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
Commit e47d2927de79767663f0a0ece0581522fbe40ac4 by rnk
Include (Type|Symbol)Record.h less

Most clients only need CVType and CVSymbol, not structs for every type
and symbol. Move CVSymbol and CVType to CVRecord.h to accomplish this.
Update some of the common headers that need CVSymbol and CVType to use
the new location.
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/SymbolRecord.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/RecordName.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/TypeCollection.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/SymbolRecordHelpers.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/TypeRecordHelpers.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/DebugSymbolsSubsection.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/TypeIndexDiscovery.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/SymbolDumper.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/TypeStreamMerger.h
The file was modifiedllvm/include/llvm/DebugInfo/PDB/Native/TpiStream.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/LazyRandomTypeCollection.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/CVRecord.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/CVSymbolVisitor.h
The file was modifiedllvm/lib/DebugInfo/CodeView/TypeIndexDiscovery.cpp
The file was modifiedllvm/unittests/DebugInfo/CodeView/TypeHashingTest.cpp
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/CodeViewRecordIO.h
The file was modifiedllvm/include/llvm/DebugInfo/CodeView/TypeRecord.h
Commit 738c73a454881ca78214816754c1b82941d0cd26 by Matthew.Arsenault
RegAllocFast: Make self loop live-out heuristic more aggressive

This currently has no impact on code, but prevents sizeable code size
regressions after D52010. This prevents spilling and reloading all
values inside blocks that loop back. Add a baseline test which would
regress without this patch.
The file was addedllvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
Commit 39faf428164a28f3652370958ce893d9200927c8 by Louis Dionne
[libc++] Ensure streams are initialized early

When statically linking libc++ on some systems, the streams are not
initialized early enough, which causes all kinds of issues. This was
reported e.g. in http://llvm.org/PR28954, but also in various open
source projects that use libc++.

Fixes http://llvm.org/PR28954.

Differential Revision: https://reviews.llvm.org/D31413
The file was modifiedlibcxx/src/iostream.cpp
The file was addedlibcxx/test/std/input.output/iostream.objects/init.pass.cpp
Commit f9e6d1edc0dad9afb26e773aa125ed62c58f7080 by anhtuyen
Re-land: Add new hidden option -print-changed which only reports changes to IR

A new hidden option -print-changed is added along with code to support
printing the IR as it passes through the opt pipeline in the new pass
manager. Only those passes that change the IR are reported, with others
only having the banner reported, indicating that they did not change the
IR, were filtered out or ignored. Filtering of output via the
-filter-print-funcs is supported and a new supporting hidden option
-filter-passes is added. The latter takes a comma separated list of pass
names and filters the output to only show those passes in the list that
change the IR. The output can also be modified via the -print-module-scope
function.

The code introduces a template base class that generalizes the comparison
of IRs that takes an IR representation as template parameter. The
constructor takes a series of lambdas that provide an event based API
for generalized reporting of IRs as they are changed in the opt pipeline
through the new pass manager.

The first of several instantiations is provided that prints the IR
in a form similar to that produced by -print-after-all with the above
mentioned filtering capabilities. This version, and the others to
follow will be introduced at the upcoming developer's conference.

Reviewed By: aeubanks (Arthur Eubanks), yrouban (Yevgeny Rouban), ychen (Yuanfang Chen)

Differential Revision: https://reviews.llvm.org/D86360
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp
The file was modifiedllvm/include/llvm/Passes/StandardInstrumentations.h
The file was modifiedllvm/lib/IR/LegacyPassManager.cpp
The file was addedllvm/test/Other/change-printer.ll
Commit 50f4c7c785da87679fac1f483ef6a3e53dfca37a by i
[llvm-nm] Use aggregate initialization instead of memset zero
The file was modifiedllvm/tools/llvm-nm/llvm-nm.cpp
Commit b011611e373c3d6dfddde5120ce7974cc8719d4a by spatel
[SLP] add tests for reduction ordering; NFC
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
Commit c6a82fdbf2ea691fdaf70fb07ae1f61d8452e1ac by llvm-dev
ValueEnumerator.cpp - remove duplicate includes. NFCI.

Remove headers already included in ValueEnumerator.h
The file was modifiedllvm/lib/Bitcode/Writer/ValueEnumerator.cpp
Commit 69682f993cc0545da30be32fab572a2a56074653 by llvm-dev
InterferenceCache.cpp - remove duplicate includes. NFCI.

Remove headers already included in InterferenceCache.h
The file was modifiedllvm/lib/CodeGen/InterferenceCache.cpp
Commit 73d02064d2533daecf6fe82b8608da8f6eed59a5 by llvm-dev
raw_ostream.cpp - remove duplicate includes. NFCI.

Remove headers already included in raw_ostream.h
The file was modifiedllvm/lib/Support/raw_ostream.cpp
Commit 8f7d6b2375618a79f621d5484e44870ede335a13 by llvm-dev
DwarfUnit.h - remove unnecessary includes. NFCI.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
Commit c4e589b7954c4e202474ce4a2101f07014792835 by mkitzan
[GISel] Add new combines for unary FP instrs with constant operand

https://reviews.llvm.org/D86393

Patch adds five new `GICombinerRules`, one for each of the following unary
FP instrs: `G_FNEG`, `G_FABS`, `G_FPTRUNC`, `G_FSQRT`, and `G_FLOG2`. The
combine rules perform the FP operation on the constant operand and replace
the original instr with the result. Patch additionally adds new combiner
tests for the AArch64 target to test these new combiner rules.
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
The file was modifiedllvm/include/llvm/CodeGen/LowLevelType.h
The file was modifiedllvm/lib/CodeGen/LowLevelType.cpp
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
Commit ebf267b87d4b557dff488f87f66df3628e3da957 by zequanwu
[Sema][MSVC] warn at dynamic_cast/typeid when /GR- is given

Differential Revision: https://reviews.llvm.org/D86369
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was addedclang/test/SemaCXX/no-rtti-data.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticGroups.td
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaCast.cpp
The file was addedclang/test/SemaCXX/ms-no-rtti-data.cpp
Commit f3c2e0bcee64b0905addaefe9cd0c9ad4d20ac6f by mascasa
[libFuzzer] Enable entropic by default.

Entropic has performed at least on par with vanilla scheduling on
Clusterfuzz, and has shown a slight coverage improvement on FuzzBench:
https://www.fuzzbench.com/reports/2020-08-31/index.html

Reviewed By: Dor1s

Differential Revision: https://reviews.llvm.org/D87476
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerOptions.h
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerFlags.def
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerDriver.cpp
The file was modifiedcompiler-rt/test/fuzzer/cross_over_uniform_dist.test
The file was modifiedcompiler-rt/test/fuzzer/keep-seed.test
Commit 77a01d9498a79d2e6e3f366fdb363928f188ec11 by Saleem Abdulrasool
Sema: add support for `__attribute__((__swift_bridge__))`

This extends semantic analysis of attributes for Swift interoperability
by introducing the `swift_bridge` attribute.  This attribute enables
bridging Objective-C types to Swift specific types.

This is based on the work of the original changes in
https://github.com/llvm/llvm-project-staging/commit/8afaf3aad2af43cfedca7a24cd817848c4e95c0c

Differential Revision: https://reviews.llvm.org/D87532
Reviewed By: Aaron Ballman
The file was addedclang/test/AST/attr-swift_bridge.m
The file was addedclang/test/SemaObjC/attr-swift_bridge.m
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
Commit 4d437348d24d6342bdeb3ad84a64e57a889a0ea2 by zequanwu
fix test no-rtti.cpp
The file was modifiedclang/test/SemaCXX/no-rtti.cpp
Commit 4d4f0922837de3f1aa9862ae8a8d941b3b6e5f78 by michael.hliao
[clang][codegen] Skip adding default function attributes on intrinsics.

- After loading builtin bitcode for linking, skip adding default
  function attributes on LLVM intrinsics as their attributes are
  well-defined and retrieved directly from internal definitions. Adding
  extra attributes on intrinsics results in inconsistent result when
  `-save-temps` is present. Also, that makes few optimizations
  conservative.

Differential Revision: https://reviews.llvm.org/D87761
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
The file was addedclang/test/CodeGenCUDA/dft-func-attr-skip-intrinsic.hip
The file was addedclang/test/CodeGenCUDA/Inputs/device-lib-code.ll
Commit 6ad33d8360335143ef50e7f7b66ae1ce17aaa2a5 by Amara Emerson
[AArch64][GlobalISel] Make G_BUILD_VECTOR os <16 x s8> legal.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit b3d33f5e838f8a181feb391fc96e74e3bb6be110 by thakis
[gn build] make "all" target build

If you want to build everything, building the default target
via just `ninja` is better, but `ninja all` shouldn't give you
compile errors -- this fixes that.
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/scudo/BUILD.gn
Commit 88bdcbbf1aaef6ac99877cc511bf4b2a85343773 by Matthew.Arsenault
GlobalISel: Lift store value widening restriction

This doesn't change the memory size and doesn't need to worry about
non-power-of-2 sizes.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir