Started 1 mo 9 days ago
Took 2 hr 13 min

Success Build clang-d366533-g05d4c4ebc2f-t14620-b14620.tar.gz (Sep 17, 2020 2:06:10 PM)

Issues

No known issues detected

Build Log

Changes
  1. [X86] Don't match x87 register inline asm constraints unless the VT is floating point or its a clobber (details)
  2. [VectorCombine] limit load+insert transform to one-use (details)
  3. [AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal for shifts. (details)
  4. [AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b. (details)
  5. [PDB] Split TypeServerSource and extend type index map lifetime (details)
  6. [SVE][WIP] Implement lowering for fixed length VSELECT to Scalable (details)
  7. [IRSim] Adding IR Instruction Mapper (details)
  8. [gn build] Port 7e4c6fb8546 (details)
  9. AArch64::ArchKind's underlying type is uint64_t (details)
  10. [Lsan] Use fp registers to search for pointers (details)
  11. Disable hoisting MI to hotter basic blocks when using pgo (details)
  12. [SCEV] Add test cases for max BTC with loop guard info. (details)
  13. [GVN] Add additional assume tests (NFC) (details)
  14. [GVN] Use that assume(!X) implies X==false (PR47496) (details)
  15. [LoopUnrollAndJam] Allow unroll and jam loops forced by user. (details)
  16. [InstCombine] Canonicalize SPF_ABS to abs intrinc (details)

Started by upstream project relay-test-suite-verify-machineinstrs build number 8968
originally caused by:

This run spent:

  • 1 hr 37 min waiting;
  • 2 hr 13 min build duration;
  • 2 hr 13 min total from scheduled to completion.
Revision: 3b3349e94a30eb9608e44f335ba74119311d714c
  • refs/remotes/origin/master
Revision: 05d4c4ebc2fb006b8a2bd05b24c6aba10dd2eef8
  • detached
Revision: 61eaf8a9eccf4edbef18f55593d1095254ed3ff5
  • refs/remotes/origin/master
Revision: 9771b578de06f96603e20ee6e0f76ee1f0b59d2f
  • refs/remotes/origin/master